From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9F9B1DE4D8; Sat, 19 Oct 2024 11:50:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338651; cv=none; b=NZLS9Vg6O2mby4OIeiufE8eDoWAtH0VXHfpJhMdRxmiFBeHnrxf32USV4jpu2pcauoE1dsQErS0OZqsmJ0jxDxBoCwpwDgT+82AAvbZnni6jtVnXr0yUrIcxs+z63ilfKjKliJUgw9J9cxKEph+QWQs2C4zSQ1gF2XW8NdOEHY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338651; c=relaxed/simple; bh=WQ5LcC5dxomf+Jk8o6tbrfygW77imH/aaZDIzSsjPZM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EC6dgiQQLSAHtZiFjwbXOruzNSrZ9RZA4TblelqOPGBozyxYtSLkF5C9+COWqVfVfyeU7K/hUgd+mUWzVAojyoS5HNQLoSNWWb4ECnoIexAOf96Z8e4cFZ1PE8lKy19EOXFNLeYid9UbR4j+luGEUwF4qzt17wcsNWh7TSoxe48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=Dzl/peBA; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="Dzl/peBA" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 8E8A9E459D; Sat, 19 Oct 2024 11:50:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338642; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q8cvryaZPKYiI0Nyj6A8ssk4KjXnZlrTtmSMkN+/r2k=; b=Dzl/peBADOvEWtYvEcgR0HdIs230YvCiAK8U9ujq8ZuTSFA+qXTue7gg6/7JDF2I9FheEW MbRThb8thwZy6h2gAolyWffomDeg42fFJ+hKXamJ/4us8ORJtLiYG0pWyvVlMuK5o4M4cr nLEPnS2PAAPS2gsq9pTNDk7C5+OPMlbBGsmkyKPG6iKp6b5uA3EI2CmbddQc0GFGkLNBU1 jNoX5wkrX09WHWGCVQmFrZQfvZkFPX/uE8mlURBadEH6hSaWSa3Uf85hm3UCzkzKr6fVlq sSZixrSBnzz1HoBwEKP4enVX8D0pu4zmjHm8n5MLME8sBzUN08ueuiq/hFvXjg== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:38 +0200 Subject: [PATCH RFC 01/14] dt-bindings: pinctrl: qcom,pmic-gpio: add PM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-1-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=1585; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=WQ5LcC5dxomf+Jk8o6tbrfygW77imH/aaZDIzSsjPZM=; b=f0IA5PHv7MnjhaEhvKgo5IuG1YbuSqNz+AQYQbX8T/8jJmY0r0y9k9sXToJfDUBhE1LF/Uw8Y 2OE2FCXyCZiCM5zHZTqR3/9RraAOHiPTFes5Q0PRnRBvrUCtRc/OEP1 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the 8 GPIOs found on PM8937. It has holes on 3,4 and 6 pins. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml = b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index c1b799167d81b0b4e1edff6a6fce557fa88fd1ea..055cea5452eb62ab6e251a3a919= 3d1e5da293ccb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -48,6 +48,7 @@ properties: - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio + - qcom,pm8937-gpio - qcom,pm8941-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio @@ -184,6 +185,7 @@ allOf: - qcom,pm8226-gpio - qcom,pm8350b-gpio - qcom,pm8550ve-gpio + - qcom,pm8937-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio - qcom,pmi632-gpio @@ -468,6 +470,7 @@ $defs: - gpio1-gpio6 for pm8550vs - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 + - gpio1-gpio8 for pm8937 (hole on gpio3, gpio4 and gpio6) - gpio1-gpio36 for pm8941 - gpio1-gpio8 for pm8950 (hole on gpio3) - gpio1-gpio8 for pm8953 (hole on gpio3 and gpio6) --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D28F31E049C; Sat, 19 Oct 2024 11:50:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338652; cv=none; b=SmBTcHskgRNBS0801Qr+j/9BRc8FRzDKx9+GeNYvjd1LMF2p0R16OrqLx8q2+NRyDeRYw+KefxleMEbKLnUqx2PxOccNiTezuawwyUxX9plgNXVR2CHfFJ0GK2TRlpUSV8PfCgEJwpUTOvMvj/2r/vSOygCdETfBYqHQx1IBMRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338652; c=relaxed/simple; bh=lD7Z5J16+ZW7jj0xA29KakGtzo/Qo18WuBFRIMXCgUw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z/pZmztlzi0NCifDIApTcOjjJ2HvhUezDQ3HhpC+P6Kd7tehSHuDD6k7jw5L5KZ0IiFkTRZ2wTiDM+psMnJWdBWypf8L/h/M0m0XhlOnUFHIGLvURFkHaItL6DMPkWbWJNRj8PubQwJwQz94ia/hfaUvzWACYkobvUhfGDAaKRI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=cRL2yetM; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="cRL2yetM" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 45402E459E; Sat, 19 Oct 2024 11:50:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338642; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=84UkJxh0Dni49KkElyBD9QL3bGo5S0yZi1HX4sLA6Es=; b=cRL2yetMc8SmhpXr6wkmi1x/wALsWy4EFMSKbcqdUVinhaEmgMw0L/MKp3gYVQdm1UQUCK clotp6hq/OV+AYAg1fzkGRskDc+sQGq04vOZ4hbUn7IhCz+Xd74UA0bagjxzG/IZ5UBLoN 9IPa5UXef+lTepe3yagdqKpu7dLL5/SnhwqyuRyF6S1vqExiL4+LFdTW/cSMASKpzCJPTC R+sTHYLpjq0VoWP3au4bM1OPwHf+fgc7ZKIuH5QZikAjbaicNz/SDhTy8UiCcInqK7FNal JZZtPVDzjDS8UPQiWV3Yute8PD8ntGYSFTmuki+3XzYkYZd+N3fq04UEsLKJlg== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:39 +0200 Subject: [PATCH RFC 02/14] pinctrl: qcom-pmic-gpio: add support for PM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-2-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=1075; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=lD7Z5J16+ZW7jj0xA29KakGtzo/Qo18WuBFRIMXCgUw=; b=wBsmI82ji2gGlqWChhszxmibZWvyY8BDUS5pQRj8cEcI7aZBalWK2NDTRmGpqdbQfO40cowY+ 0t4yDlP/1CMApp/tmqx3Erk67q1yS8cXrOEiPdWceCOFKRqz8RObwSL X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= PM8937 has 8 GPIO-s with holes on GPIO3, GPIO4 and GPIO6. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qco= m/pinctrl-spmi-gpio.c index c33af2d6677846a4c43fc817e7b01621ab220890..b1140eaecd32de90e4ae2eafb1d= 0e0ec939e24bf 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1226,6 +1226,8 @@ static const struct of_device_id pmic_gpio_of_match[]= =3D { { .compatible =3D "qcom,pm8550ve-gpio", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8550vs-gpio", .data =3D (void *) 6 }, { .compatible =3D "qcom,pm8916-gpio", .data =3D (void *) 4 }, + /* pm8937 has 8 GPIOs with holes on 3, 4 and 6 */ + { .compatible =3D "qcom,pm8937-gpio", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8941-gpio", .data =3D (void *) 36 }, /* pm8950 has 8 GPIOs with holes on 3 */ { .compatible =3D "qcom,pm8950-gpio", .data =3D (void *) 8 }, --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84B561E0B66; Sat, 19 Oct 2024 11:50:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338654; cv=none; b=ayZvYtRZ1Vo2HENdEm2cRJ5Na1bHQBgiFkxaYRx7E+hiuj800Ro92G2+xudKHz5nZbE+w6+5Fu6VNkh/hVEWnull/a/l2opwCe5GseDNhPY8nlgZYLKbJGn+g3WUTzufinghUbu7Oh51MVYgUyQbcSqqL988x1/sW8umyLBpQb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338654; c=relaxed/simple; bh=kANJbusz/1wsoZAzBf9MgUzpPoVv15jJLK4rJBNHHIw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aitDxMCUExKnCXvBakLgPWiFvxN2VsoPdTbww4CTNM/ZBdTUXeGXcJ/+nAzhK7kFd7CY5pRykhRdIgBZ/r4bCf+p0fau6zZfSqHPvGiy5Lg1TZMU/IVE+IAayUrgQFCJ2kHwX0Ff6SM46ZAp2ZHmCx5SKdYjk00ctR0LLAlcN6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=AXY6qiyP; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="AXY6qiyP" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 1CE55E459F; Sat, 19 Oct 2024 11:50:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338643; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PoFhgvV9a9kora5JIHDRkULnX8QqLWjcJwM1ZxNV22U=; b=AXY6qiyPCQ77l35uzMpOoiDG70WUJTNJidpdjX4Fibi4TGU9Ga7KJDrbNKDREcJtPCYjuJ eBrb/fYje/P/UWLHlzcFyIki5mhExUCrNrWyth+QTLnoC1pg+n9gXtdaS2spf4DyxCysSY kbOmmrg1XNPYRpKEA1thMGXP4sC/HGh/EQeCq0gye3H+9WjfGJ26MV3mYPpuisG2pPVjpM lpfs1s9YHQ800yUQGRzWDCh6r13UA5Q5/WQdNb4KlvdjRRaHIzVGtInJKvSnmFjjM8rTzQ g35lNbhL/tDQ8eCIr4WN6wDi/qscnngVyhA+Lm/jEJxzjdP9Y68UxbOdzSnRaQ== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:40 +0200 Subject: [PATCH RFC 03/14] dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8937 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-3-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=1209; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=kANJbusz/1wsoZAzBf9MgUzpPoVv15jJLK4rJBNHHIw=; b=Lc6quThl4hMz+nKEIqPddVDf0/5bSQxarhJmpvvTABs2NAA8TgC7b77d0PQqBTZ/kYBjgch3v eJNCvtHQyNLAyyC7qav2Ff9TLwNTbNShKe1MG7e0/6KqDES6x96rQ3x X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the Device Tree binding for PM8937 MPPs. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b= /Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 43146709e2044d9dead08a6786b98672ef766629..9364ae05f3e68f3a2f4dd78ba3c= 0f94b3ccc3c51 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -22,6 +22,7 @@ properties: - qcom,pm8226-mpp - qcom,pm8841-mpp - qcom,pm8916-mpp + - qcom,pm8937-mpp - qcom,pm8941-mpp - qcom,pm8950-mpp - qcom,pmi8950-mpp @@ -92,6 +93,7 @@ $defs: this subnode. Valid pins are - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 + - mpp1-mpp4 for pm8937 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84C1B1E0B6A; Sat, 19 Oct 2024 11:50:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338653; cv=none; b=KCzaptQhvyLXJf4OrjWGe1ONT9of5MioGUifGJTv8QS0ra6me8xmNW/edByzc4+3ckKeodpUHE7Y3GPtKBLGqyXsHYStQJwXnh8d9vwdk3MEdXkNf7YzMPriKtteLD9QcQD0nMwsN+2z2pW58wDKHQBtWnifuMN86i9Kh/RcvSg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338653; c=relaxed/simple; bh=cDWauIFOhCPNbwkCVY3LkMwztyH8z561yVG1fYO4mVA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f0iJqd50rH23WRk2NtBxa9dhgGGevgGkv6GNlCrwwK8/7icxloTzI4kr5PtSPJMY/U64qF9AXKMIJZrEI6n4+1BwOqSzUVuLCxBawAir9QXRzTjHBgY1dMWDY08UbvE+xWr1SZkgZxqwDP3g4nmIpYfDTDdsXCMpxmRdJPTIMX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=iy/mKOQN; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="iy/mKOQN" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id C43E8E45A0; Sat, 19 Oct 2024 11:50:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338644; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jnmFf/TpFXfbNZ2S1IT03EPJKNClcoQzc2cdpLaxzbE=; b=iy/mKOQNv/w8rWL1e4vUd09XTDszMSJNBGwzpos1KfBdcAYEMfpJgXJWRKKPyKs0H4Ad1O ZhPniovDiOGsmNim3vrmHFuVM+R6r9wEhnCzzNt7T+6iNpSGUQ4QjMZ/J7jKay9ZcNLSJj JoQePMExnEwlmIR07pzyWmkhG37BIlEng6loWREnoUfyuc5fUTpSsvc/8IPtYMLrlBiKVV XOZgdAVVbjCOd7clk5vVqZ5SDPKfidBMgnQGoBtM43/H/zTfPj3dJee6P9EunOijtPxyyc IhS91X0JOmYTAc6/zlNLKrX8ABk3Al9KJ+3GIGtkc92gPsGt6feZgAXh9b3xoA== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:41 +0200 Subject: [PATCH RFC 04/14] pinctrl: qcom: spmi-mpp: Add PM8937 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-4-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=1023; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=cDWauIFOhCPNbwkCVY3LkMwztyH8z561yVG1fYO4mVA=; b=9L8g6ZfQQ3E3qOqsanyM3Zu0oNP0L/K8rbxg5zpTgtvqTTmff8R3EPmxNeg1d43ZNAK8+5786 CkGyD3O1erbBBUM2tU18HFoq1tnuy0EuCqjFnsRtN4n6WioYmmg2GB3 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= The PM8937 provides 4 MPPs. Add a compatible to support them. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom= /pinctrl-spmi-mpp.c index b5b3ac82f030b55f9e199bb4265c770cfde4a81a..84de584cf7ebbd35dd3e7aa89d4= b971645b02f82 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -983,6 +983,7 @@ static const struct of_device_id pmic_mpp_of_match[] = =3D { { .compatible =3D "qcom,pm8226-mpp", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8841-mpp", .data =3D (void *) 4 }, { .compatible =3D "qcom,pm8916-mpp", .data =3D (void *) 4 }, + { .compatible =3D "qcom,pm8937-mpp", .data =3D (void *) 4 }, { .compatible =3D "qcom,pm8941-mpp", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8950-mpp", .data =3D (void *) 4 }, { .compatible =3D "qcom,pmi8950-mpp", .data =3D (void *) 4 }, --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08B9B1E0B86; Sat, 19 Oct 2024 11:50:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338654; cv=none; b=qo/YlXxsrStfsFguvBiLvHHuLdeC/Gh9Px0ClpSAekIKvM1Sz7ImP+hyDAUAyI4cyDKKAD94qjGIJjH2mmSLlDWRQC3bpDiAAH1j1lD9JedE96ekDCHjSumagmyPHRZKtXhYFR6CWcNIorEG/iKpJ2c5yVsvitC60sbOyt35SOM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338654; c=relaxed/simple; bh=pGdE3JbMnx8RRxsOjP5sqLKvgYxJu9uHccWmmEz1BBY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RUOLzVBMCWdxfZ+31NaVG7z9FcKB0E1UWU4jsPIaAJhY7/4h6uYf4QIabnxK44u9TGjafujK375ZANR332cDINKo+EBUL+ouwv3KzfQkTVUrhCfo55FLJw77Y2890S73ngoYTtNp7J50NTrk3B6Tj6xf9u2NJYKCQb46MK3n2CA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=Q2hAG+P4; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="Q2hAG+P4" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 828B3E45A1; Sat, 19 Oct 2024 11:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338645; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WQ9PPHmGUCj1OfdVnwY9QeNORTy83vI8ai4ibJSzc/c=; b=Q2hAG+P4c8TrGbiSjBC1zGAbkAkJ3yNjfwStF1K0OGwtR+Ofw5hydon04iBcqFnG4DI+JV r490OspTQWNiA5aAOrmXjQTRSgc/KVB7qJBHReU0xNYKDrVDdLjCZef3mu+HbNRKpJ/iqW BLDmiYstEtZnsHcYf3SCAwEHq2uNxfbMZfWL25BinwQ7QN8ANYvvHnIhLswnhSAattReI0 OsCRjzpj6hyMxq/JHG2FUGnFikoeV3NNEwNvThy5w0RLaCa/aOvFy72ks2lbseXaiNHrqq jejsk1uadvIhEN5093WeFPy3DRdzHeHp/hJn9Um+JD6kK3Zz76WH57yhFq/QTQ== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:42 +0200 Subject: [PATCH RFC 05/14] arm64: dts: qcom: Add PM8937 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-5-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Dang Huynh , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=5605; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=lHNnzvmjpc3j5FxTFCw87+ln8lcsQMaGeUUUPNMlpb0=; b=O0m30iyb8Hz6BbiCNwy6EFGh5ivkIuduYzKXzebEytblgLjuwVv44KEwNqTpwjFfDAo181g9d kwKYqLpPPxaAlU9UGBZGSbsDLmWkqzx6Ehr9aXSKA5tJZIEsyK62vuH X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dang Huynh The PM8937 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add the device tree so that any boards with this PMIC can use it. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dang Huynh Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/pm8937.dtsi | 216 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 216 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8937.dtsi b/arch/arm64/boot/dts/qco= m/pm8937.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..34e2b4cd0d5f4f92c16bb20f53e= 4520544a644bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8937.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Dang Huynh + */ + +#include +#include +#include +#include +#include + +/ { + thermal-zones { + pm8937-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&pm8937_temp>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + + trip2 { + temperature =3D <145000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@0 { + compatible =3D "qcom,pm8937", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pon@800 { + compatible =3D "qcom,pm8916-pon"; + reg =3D <0x800>; + mode-bootloader =3D <0x2>; + mode-recovery =3D <0x1>; + + pm8937_pwrkey: pwrkey { + compatible =3D "qcom,pm8941-pwrkey"; + interrupts =3D <0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce =3D <15625>; + bias-pull-up; + linux,code =3D ; + }; + + pm8937_resin: resin { + compatible =3D "qcom,pm8941-resin"; + interrupts =3D <0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce =3D <15625>; + bias-pull-up; + status =3D "disabled"; + }; + }; + + pm8937_gpios: gpio@c000 { + compatible =3D "qcom,pm8937-gpio", "qcom,spmi-gpio"; + reg =3D <0xc000>; + gpio-controller; + gpio-ranges =3D <&pm8937_gpios 0 0 8>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pm8937_mpps: mpps@a000 { + compatible =3D "qcom,pm8937-mpp", "qcom,spmi-mpp"; + reg =3D <0xa000>; + gpio-controller; + gpio-ranges =3D <&pm8937_mpps 0 0 4>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pm8937_temp: temp-alarm@2400 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0x2400>; + interrupts =3D <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pm8937_vadc VADC_DIE_TEMP>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pm8937_vadc: adc@3100 { + compatible =3D "qcom,spmi-vadc"; + reg =3D <0x3100>; + interrupts =3D <0 0x31 0 IRQ_TYPE_EDGE_RISING>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + + channel@5 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "vcoin"; + }; + + channel@7 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "vph_pwr"; + }; + + channel@8 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "die_temp"; + }; + + channel@9 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_625mv"; + }; + + channel@a { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_1250mv"; + }; + + channel@c { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_buf_625mv"; + }; + + channel@e { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_gnd"; + }; + + channel@f { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_vdd"; + }; + + channel@11 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + label =3D "pa_therm1"; + }; + + channel@13 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + label =3D "case_therm"; + }; + + channel@32 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + label =3D "xo_therm"; + }; + + channel@36 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + label =3D "pa_therm0"; + }; + + channel@3c { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + label =3D "xo_therm_buf"; + }; + }; + + rtc@6000 { + compatible =3D "qcom,pm8941-rtc"; + reg =3D <0x6000>, <0x6100>; + reg-names =3D "rtc", "alarm"; + interrupts =3D <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pmic@1 { + compatible =3D "qcom,pm8937", "qcom,spmi-pmic"; + reg =3D <0x1 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8937_spmi_regulators: regulators { + compatible =3D "qcom,pm8937-regulators"; + }; + }; +}; --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25AC31E0B90; Sat, 19 Oct 2024 11:50:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338655; cv=none; b=NpFg+VHaYuzX8ez7d6TOtKP7xpZa1ClOT4I1qjlX6FclIvsgOzymGY7tZgfnVpTvvwUrOlVWOKqVt284UkOVuRFrlxjHYUHkxxeBCoold+XEXVs4gsk97ZIzy18PmyUU1dfLtQBpULdkxRiTw+6Kllo4jYVc1K+aD1crD1isW/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338655; c=relaxed/simple; bh=nKRAjGHplcBjSY8FGUHOTB8ghGJrx7beTyIEn7gCe/4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oKFtffj5Lu9vwKErDheLbHG8skSchSWDIoBB3d1/IOyZKnvamRetzX0ZOix82DKuYgOhhyT5tCZQaU587ftSrmdbqI1MaVMjLxm77E4am+0+7KRxdmhmR0ZdmFfmkFc2tTrdr8b2wqTqMtisMiA9GWqVc1eWms9N722Q6jCl4IA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=VHFgg5HR; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="VHFgg5HR" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 4ACCAE45A2; Sat, 19 Oct 2024 11:50:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338645; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Olj9iYH7LcbphKshwr7qao2rM+CM/q0woKUYsmasCt4=; b=VHFgg5HRelXRx4/0GeYJYtiz7nwdpx54jfSybbwcPDW+lQuyiluE4JQHMWWaFi04qhUR7c Y2lPWs4SpSJtVy0kCNtIEPpoK0ULqsLsUr8INnkBcFFhZKyBwu1xk4/wtcSOvBRe2FiZHa i/CBFWEdmwZHe5P2iZWNTgnzGJ1c8/wiHMyI0d0lKjqHyinckE39Z064dNIfgRU1vKKeki HD4mHF5dxAK8oJW8VOq9SVB9Q0tcpF3aatxJUIVu2lTwdIhNqKF+BPppMDodzlulyEqD9g k9GTSybtCd6WC0HjW3xqtnV7iAd5uPNvQKwI+7ZtSJ+ke3JQ9aq0//suKr6wzA== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:43 +0200 Subject: [PATCH RFC 06/14] dt-bindings: pinctrl: qcom: Add MSM8917 pinctrl bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-6-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=6514; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=nKRAjGHplcBjSY8FGUHOTB8ghGJrx7beTyIEn7gCe/4=; b=SBR0UiMI0qHJlKfLm+epe47EkvvVA+1HiDd+BDkKcox8Se5LV4+xWYcw4aCRXHdDIvLAqFpU4 qSN69ovB04eDjQoi2Celt+VeQs7cmEG/tp9ft5/bEWvq2c3lFybP6nR X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add device tree bindings documentation for Qualcomm MSM8917 pinctrl driver. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- .../bindings/pinctrl/qcom,msm8917-pinctrl.yaml | 155 +++++++++++++++++= ++++ 1 file changed, 155 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..41349ce9898aaaf68a10f30ffe6= 11dcedc1e9311 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8917-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8917 TLMM pin controller + +maintainers: + - Barnabas Czeman + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8917 SoC. + +properties: + compatible: + const: qcom,msm8917-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8917-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8917-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8917-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, + qdsd_data1, qdsd_data2, qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + + enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, + atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_combodac_to_gpio_native, + atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, + atest_tsens, atest_wlan0, atest_wlan1, audio_ref, + audio_reset, bimc_dte0, bimc_dte1, blsp6_spi, blsp8_spi, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, + blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, blsp_spi2, + blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, + blsp_spi8, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, + blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, cam0_ldo, + cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam_mclk, + cci_async, cci_i2c, cci_timer0, cci_timer1, cdc_pdm0, + codec_int1, codec_int2, codec_mad, coex_uart, cri_trng, + cri_trng0, cri_trng1, dbg_out, dmic0_clk, dmic0_data, + ebi_cdc, ebi_ch0, ext_lpass, forced_usb, fp_gpio, fp_int, + gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, + gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, + gsm0_tx, key_focus, key_snapshot, key_volp, ldo_en, + ldo_update, lpass_slimbus, lpass_slimbus0, lpass_slimbus1, + m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, nav_pps, + nav_pps_in_a, nav_pps_in_b, nav_tsync, nfc_pwr, ov_ldo, + pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_mclk_a, + pri_mi2s_mclk_b, pri_mi2s_ws, prng_rosc, + pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_= a, + pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a= 1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_= a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, sd_write, sdcard_det, + sec_mi2s, sec_mi2s_mclk_a, sec_mi2s_mclk_b, sensor_rst, + smb_int, ssbi_wtr1, ts_resout, ts_sample, uim1_clk, + uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, uim_batt, us_emitter, us_euro, + wcss_bt, wcss_fm, wcss_wlan, wcss_wlan0, wcss_wlan1, + wcss_wlan2, webcam_rst, webcam_standby, wsa_io, wsa_irq ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8917-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi1-default-state { + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "blsp_spi1"; + + drive-strength =3D <12>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio2"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + }; --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC96C1E0E08; Sat, 19 Oct 2024 11:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338658; cv=none; b=FTXH7gxh8hupLoLYmN7tG7YvG/hgtEqkuiS7zR5Z/fjTQwVYgSptBa+lmCmarLaUvLcjV2e5QeUndfhNmVgJ6nAyYcyjsRVe42q2E244CtXcRk1LcbYkRIUBxKGHheldUjnzOoXl33R3MGhKIxvTTWWAluSrxr0jwmCOWIDlPbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338658; c=relaxed/simple; bh=DZt9TOuSabNqZrkZyP7/uKYYv4Yzx7jqrUzjx+UqoKo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nC7FOaOipbp5ldC3uoZrW9CJrsBC++FPbYEYIYo7q0qinlaA3rmMM19vT4F8vfJIBwXWf/oE5sbCvThP222a6BdGHORZCMB6feX9rVwVM1NKUqhfUE4kSMCCsiwsnLJHwKTdThfgjIf3MT4NLMSRiEmFqs1fpxxrWZ0N9O+BrUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=jvgJcWrC; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="jvgJcWrC" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 3C7B8E45A3; Sat, 19 Oct 2024 11:50:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338646; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6u7KL9/t52kTf2pdWRreZ6xel52XUm+OQAGufHT9BFI=; b=jvgJcWrCDMvQBOxG8UANlZa6d7LBEKhynH0RyVzGTYBzoDuFSl20EuOzJPLa3sNEVAP7HZ XMS1ewRTEfnwOYUXFNr8KE8tF1EyrufIXRCNu48Huw49d+RRWqZI92/c9wjRMDDcYoJcUO 7lCeIQMM1IjkimScHL3nwdMCiSuC+GOlFrPDjCPQ+ew/ozOZ+h8aePrJrMSwJOzHBYjsf9 j9hg+A9LrFO6fNYb3dF/J51Cc9T4XpKWzbVGlQiqA7Ob8BtBa72Brg8X1yCNo4Ip8xNvWm ullQ3MPdpO5HqQZqi7MLV0y2X7MGxqvWwdIbPz4SkyLY+AKUx+l4ykrUUFeFTA== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:44 +0200 Subject: [PATCH RFC 07/14] pinctrl: qcom: Add MSM8917 tlmm pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-7-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=49795; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=guCdWWX5n1lXVui3Lz3Ki1pxpDgRv27m8fhq/Sj03r0=; b=uaOPCpI0piB3h3fI3mttVjKzXlYsWdjX5PkYEI2trQSp1w3Y7/YS8XTCip2VHMO8Z/WxrgkZE KVLF6p7TXFsC6u8aHirzc+Fj2/jAK07Gptdq38rEK2niu76K5Q8Ydv4 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Otto Pfl=C3=BCger It is based on MSM8916 driver with the pinctrl definitions from Qualcomm's downstream MSM8917 driver. Signed-off-by: Otto Pfl=C3=BCger Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- drivers/pinctrl/qcom/Kconfig.msm | 6 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-msm8917.c | 1622 ++++++++++++++++++++++++++++= ++++ 3 files changed, 1629 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index c79f0c3c873da56e8c0e1de9f91bce4b552221d2..f53043ea213012447aaaf07e9f3= 39a16493a1b95 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -137,6 +137,12 @@ config PINCTRL_MSM8916 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. =20 +config PINCTRL_MSM8917 + tristate "Qualcomm 8917 pin controller driver" + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm 8917 platform. + config PINCTRL_MSM8953 tristate "Qualcomm 8953 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 715c3b5a636ad6a1b07b4160f4336b5c70a8f2e3..268264ea87aa9dd37d27ca7944e= 0bf4e674e8132 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MSM8960) +=3D pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) +=3D pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8909) +=3D pinctrl-msm8909.o obj-$(CONFIG_PINCTRL_MSM8916) +=3D pinctrl-msm8916.o +obj-$(CONFIG_PINCTRL_MSM8917) +=3D pinctrl-msm8917.o obj-$(CONFIG_PINCTRL_MSM8953) +=3D pinctrl-msm8953.o obj-$(CONFIG_PINCTRL_MSM8976) +=3D pinctrl-msm8976.o obj-$(CONFIG_PINCTRL_MSM8994) +=3D pinctrl-msm8994.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/= pinctrl-msm8917.c new file mode 100644 index 0000000000000000000000000000000000000000..101baf6d7f8e446bd9045487eea= 8c810dbc0db5a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c @@ -0,0 +1,1622 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8917_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "SDC1_CLK"), + PINCTRL_PIN(135, "SDC1_CMD"), + PINCTRL_PIN(136, "SDC1_DATA"), + PINCTRL_PIN(137, "SDC1_RCLK"), + PINCTRL_PIN(138, "SDC2_CLK"), + PINCTRL_PIN(139, "SDC2_CMD"), + PINCTRL_PIN(140, "SDC2_DATA"), + PINCTRL_PIN(141, "QDSD_CLK"), + PINCTRL_PIN(142, "QDSD_CMD"), + PINCTRL_PIN(143, "QDSD_DATA0"), + PINCTRL_PIN(144, "QDSD_DATA1"), + PINCTRL_PIN(145, "QDSD_DATA2"), + PINCTRL_PIN(146, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } + +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); + +static const unsigned int sdc1_clk_pins[] =3D { 134 }; +static const unsigned int sdc1_cmd_pins[] =3D { 135 }; +static const unsigned int sdc1_data_pins[] =3D { 136 }; +static const unsigned int sdc1_rclk_pins[] =3D { 137 }; +static const unsigned int sdc2_clk_pins[] =3D { 138 }; +static const unsigned int sdc2_cmd_pins[] =3D { 139 }; +static const unsigned int sdc2_data_pins[] =3D { 140 }; +static const unsigned int qdsd_clk_pins[] =3D { 141 }; +static const unsigned int qdsd_cmd_pins[] =3D { 142 }; +static const unsigned int qdsd_data0_pins[] =3D { 143 }; +static const unsigned int qdsd_data1_pins[] =3D { 144 }; +static const unsigned int qdsd_data2_pins[] =3D { 145 }; +static const unsigned int qdsd_data3_pins[] =3D { 146 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs =3D (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs =3D 10, \ + .ctl_reg =3D 0x1000 * id, \ + .io_reg =3D 0x4 + 0x1000 * id, \ + .intr_cfg_reg =3D 0x8 + 0x1000 * id, \ + .intr_status_reg =3D 0xc + 0x1000 * id, \ + .intr_target_reg =3D 0x8 + 0x1000 * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 4, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D ctl, \ + .io_reg =3D 0, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D pull, \ + .drv_bit =3D drv, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D -1, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_target_kpss_val =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +enum msm8917_functions { + msm_mux_accel_int, + msm_mux_adsp_ext, + msm_mux_alsp_int, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_combodac_to_gpio_native, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_atest_tsens, + msm_mux_atest_wlan0, + msm_mux_atest_wlan1, + msm_mux_audio_ref, + msm_mux_audio_reset, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp6_spi, + msm_mux_blsp8_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uart7, + msm_mux_blsp_uart8, + msm_mux_cam0_ldo, + msm_mux_cam1_rst, + msm_mux_cam1_standby, + msm_mux_cam2_rst, + msm_mux_cam2_standby, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cdc_pdm0, + msm_mux_codec_int1, + msm_mux_codec_int2, + msm_mux_codec_mad, + msm_mux_coex_uart, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_ebi_cdc, + msm_mux_ebi_ch0, + msm_mux_ext_lpass, + msm_mux_forced_usb, + msm_mux_fp_gpio, + msm_mux_fp_int, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_gsm0_tx, + msm_mux_key_focus, + msm_mux_key_snapshot, + msm_mux_key_volp, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_lpass_slimbus0, + msm_mux_lpass_slimbus1, + msm_mux_m_voc, + msm_mux_mag_int, + msm_mux_mdp_vsync, + msm_mux_mipi_dsi0, + msm_mux_modem_tsync, + msm_mux_nav_pps, + msm_mux_nav_pps_in_a, + msm_mux_nav_pps_in_b, + msm_mux_nav_tsync, + msm_mux_nfc_pwr, + msm_mux_ov_ldo, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pri_mi2s_mclk_b, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_sd_write, + msm_mux_sdcard_det, + msm_mux_sec_mi2s, + msm_mux_sec_mi2s_mclk_a, + msm_mux_sec_mi2s_mclk_b, + msm_mux_sensor_rst, + msm_mux_smb_int, + msm_mux_ssbi_wtr1, + msm_mux_ts_resout, + msm_mux_ts_sample, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_us_emitter, + msm_mux_us_euro, + msm_mux_wcss_bt, + msm_mux_wcss_fm, + msm_mux_wcss_wlan, + msm_mux_wcss_wlan0, + msm_mux_wcss_wlan1, + msm_mux_wcss_wlan2, + msm_mux_webcam_rst, + msm_mux_webcam_standby, + msm_mux_wsa_io, + msm_mux_wsa_irq, + msm_mux_NA, +}; + +static const char * const qdss_tracedata_b_groups[] =3D { + "gpio0", "gpio1", "gpio6", "gpio7", "gpio12", "gpio13", "gpio23", + "gpio42", "gpio43", "gpio44", "gpio47", "gpio66", "gpio86", "gpio87", + "gpio88", "gpio92", +}; + +static const char * const blsp_uart1_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", +}; + +static const char * const blsp_spi1_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const adsp_ext_groups[] =3D { + "gpio1", +}; + +static const char * const blsp_i2c1_groups[] =3D { + "gpio2", "gpio3", +}; + +static const char * const prng_rosc_groups[] =3D { + "gpio2", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] =3D { + "gpio2", +}; + +static const char * const blsp_spi2_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_uart2_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_uart3_groups[] =3D { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const pbs0_groups[] =3D { + "gpio8", +}; + +static const char * const pbs1_groups[] =3D { + "gpio9", +}; + +static const char * const pwr_modem_enabled_b_groups[] =3D { + "gpio9", +}; + +static const char * const blsp_i2c3_groups[] =3D { + "gpio10", "gpio11", +}; + +static const char * const gcc_gp2_clk_b_groups[] =3D { + "gpio10", +}; + +static const char * const ldo_update_groups[] =3D { + "gpio4", +}; + +static const char * const atest_combodac_to_gpio_native_groups[] =3D { + "gpio4", "gpio12", "gpio13", "gpio20", "gpio21", "gpio28", "gpio29", + "gpio30", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", + "gpio45", "gpio46", "gpio47", "gpio48", "gpio67", "gpio115", +}; + +static const char * const ldo_en_groups[] =3D { + "gpio5", +}; + +static const char * const blsp_i2c2_groups[] =3D { + "gpio6", "gpio7", +}; + +static const char * const gcc_gp1_clk_b_groups[] =3D { + "gpio6", +}; + +static const char * const pbs2_groups[] =3D { + "gpio7", +}; + +static const char * const atest_gpsadc_dtest0_native_groups[] =3D { + "gpio7", +}; + +static const char * const blsp_spi3_groups[] =3D { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const gcc_gp3_clk_b_groups[] =3D { + "gpio11", +}; + +static const char * const blsp_spi4_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const blsp_uart4_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const sec_mi2s_groups[] =3D { + "gpio12", "gpio13", "gpio94", "gpio95", +}; + +static const char * const pwr_nav_enabled_b_groups[] =3D { + "gpio12", +}; + +static const char * const codec_mad_groups[] =3D { + "gpio13", +}; + +static const char * const pwr_crypto_enabled_b_groups[] =3D { + "gpio13", +}; + +static const char * const blsp_i2c4_groups[] =3D { + "gpio14", "gpio15", +}; + +static const char * const blsp_spi5_groups[] =3D { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const blsp_uart5_groups[] =3D { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const qdss_traceclk_a_groups[] =3D { + "gpio16", +}; + +static const char * const atest_bbrx1_groups[] =3D { + "gpio16", +}; + +static const char * const m_voc_groups[] =3D { + "gpio17", "gpio21", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] =3D { + "gpio17", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] =3D { + "gpio21", +}; + +static const char * const blsp_i2c6_groups[] =3D { + "gpio22", "gpio23", +}; + +static const char * const qdss_traceclk_b_groups[] =3D { + "gpio22", +}; + +static const char * const atest_wlan0_groups[] =3D { + "gpio22", +}; + +static const char * const atest_bbrx0_groups[] =3D { + "gpio17", +}; + +static const char * const blsp_i2c5_groups[] =3D { + "gpio18", "gpio19", +}; + +static const char * const qdss_tracectl_a_groups[] =3D { + "gpio18", +}; + +static const char * const atest_gpsadc_dtest1_native_groups[] =3D { + "gpio18", +}; + +static const char * const qdss_tracedata_a_groups[] =3D { + "gpio19", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio38", "gpio39", + "gpio40", "gpio50", +}; + +static const char * const blsp_spi6_groups[] =3D { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const blsp_uart6_groups[] =3D { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qdss_tracectl_b_groups[] =3D { + "gpio20", +}; + +static const char * const atest_wlan1_groups[] =3D { + "gpio23", +}; + +static const char * const mdp_vsync_groups[] =3D { + "gpio24", "gpio25", +}; + +static const char * const pri_mi2s_mclk_a_groups[] =3D { + "gpio25", +}; + +static const char * const sec_mi2s_mclk_a_groups[] =3D { + "gpio25", +}; + +static const char * const cam_mclk_groups[] =3D { + "gpio26", "gpio27", "gpio28", +}; + +static const char * const cci_i2c_groups[] =3D { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const pwr_modem_enabled_a_groups[] =3D { + "gpio29", +}; + +static const char * const cci_timer0_groups[] =3D { + "gpio33", +}; + +static const char * const cci_timer1_groups[] =3D { + "gpio34", +}; + +static const char * const cam1_standby_groups[] =3D { + "gpio35", +}; + +static const char * const pwr_nav_enabled_a_groups[] =3D { + "gpio35", +}; + +static const char * const cam1_rst_groups[] =3D { + "gpio36", +}; + +static const char * const pwr_crypto_enabled_a_groups[] =3D { + "gpio36", +}; + +static const char * const forced_usb_groups[] =3D { + "gpio37", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] =3D { + "gpio37", +}; + +static const char * const cam2_rst_groups[] =3D { + "gpio38", +}; + +static const char * const webcam_standby_groups[] =3D { + "gpio39", +}; + +static const char * const cci_async_groups[] =3D { + "gpio39", +}; + +static const char * const webcam_rst_groups[] =3D { + "gpio40", +}; + +static const char * const ov_ldo_groups[] =3D { + "gpio41", +}; + +static const char * const sd_write_groups[] =3D { + "gpio41", +}; + +static const char * const accel_int_groups[] =3D { + "gpio42", +}; + +static const char * const gcc_gp1_clk_a_groups[] =3D { + "gpio42", +}; + +static const char * const alsp_int_groups[] =3D { + "gpio43", +}; + +static const char * const gcc_gp2_clk_a_groups[] =3D { + "gpio43", +}; + +static const char * const mag_int_groups[] =3D { + "gpio44", +}; + +static const char * const gcc_gp3_clk_a_groups[] =3D { + "gpio44", +}; + +static const char * const blsp6_spi_groups[] =3D { + "gpio47", +}; + +static const char * const fp_int_groups[] =3D { + "gpio48", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] =3D { + "gpio48", +}; + +static const char * const uim_batt_groups[] =3D { + "gpio49", +}; + +static const char * const cam2_standby_groups[] =3D { + "gpio50", +}; + +static const char * const uim1_data_groups[] =3D { + "gpio51", +}; + +static const char * const uim1_clk_groups[] =3D { + "gpio52", +}; + +static const char * const uim1_reset_groups[] =3D { + "gpio53", +}; + +static const char * const uim1_present_groups[] =3D { + "gpio54", +}; + +static const char * const uim2_data_groups[] =3D { + "gpio55", +}; + +static const char * const uim2_clk_groups[] =3D { + "gpio56", +}; + +static const char * const uim2_reset_groups[] =3D { + "gpio57", +}; + +static const char * const uim2_present_groups[] =3D { + "gpio58", +}; + +static const char * const sensor_rst_groups[] =3D { + "gpio59", +}; + +static const char * const mipi_dsi0_groups[] =3D { + "gpio60", +}; + +static const char * const smb_int_groups[] =3D { + "gpio61", +}; + +static const char * const cam0_ldo_groups[] =3D { + "gpio62", +}; + +static const char * const us_euro_groups[] =3D { + "gpio63", +}; + +static const char * const atest_char3_groups[] =3D { + "gpio63", +}; + +static const char * const dbg_out_groups[] =3D { + "gpio63", +}; + +static const char * const bimc_dte0_groups[] =3D { + "gpio63", "gpio65", +}; + +static const char * const ts_resout_groups[] =3D { + "gpio64", +}; + +static const char * const ts_sample_groups[] =3D { + "gpio65", +}; + +static const char * const sec_mi2s_mclk_b_groups[] =3D { + "gpio66", +}; + +static const char * const pri_mi2s_groups[] =3D { + "gpio66", "gpio85", "gpio86", "gpio88", "gpio94", "gpio95", +}; + +static const char * const sdcard_det_groups[] =3D { + "gpio67", +}; + +static const char * const atest_char1_groups[] =3D { + "gpio67", +}; + +static const char * const ebi_cdc_groups[] =3D { + "gpio67", "gpio69", "gpio118", "gpio119", "gpio120", "gpio123", +}; + +static const char * const audio_reset_groups[] =3D { + "gpio68", +}; + +static const char * const atest_char0_groups[] =3D { + "gpio68", +}; + +static const char * const audio_ref_groups[] =3D { + "gpio69", +}; + +static const char * const cdc_pdm0_groups[] =3D { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", +}; + +static const char * const pri_mi2s_mclk_b_groups[] =3D { + "gpio69", +}; + +static const char * const lpass_slimbus_groups[] =3D { + "gpio70", +}; + +static const char * const lpass_slimbus0_groups[] =3D { + "gpio71", +}; + +static const char * const lpass_slimbus1_groups[] =3D { + "gpio72", +}; + +static const char * const codec_int1_groups[] =3D { + "gpio73", +}; + +static const char * const codec_int2_groups[] =3D { + "gpio74", +}; + +static const char * const wcss_bt_groups[] =3D { + "gpio75", "gpio83", "gpio84", +}; + +static const char * const atest_char2_groups[] =3D { + "gpio75", +}; + +static const char * const ebi_ch0_groups[] =3D { + "gpio75", +}; + +static const char * const wcss_wlan2_groups[] =3D { + "gpio76", +}; + +static const char * const wcss_wlan1_groups[] =3D { + "gpio77", +}; + +static const char * const wcss_wlan0_groups[] =3D { + "gpio78", +}; + +static const char * const wcss_wlan_groups[] =3D { + "gpio79", "gpio80", +}; + +static const char * const wcss_fm_groups[] =3D { + "gpio81", "gpio82", +}; + +static const char * const ext_lpass_groups[] =3D { + "gpio81", +}; + +static const char * const cri_trng_groups[] =3D { + "gpio82", +}; + +static const char * const cri_trng1_groups[] =3D { + "gpio83", +}; + +static const char * const cri_trng0_groups[] =3D { + "gpio84", +}; + +static const char * const blsp_spi7_groups[] =3D { + "gpio85", "gpio86", "gpio87", "gpio88", +}; + +static const char * const blsp_uart7_groups[] =3D { + "gpio85", "gpio86", "gpio87", "gpio88", +}; + +static const char * const pri_mi2s_ws_groups[] =3D { + "gpio87", +}; + +static const char * const blsp_i2c7_groups[] =3D { + "gpio87", "gpio88", +}; + +static const char * const gcc_tlmm_groups[] =3D { + "gpio87", +}; + +static const char * const dmic0_clk_groups[] =3D { + "gpio89", +}; + +static const char * const dmic0_data_groups[] =3D { + "gpio90", +}; + +static const char * const key_volp_groups[] =3D { + "gpio91", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] =3D { + "gpio91", +}; + +static const char * const us_emitter_groups[] =3D { + "gpio92", +}; + +static const char * const wsa_irq_groups[] =3D { + "gpio93", +}; + +static const char * const wsa_io_groups[] =3D { + "gpio94", "gpio95", +}; + +static const char * const blsp_spi8_groups[] =3D { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const blsp_uart8_groups[] =3D { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const blsp_i2c8_groups[] =3D { + "gpio98", "gpio99", +}; + +static const char * const gcc_plltest_groups[] =3D { + "gpio98", "gpio99", +}; + +static const char * const nav_pps_in_a_groups[] =3D { + "gpio115", +}; + +static const char * const pa_indicator_groups[] =3D { + "gpio116", +}; + +static const char * const modem_tsync_groups[] =3D { + "gpio117", +}; + +static const char * const nav_tsync_groups[] =3D { + "gpio117", +}; + +static const char * const nav_pps_in_b_groups[] =3D { + "gpio117", +}; + +static const char * const nav_pps_groups[] =3D { + "gpio117", +}; + +static const char * const gsm0_tx_groups[] =3D { + "gpio119", +}; + +static const char * const atest_char_groups[] =3D { + "gpio120", +}; + +static const char * const atest_tsens_groups[] =3D { + "gpio120", +}; + +static const char * const bimc_dte1_groups[] =3D { + "gpio121", "gpio122", +}; + +static const char * const ssbi_wtr1_groups[] =3D { + "gpio122", "gpio123", +}; + +static const char * const fp_gpio_groups[] =3D { + "gpio124", +}; + +static const char * const coex_uart_groups[] =3D { + "gpio124", "gpio127", +}; + +static const char * const key_snapshot_groups[] =3D { + "gpio127", +}; + +static const char * const key_focus_groups[] =3D { + "gpio128", +}; + +static const char * const nfc_pwr_groups[] =3D { + "gpio129", +}; + +static const char * const blsp8_spi_groups[] =3D { + "gpio130", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] =3D { + "gpio132", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] =3D { + "gpio133", +}; + +static const struct pinfunction msm8917_functions[] =3D { + MSM_PIN_FUNCTION(accel_int), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(alsp_int), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_combodac_to_gpio_native), + MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native), + MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_wlan0), + MSM_PIN_FUNCTION(atest_wlan1), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(audio_reset), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp6_spi), + MSM_PIN_FUNCTION(blsp8_spi), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(blsp_uart7), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(cam0_ldo), + MSM_PIN_FUNCTION(cam1_rst), + MSM_PIN_FUNCTION(cam1_standby), + MSM_PIN_FUNCTION(cam2_rst), + MSM_PIN_FUNCTION(cam2_standby), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cdc_pdm0), + MSM_PIN_FUNCTION(codec_int1), + MSM_PIN_FUNCTION(codec_int2), + MSM_PIN_FUNCTION(codec_mad), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(ebi_cdc), + MSM_PIN_FUNCTION(ebi_ch0), + MSM_PIN_FUNCTION(ext_lpass), + MSM_PIN_FUNCTION(forced_usb), + MSM_PIN_FUNCTION(fp_gpio), + MSM_PIN_FUNCTION(fp_int), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(key_focus), + MSM_PIN_FUNCTION(key_snapshot), + MSM_PIN_FUNCTION(key_volp), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(lpass_slimbus0), + MSM_PIN_FUNCTION(lpass_slimbus1), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mag_int), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mipi_dsi0), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(nav_pps_in_a), + MSM_PIN_FUNCTION(nav_pps_in_b), + MSM_PIN_FUNCTION(nav_tsync), + MSM_PIN_FUNCTION(nfc_pwr), + MSM_PIN_FUNCTION(ov_ldo), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_mclk_a), + MSM_PIN_FUNCTION(pri_mi2s_mclk_b), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto_enabled_a), + MSM_PIN_FUNCTION(pwr_crypto_enabled_b), + MSM_PIN_FUNCTION(pwr_modem_enabled_a), + MSM_PIN_FUNCTION(pwr_modem_enabled_b), + MSM_PIN_FUNCTION(pwr_nav_enabled_a), + MSM_PIN_FUNCTION(pwr_nav_enabled_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdcard_det), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sec_mi2s_mclk_a), + MSM_PIN_FUNCTION(sec_mi2s_mclk_b), + MSM_PIN_FUNCTION(sensor_rst), + MSM_PIN_FUNCTION(smb_int), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(ts_resout), + MSM_PIN_FUNCTION(ts_sample), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(us_emitter), + MSM_PIN_FUNCTION(us_euro), + MSM_PIN_FUNCTION(wcss_bt), + MSM_PIN_FUNCTION(wcss_fm), + MSM_PIN_FUNCTION(wcss_wlan), + MSM_PIN_FUNCTION(wcss_wlan0), + MSM_PIN_FUNCTION(wcss_wlan1), + MSM_PIN_FUNCTION(wcss_wlan2), + MSM_PIN_FUNCTION(webcam_rst), + MSM_PIN_FUNCTION(webcam_standby), + MSM_PIN_FUNCTION(wsa_io), + MSM_PIN_FUNCTION(wsa_irq), +}; + +static const struct msm_pingroup msm8917_groups[] =3D { + PINGROUP(0, blsp_spi1, blsp_uart1, qdss_tracedata_b, NA, NA, NA, NA, + NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, adsp_ext, NA, NA, NA, NA, NA, + qdss_tracedata_b), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, prng_rosc, NA, NA, NA, + NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, NA, NA, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, + qdss_tracedata_b, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, pbs2, NA, + qdss_tracedata_b, NA, atest_gpsadc_dtest0_native, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, pbs0, NA, NA, NA, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, pbs1, pwr_modem_enabled_b, NA, NA, + NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp2_clk_b, NA, NA, + NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp3_clk_b, NA, NA, + NA, NA, NA), + PINGROUP(12, blsp_spi4, blsp_uart4, sec_mi2s, pwr_nav_enabled_b, NA, + NA, NA, NA, NA), + PINGROUP(13, blsp_spi4, blsp_uart4, sec_mi2s, pwr_crypto_enabled_b, NA, + NA, NA, NA, NA), + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi5, blsp_uart5, NA, NA, NA, NA, qdss_traceclk_a, + NA, atest_bbrx1), + PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, NA, + atest_bbrx0, NA, NA, NA), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracectl_a, NA, + atest_gpsadc_dtest1_native, NA, NA, NA), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(20, blsp_spi6, blsp_uart6, NA, NA, NA, NA, NA, NA, + qdss_tracectl_b), + PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, NA, NA, NA, NA, NA, + qdss_cti_trig_in_b0), + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, NA, + atest_wlan0, NA, NA, NA), + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, NA, + atest_wlan1, NA, NA, NA), + PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, NA, NA, NA, + NA, NA, NA), + PINGROUP(26, cam_mclk, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, NA), + PINGROUP(27, cam_mclk, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(28, cam_mclk, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native), + PINGROUP(29, cci_i2c, pwr_modem_enabled_a, NA, NA, NA, NA, NA, + qdss_tracedata_a, NA), + PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(31, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(32, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(33, cci_timer0, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(34, cci_timer1, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(35, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, + qdss_tracedata_a), + PINGROUP(36, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, + qdss_tracedata_a), + PINGROUP(37, NA, NA, NA, NA, NA, qdss_cti_trig_out_b1, NA, NA, NA), + PINGROUP(38, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, cci_async, NA, NA, NA, NA, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native), + PINGROUP(40, NA, NA, NA, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native, NA, NA), + PINGROUP(41, sd_write, NA, NA, NA, NA, NA, NA, NA, + atest_combodac_to_gpio_native), + PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA), + PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA), + PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, + NA), + PINGROUP(46, NA, NA, atest_combodac_to_gpio_native, NA, NA, NA, NA, NA, + NA), + PINGROUP(47, blsp6_spi, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(48, NA, qdss_cti_trig_in_b1, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA, NA), + PINGROUP(49, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, atest_char3, dbg_out, bimc_dte0, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, bimc_dte0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, NA, qdss_tracedata_b, NA, NA, + NA, NA, NA), + PINGROUP(67, atest_char1, ebi_cdc, NA, atest_combodac_to_gpio_native, + NA, NA, NA, NA, NA), + PINGROUP(68, atest_char0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, audio_ref, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, NA, NA, NA, + NA, NA), + PINGROUP(70, lpass_slimbus, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, lpass_slimbus0, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, lpass_slimbus1, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, wcss_bt, atest_char2, NA, ebi_ch0, NA, NA, NA, NA, NA), + PINGROUP(76, wcss_wlan2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, wcss_wlan1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, wcss_wlan0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, wcss_wlan, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, wcss_wlan, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, wcss_fm, ext_lpass, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, wcss_fm, cri_trng, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, wcss_bt, cri_trng1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, wcss_bt, cri_trng0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, pri_mi2s, blsp_spi7, blsp_uart7, NA, NA, NA, NA, NA, NA), + PINGROUP(86, pri_mi2s, blsp_spi7, blsp_uart7, qdss_tracedata_b, NA, NA, + NA, NA, NA), + PINGROUP(87, pri_mi2s_ws, blsp_spi7, blsp_uart7, blsp_i2c7, + qdss_tracedata_b, gcc_tlmm, NA, NA, NA), + PINGROUP(88, pri_mi2s, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA, + NA, NA), + PINGROUP(89, dmic0_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, dmic0_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, qdss_cti_trig_in_a1, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, wsa_io, sec_mi2s, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(95, wsa_io, sec_mi2s, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(96, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, NA, NA, NA, + NA, NA), + PINGROUP(99, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, NA, NA, NA, + NA, NA), + PINGROUP(100, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, nav_pps_in_a, NA, atest_combodac_to_gpio_native, + NA, NA, NA, NA), + PINGROUP(116, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, modem_tsync, nav_tsync, nav_pps_in_b, nav_pps, NA, + NA, NA, NA), + PINGROUP(118, NA, ebi_cdc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, gsm0_tx, NA, ebi_cdc, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, atest_char, ebi_cdc, NA, atest_tsens, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, bimc_dte1, NA, NA, NA, NA, NA), + PINGROUP(122, NA, ssbi_wtr1, NA, NA, bimc_dte1, NA, NA, NA, NA), + PINGROUP(123, NA, ssbi_wtr1, ebi_cdc, NA, NA, NA, NA, NA, NA), + PINGROUP(124, coex_uart, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, coex_uart, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, blsp8_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_PINGROUP(sdc1_rclk, 0x10a000, 15, 0), + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +#define NUM_GPIO_PINGROUPS 134 + +static const struct msm_pinctrl_soc_data msm8917_pinctrl =3D { + .pins =3D msm8917_pins, + .npins =3D ARRAY_SIZE(msm8917_pins), + .functions =3D msm8917_functions, + .nfunctions =3D ARRAY_SIZE(msm8917_functions), + .groups =3D msm8917_groups, + .ngroups =3D ARRAY_SIZE(msm8917_groups), + .ngpios =3D NUM_GPIO_PINGROUPS, +}; + +static int msm8917_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8917_pinctrl); +} + +static const struct of_device_id msm8917_pinctrl_of_match[] =3D { + { .compatible =3D "qcom,msm8917-pinctrl", }, + { }, +}; + +static struct platform_driver msm8917_pinctrl_driver =3D { + .driver =3D { + .name =3D "msm8917-pinctrl", + .of_match_table =3D msm8917_pinctrl_of_match, + }, + .probe =3D msm8917_pinctrl_probe, + .remove_new =3D msm_pinctrl_remove, +}; + +static int __init msm8917_pinctrl_init(void) +{ + return platform_driver_register(&msm8917_pinctrl_driver); +} +arch_initcall(msm8917_pinctrl_init); + +static void __exit msm8917_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8917_pinctrl_driver); +} +module_exit(msm8917_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8917 pinctrl driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, msm8917_pinctrl_of_match); --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B1441E0DE5; Sat, 19 Oct 2024 11:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338655; cv=none; b=tzTt9G1+kVT51Cy1E7ZqACst1i6AGIcCskzfydp7HIo56DDc1JB5Ox8K6F9a8Ei8hKJN2F0iTIZXiUy79P5/gu/iJH+9jpqHw/Sdj/bk1gWGm6H++1pfZ6Ro/pRumVLVMDw4NxamC3PZA86QOiw/F8ZXGAWOXJb2XnLVG7wyBVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338655; c=relaxed/simple; bh=u8x5Y76BpR7GHm0tcI8s42oOSgTRRalW68806GGcELk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C+tDuEUGzuJIcjOaRJ857C9Um3QnQPonoPNxEdaPllPjfopk/LU2f8OS/BXayhoWb6hY+327RJfg0jT+peKfLqSDeJ66w00DQtEbXE4ggu9W3ar5Tjftz+Fd71nqiAXgb0JDWxZoAIwqxyFOZhTaAHwLD/MhG/5GSGT3UwHp9lY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=gH16FJTL; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="gH16FJTL" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 0B203E45A4; Sat, 19 Oct 2024 11:50:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338647; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=V3+UAizzWXsZekrxnLJdeu9Ruj4MIRyoNFA7cvKypSE=; b=gH16FJTLWMW4j5HW38K6k0StfWUvgA5cwGnDQITxWaP05n/4JCceElAkuEYRhrlXaevFuI 6NTZT7NVYRm2uG5ZGW5nnG5nQgojg80TB+LkS+5Rw5IV4NP1ubL6g3K61kWyhE4ta3PvW7 Nxqke26VTtOZ4Ayx1TZKhKjBOVkpxg6gDz8FlitUgTbGijrSwkZt3Prkv/Dz5KeJp9NH7p T3xQdmdVaR7lUQIQdDi/JvYvquIJgeU4vTvFRoXe3I1uZGxx5LCiOTu8UUgY36VGE59SF7 LMlIncnX3TBa+IkSK/LSxU0BBUVm78nGEdAtPMEfPXiAUrtzafyKRATe97gDPw== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:45 +0200 Subject: [PATCH RFC 08/14] dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8917 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-8-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=824; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=u8x5Y76BpR7GHm0tcI8s42oOSgTRRalW68806GGcELk=; b=i+NdQ+S9ej8/pGzje2ajBDoOYtWjt16eE0oIprmWbmXEKq+IypS3/uIR7WP+TdJpDvDuOYJeK LUl/aoemcqfAe4JHE+SUImsB8TnS3dIFmAYyYVgb0EjdTPYcMwzdfQw X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the qcom,msm8917-tcsr compatible. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documen= tation/devicetree/bindings/mfd/qcom,tcsr.yaml index c4fcf501f502724b5ca36bc4a26f77a00104ac48..79add913e35c848363941a8634a= 361c45d296392 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -50,6 +50,7 @@ properties: - qcom,tcsr-msm8226 - qcom,tcsr-msm8660 - qcom,tcsr-msm8916 + - qcom,tcsr-msm8917 - qcom,tcsr-msm8953 - qcom,tcsr-msm8960 - qcom,tcsr-msm8974 --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B68D81E1050; Sat, 19 Oct 2024 11:50:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338656; cv=none; b=GEZRbGEmxBZDWLy8mONhEeHBbOig9+11DvpiMubp8YgmcK45INuDAk5Ge2Eg5ZRcrkFJfhGFdlV7Pu7vhRmI+7yKnQ/y73hlJG2PHwjCql9fc7EG6IsAeDBiA9acMX5rOkWzC35MijBX26MW7Y7vMaTRG4t01CnA1SG7RhMnyWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338656; c=relaxed/simple; bh=IRtvRWDOANUihN14f+/JFJ+TjYo+Ikv6z9bgXN7AQDE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uUWf6mQ/2Neb+8vkLAbfoNy7wDjjtRHDXLnK0cCwzVdJLzB4g0SBIYcZyiLmge3lZubDPCRgBERJgcNoT9CfXWaiUDCtWx+h0TvBRnV6VzNgpm7ZBFkC8pFIuDrqDFzlYebDY0vQYkUW2rocDgywQ1WrmILIwaeJd4XOVtd567E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=qGrCPH8l; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="qGrCPH8l" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 19880E45A5; Sat, 19 Oct 2024 11:50:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338648; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mKHpg+U4gE4J6mrWua3GIqYVhtuoK9V1rqrrgqzuVrU=; b=qGrCPH8lehKF+IPaQbQsIOFO8HJKyTB5H6qqEEDwMSN+/vXsKyryhYcIUhB9XXh/S8OXe5 DY/aomyV2/Y7+c2wsD8DvKawtIflnELE7e0JT8uKJF/cJw+98Et40J/AHER66gHBTKPqNO hXZUYdulfqTDgPYpx0IBvNCbKN9IXvAVmLCKBVw6eNuiDRw+nB03Cq1hGd2hiC2o6Qqfu2 SEkkefdeR0NzXnE2cKk2asA4oefFka8WT/og4uDapZ+TgRQx1R3tgsX3Nw7Mb3wEUm2TAh pYV5H5UgCIO6710KDp5IxWbdrCpjG1SPm+ceRzxSw2njBD/9cVa0V51M93iJYg== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:46 +0200 Subject: [PATCH RFC 09/14] dt-bindings: thermal: tsens: Add MSM8917 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-9-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=860; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=IRtvRWDOANUihN14f+/JFJ+TjYo+Ikv6z9bgXN7AQDE=; b=xYlQSXfyL3pitR6D3rsfA/xofcBFsujGkMfpMCUlWG2cSdI1Yb3l1nYwgqXNIFAi72eFKyJsZ c5vr5BK6zcHAYyJgpn0QFAPXP2MMlmbxZInICQCDlPN9gKdE+dV6fDT X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the compatible string for tsens found in MSM8917. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index a12fddc8195500a0e7bdd51952a558890b35935c..9add4fdc21fa307cbe9be6dde30= 369777f1ef91c 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -39,6 +39,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,msm8917-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A1DD1E103D; Sat, 19 Oct 2024 11:50:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338657; cv=none; b=q1j4PeilHy9aiigU5eta9DgtOwJ0N9Ss0drZ1kNID6AERAbHBfzHwatA3hyQI/v6He7yZq9q2FRBOIC36ZgwiwVXAXUh4adkyeQhRYAz86IHzeMQvF3gQFa0xcMyHNqjy5yQqGBIHSGJx+LYCvjVDbED9dACuV3YgmGlQn/1UDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338657; c=relaxed/simple; bh=+auV2xbHnH8Ew5XeZexktMLe4HULByqQHcRGhcce8AI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oAF10XqlcIUOw8MwGa4/gl+dIhFiF+WVDOsDVix91Jwmo5Jz+FlHgYVYhJ62X7fkRvDURx5UMx2b8XpRlcx3tFdNFa6VeTtnnY32Y0F/3iYic2gj2j4OhV7u2REPOZmekCvluMfygd4k0H/PL+AWmI0mjBtvyDOW06mQYrzoL7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=G0kj8Kd7; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="G0kj8Kd7" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id B7EE1E45A6; Sat, 19 Oct 2024 11:50:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wSjtl8egN/7amHQK4rd+lA7Mo+LBp5UxTJkQiEalxxA=; b=G0kj8Kd7yFJp1V011CW6hIEGyP3Z8wa22Pw2s9JlobBOBpsWkz/ztSMhXY1x9vKxhf2lum VnK7d1D9RIfj5S+cifq5cjzN6dNKNzehUs2JcgFCTBYAkqn7Pd8JAaKHawScEO3d+uExl9 yEaYIV7e/ZUvEMaw65kz9+nb8PdlmwNKVKvbi4qmHwtwXgSTQ8+XJM+ng9/ZH9Vh5E4UKN xTWfA9w4C7Y0aiAFIpzGN2GwtVnghx1G0E/J72ausBDJvtLRBDEuK7ypWN0m/J58Z+TEEe Rh9Eh9FWoWRFPvjR5XkI11/VG/V0LPITeSsz3/cqKf4wGPeh8og1euWxqBFnvA== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:47 +0200 Subject: [PATCH RFC 10/14] dt-bindings: iommu: qcom,iommu: Add MSM8917 IOMMU to SMMUv1 compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-10-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=939; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=+auV2xbHnH8Ew5XeZexktMLe4HULByqQHcRGhcce8AI=; b=mNOPhhrVpRQixxGld4RDKS/wBnAShh0zzApIWIZiN9PugJfI29a1VYKHo4+ninOR9hr+za1SC cm/glkJsPZDC56qJ7K0oM3IeIeQ/jnbgUgpqe2jLYDKQWaBwixRwiPH X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add MSM8917 compatible string with "qcom,msm-iommu-v1" as fallback for the MSM8917 IOMMU which is compatible with Qualcomm's secure fw "SMMU v1" implementation. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Docu= mentation/devicetree/bindings/iommu/qcom,iommu.yaml index f8cebc9e8cd9d46b449cd297153dbebe5c84bf3f..5ae9a628261fd251c1e991a7066= 2c6d37ef2c4e3 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - qcom,msm8916-iommu + - qcom,msm8917-iommu - qcom,msm8953-iommu - const: qcom,msm-iommu-v1 - items: --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E0B1E1319; Sat, 19 Oct 2024 11:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338657; cv=none; b=Cks/kL6r3C5NJECi0xSTug5ABgGhBr70NmPr+ubPf4oMslyRyFGEDZRwhY/uMw19m1+Gy1UB41O5WGK2EQKTp1rDisTXfHC0AMX3GPvymPfsW4KOU3LemrftF1ekkpzwiGwynJ6IwJAl7HCu7a07cv0EdA9hy4/1SnGQvQzMJZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338657; c=relaxed/simple; bh=6kyI8Tcl7R9HDBFx1gkFswYsDmaf4ylpJeZ5Zg10oiQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rgXmrnudPipkdG52BWEvy/+LO3MyuakQ+SFt74U/4zbBFG26RwFPf2/gqOXQAWCYGR3uDDyns9hmt1AQuUgJ9gqRsh1HLz9X7kNk0AraRm7rKm/KNO9j6vi/pONe5mu+Q7NKIY9ZUuHsbMD+lVOCUfTnavd+OVh8FtB0fIp7gdU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=HUA7lt2q; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="HUA7lt2q" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 6CFB0E45A7; Sat, 19 Oct 2024 11:50:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5alMJRql3gqrqTNkSA2fg70oYcbid9R/aDxsT0IGwds=; b=HUA7lt2qe8OpQQQtApF83xR3uYiVfuhTwP8+FE8/h+mOuy+R0JrtG0ihXVwGp0Nm1ihvjG gIO9mXMlFviClrB+GWekxgqg+hb0fS/m9OiMb/y6JaSC97OLRDqXaBGakkp4gJLsbkFPll BJSbYbmZ6J/YXTp196AcHr0ih9fzH5b4YORVyUltWtb80JMY9wiOvV1ck0HYFxIIV6OTEG 1/9HT5FzYUQilwlPrUXQIicXGiWtY0tG2lzAbPOQURoKwZp8wMuwFlYQugqMY9XiiRwPDr SDPGChSQUinGVgAyQ4i4/gqy9D+JMRpLxKkhXEcy0PM6zPoTMiiX1UUy6Lpu4g== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:48 +0200 Subject: [PATCH RFC 11/14] dt-bindings: nvmem: Add compatible for MS8917 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-11-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=859; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=6kyI8Tcl7R9HDBFx1gkFswYsDmaf4ylpJeZ5Zg10oiQ=; b=ufw5737uB19IWV5PM9IkUvAkzFDRi1X8Sv2lKjiAk865fKuZYyAqFVlLC1ZzgIRBN7ihpE9t+ kFQjeR0M+H3CjR9wAE9/Q0JUNhRnmAq8DFL6ujbJmaSEIw4ry5jGEj2 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the QFPROM block found on MSM8917. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Doc= umentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 80845c722ae46611c722effeaaf014a0caf76e4a..4d81f98ed37a3a12f01d444dbfa= 77badcc09c22d 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -26,6 +26,7 @@ properties: - qcom,ipq9574-qfprom - qcom,msm8226-qfprom - qcom,msm8916-qfprom + - qcom,msm8917-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom - qcom,msm8996-qfprom --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 239F21E1303; Sat, 19 Oct 2024 11:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338660; cv=none; b=R8+QurA8uGJWd/Km8GZpwifJNyXjVngkK5lG6P/dBR7unbwir6e/oWk1JLucMdhmRaRdrZUzRTWr2h3i42D1qNaR1bmXJA0TCYmjrD7apTtQMOoM6wUEMlhPpMmLAyZIpRAVxKHs1aW+klOCbGaRaKzg9C5wl1K01CcUhsbiGvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338660; c=relaxed/simple; bh=yWdPwbCVQVtO6XxacTnxUCHCd3yOFNC/p5yh/VqbA/Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HJePV15xSgz5k3+TgGKPw5NVxoOCJWTSLbV/6xFJ8v2VE7U2sHLyqC0MeCX5zV/TTXdHloAyfiBvJj1eKP/FCWqlXkDlyDt8/3/SiH7982iUYSovOWDtsiss9lISl9gNdKMOfdQhJzfcfctTzX65Brc6tjiN8e0DBg3hzQoFqV8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=G8ebZbWs; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="G8ebZbWs" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 0F376E45A8; Sat, 19 Oct 2024 11:50:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338650; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9DCtVlR1OObUQ8dN4ZJA6SNkEKl/VKGLEJC/8cKQif4=; b=G8ebZbWsROc66iQzdYo/CLgUIOPzUtO2vQhOpmpeHrA2kxH6xRXqd9kwXF5gMaX/3aPoKT GkQXDdnSWOT8mkGYwfZnLJCrsWNc+khRxGm6QQM1+UR3wRgSP+DidfRJb7oPdC/CCSwFoZ 3N1CoZ5IYI9XbhEmWt/MOdAguUYxXM6n3K1WbQLhrjVLQX732M0F9AmjnYw1+uUKeDYvMW 2kj3awD2ym/ps7aXCr57nLcrD6Ox59X8ZkZEGJErKzLq/8QRFC4lcEe+j3TGD6sKYTyorX hUWTBVpBQfl/C9sZJt1kj0MbNvMRloyEO4WWPJUQ8rHgg5zScACthpwbtkyVrQ== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:49 +0200 Subject: [PATCH RFC 12/14] arm64: dts: qcom: Add initial support for MSM8917 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-12-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=47269; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=YLLWvT6zvXGgEeRY20/tTrmWwXHQNKlEvFpBxQPtEx4=; b=PH3RLrjxEQGDZLrF2t2V1FV/PN9a9R+lgMNMj2DEnrdc8G4HvixMXJDDi0r9CeI/Q3gd4zMv+ NGX8ZSAsmAnDDyaUiPeoGjzIyoAbN6U/wWYpjzrrvJTjn8MuITuZ5E/ X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Otto Pfl=C3=BCger Add initial support for MSM8917 SoC. Signed-off-by: Otto Pfl=C3=BCger [reword commit, rebase, fix schema errors] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/msm8917-pins.dtsi | 344 ++++++ arch/arm64/boot/dts/qcom/msm8917.dtsi | 1557 ++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/pm8916.dtsi | 9 +- 3 files changed, 1909 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8917-pins.dtsi b/arch/arm64/boot/d= ts/qcom/msm8917-pins.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..f283ffd59b8aca8e510ef95d552= 6af9592a1c036 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917-pins.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0 +&tlmm { + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + + drive-strength =3D <16>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + + drive-strength =3D <16>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_uart1_default: blsp2-uart1-default-state { + pins =3D "gpio16", "gpio17", "gpio18", "gpio19"; + function =3D "blsp_uart5"; + + drive-strength =3D <16>; + bias-disable; + }; + + blsp2_uart1_sleep: blsp2-uart1-sleep-state { + pins =3D "gpio16", "gpio17", "gpio18", "gpio19"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp2_uart2_default: blsp2-uart2-default-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "blsp_uart5"; + + drive-strength =3D <16>; + bias-disable; + }; + + blsp2_uart2_sleep: blsp2-uart2-sleep-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + i2c2_default: i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c2_sleep: i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_default: i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_default: i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_sleep: i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_default: i2c5-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_sleep: i2c5-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c6_default: i2c6-default-state { + pins =3D "gpio22", "gpio23"; + function =3D "blsp_i2c6"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c6_sleep: i2c6-sleep-state { + pins =3D "gpio22", "gpio23"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + spi3_default: spi3-default-state { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "blsp_spi3"; + + drive-strength =3D <12>; + bias-disable; + }; + + spi3_sleep: spi3-sleep-state { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi6_default: spi6-default-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "blsp_spi6"; + + drive-strength =3D <12>; + bias-disable; + }; + + spi6_sleep: spi6-sleep-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc1_clk_on: sdc1-clk-on-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + sdc1_clk_off: sdc1-clk-off-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_cmd_on: sdc1-cmd-on-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <10>; + }; + + sdc1_cmd_off: sdc1-cmd-off-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_data_on: sdc1-data-on-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc1_data_off: sdc1-data-off-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc1_rclk_on: sdc1-rclk-on-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: sdc1-rclk-off-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc2_clk_on: sdc2-clk-on-state { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_clk_off: sdc2-clk-off-state { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc2_data_on: sdc2-data-on-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_data_off: sdc2-data-off-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc2_cd_on: cd-on-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan2-pins { + pins =3D "gpio76"; + function =3D "wcss_wlan2"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan1-pins { + pins =3D "gpio77"; + function =3D "wcss_wlan1"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan0-pins { + pins =3D "gpio78"; + function =3D "wcss_wlan0"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan-pins { + pins =3D "gpio79", "gpio80"; + function =3D "wcss_wlan"; + drive-strength =3D <6>; + bias-pull-up; + + }; + }; + + cci0_default: cci0-default-state { + pins =3D "gpio29", "gpio30"; + function =3D "cci_i2c"; + + + drive-strength =3D <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins =3D "gpio31", "gpio32"; + function =3D "cci_i2c"; + + + drive-strength =3D <2>; + bias-disable; + }; + + cdc_pdm_lines_act: pdm-lines-on-state { + pins =3D "gpio69", "gpio70", "gpio71", "gpio72", + "gpio73", "gpio74"; + function =3D "cdc_pdm0"; + + drive-strength =3D <8>; + bias-disable; + }; + + cdc_pdm_lines_sus: pdm-lines-off-state { + pins =3D "gpio69", "gpio70", "gpio71", "gpio72", + "gpio73", "gpio74"; + function =3D "cdc_pdm0"; + + drive-strength =3D <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qc= om/msm8917.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e5f580c6ec28ad6442b31a0e1ee= 256c376c5438d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -0,0 +1,1557 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + reserved@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + /* + * The memory region for the mpss firmware is generally + * relocatable and could be allocated dynamically. + * However, many firmware versions tend to fail when + * loaded to some special addresses, so it is hard to + * define reliable alloc-ranges. + * + * alignment =3D <0x0 0x400000>; + * alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + */ + reg =3D <0x0 0x86800000 0x0 0>; /* size is device-specific */ + no-map; + status =3D "disabled"; + }; + + adsp_mem: adsp { + size =3D <0x0 0x1100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + wcnss_mem: wcnss { + size =3D <0x0 0x700000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x400000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + rmtfs@92100000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x92100000 0x0 0x180000>; + no-map; + + qcom,client-id =3D <1>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + next-level-cache =3D <&L2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&CPU_PD0>; + power-domain-names =3D "psci"; + }; + + CPU1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + next-level-cache =3D <&L2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&CPU_PD1>; + power-domain-names =3D "psci"; + }; + + CPU2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + next-level-cache =3D <&L2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&CPU_PD2>; + power-domain-names =3D "psci"; + }; + + CPU3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + next-level-cache =3D <&L2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&CPU_PD3>; + power-domain-names =3D "psci"; + }; + + L2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "standalone-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <125>; + exit-latency-us =3D <180>; + min-residency-us =3D <595>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_PWRDN: cluster-gdhs { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000043>; + entry-latency-us =3D <240>; + exit-latency-us =3D <280>; + min-residency-us =3D <806>; + }; + + CLUSTER_RET: cluster-retention { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000023>; + entry-latency-us =3D <700>; + exit-latency-us =3D <650>; + min-residency-us =3D <1972>; + }; + + CLUSTER_PC: cluster-power-collapse { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000053>; + entry-latency-us =3D <700>; + exit-latency-us =3D <1000>; + min-residency-us =3D <6500>; + }; + }; + }; + + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "xo"; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "sleep_clk"; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8916", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", "bus", "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&CLUSTER_PWRDN>, <&CLUSTER_RET>, <&CLUSTER_PC>; + }; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8917-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8917", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8917", "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apcs 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + qcom,ipc =3D <&apcs 8 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <451>, <431>; + + interrupts =3D ; + + qcom,ipc =3D <&apcs 8 18>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + qcom,ipc-1 =3D <&apcs 8 13>; + qcom,ipc-3 =3D <&apcs 8 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0xffffffff>; + compatible =3D "simple-bus"; + + rng@22000 { + compatible =3D "qcom,prng"; + reg =3D <0xe3000 0x1000>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + + qfprom: qfprom@a4000 { + compatible =3D "qcom,msm8917-qfprom", "qcom,qfprom"; + reg =3D <0x000a4000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + tsens_caldata: caldata@d0 { + reg =3D <0x01d8 0x14>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x00060000 0x8000>; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8917-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + nvmem-cells =3D <&tsens_caldata>; + nvmem-cell-names =3D "calib"; + #qcom,sensors =3D <10>; + interrupts =3D ; + interrupt-names =3D "uplow"; + #thermal-sensor-cells =3D <1>; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8917-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8917"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + reg =3D <0x01800000 0x80000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>; + clock-names =3D "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8917", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + apps_iommu: iommu@1e00000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + compatible =3D "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; + ranges =3D <0 0x01e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", "bus"; + + qcom,iommu-secure-id =3D <17>; + + /* VFE */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x00014000 0x1000>; + interrupts =3D ; + }; + + /* MDP_0 */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x00015000 0x1000>; + interrupts =3D ; + }; + + /* VENUS_NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x00016000 0x1000>; + interrupts =3D ; + }; + }; + + gpu_iommu: iommu@1f00000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + compatible =3D "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; + + ranges =3D <0 0x01f08000 0x10000>; + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names =3D "iface", "bus"; + qcom,iommu-secure-id =3D <18>; + + iommu-ctx@0 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0x0000 0x1000>; + interrupts =3D ; + }; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ab0000 0x1040>; + reg-names =3D "mdss_phys", "vbif_phys"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + status =3D "disabled"; + + mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8917-mdp5", "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + iommus =3D <&apps_iommu 0x15>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdp5_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a94000 0x300>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&mdss_dsi0_opp_table>; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94400 { + compatible =3D "qcom,dsi-phy-28nm-8937"; + reg =3D <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names =3D "iface", "ref"; + }; + }; + + a53pll: clock@b016000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b016000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table>; + + pll_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-306.32", "qcom,adreno"; + reg =3D <0x01c00000 0x20000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + clock-names =3D "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gfx3d"; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains =3D <&gcc OXILI_GX_GDSC>; + operating-points-v2 =3D <&gpu_opp_table>; + #cooling-cells =3D <2>; + + iommus =3D <&gpu_iommu 0>; + + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-598000000 { + opp-hz =3D /bits/ 64 <598000000>; + }; + + opp-523200000 { + opp-hz =3D /bits/ 64 <523200000>; + }; + + opp-484800000 { + opp-hz =3D /bits/ 64 <484800000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + }; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + }; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x04044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + + num-channels =3D <6>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + apcs: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, <0x07824000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x500>, <0x07864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + bus-width =3D <4>; + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1d000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <10>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_uart1_default>; + pinctrl-1 =3D <&blsp1_uart1_sleep>; + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + status =3D "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c2_default>; + pinctrl-1 =3D <&i2c2_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c3_default>; + pinctrl-1 =3D <&i2c3_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi3_default>; + pinctrl-1 =3D <&spi3_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c4_default>; + pinctrl-1 =3D <&i2c4_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c5: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c5_default>; + pinctrl-1 =3D <&i2c5_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi6: spi@7af6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi6_default>; + pinctrl-1 =3D <&spi6_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x6c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&xo_board>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", "ahb", "sleep"; + resets =3D <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", "por"; + status =3D "disabled"; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + phy_type =3D "ulpi"; + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + status =3D "disabled"; + #reset-cells =3D <1>; + }; + + pronto: wcnss: remoteproc@a21b000 { + compatible =3D "qcom,pronto-v3-pil", "qcom,pronto"; + reg =3D <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; + reg-names =3D "ccu", "dxe", "pmu"; + + memory-region =3D <&wcnss_mem>; + + interrupts-extended =3D <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains =3D <&rpmpd MSM8917_VDDCX>, + <&rpmpd MSM8917_VDDMX>; + power-domain-names =3D "cx", "mx"; + + qcom,smem-states =3D <&wcnss_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wcnss_pin_a>; + + status =3D "disabled"; + + wcnss_iris: iris { + clocks =3D <&rpmcc RPM_SMD_RF_CLK2>; + clock-names =3D "xo"; + }; + + smd-edge { + interrupts =3D ; + + qcom,ipc =3D <&apcs 8 17>; + qcom,smd-edge =3D <6>; + qcom,remote-pid =3D <4>; + + label =3D "pronto"; + + wcnss_ctrl: wcnss { + compatible =3D "qcom,wcnss"; + qcom,smd-channels =3D "WCNSS_CTRL"; + + qcom,mmio =3D <&pronto>; + + wcnss_bt: bluetooth { + compatible =3D "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible =3D "qcom,wcnss-wlan"; + + interrupts =3D , + ; + interrupt-names =3D "tx", "rx"; + + qcom,smem-states =3D <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names =3D "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0x0b017000 0x1000>; + clocks =3D <&sleep_clk>; + }; + + timer@b120000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + clock-frequency =3D <19200000>; + + frame@b121000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0b123000 0x1000>; + status =3D "disabled"; + }; + + frame@b124000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0b124000 0x1000>; + status =3D "disabled"; + }; + + frame@b125000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0b125000 0x1000>; + status =3D "disabled"; + }; + + frame@b126000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0b126000 0x1000>; + status =3D "disabled"; + }; + + frame@b127000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0b127000 0x1000>; + status =3D "disabled"; + }; + + frame@b128000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x0b128000 0x1000>; + status =3D "disabled"; + }; + }; + }; + + thermal_zones: thermal-zones { + aoss-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + mdm-core-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 1>; + + trips { + mdm_core_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + q6-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 2>; + + trips { + q6_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 4>; + + trips { + cpuss1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpuss1_crit: cpuss1-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpuss1_alert0>; + cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 5>; + + trips { + cpu0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu0_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu0_alert1>; + cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 6>; + + trips { + cpu1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu1_alert1>; + cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 7>; + + trips { + cpu2_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu2_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu2_alert1>; + cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 8>; + + trips { + cpu3_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu3_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cpu3_alert1>; + cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 9>; + + trips { + gpu_alert: trip-point0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_crit: gpu-crit { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_alert>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +#include "msm8917-pins.dtsi" diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qco= m/pm8916.dtsi index f8e4829ff7f7de1f1f4f5da0f41020875d6c7e17..df0f679250ccb6c49a76288fad1= 2f67b01fa6b61 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -47,7 +47,7 @@ pon@800 { mode-bootloader =3D <0x2>; mode-recovery =3D <0x1>; =20 - pwrkey { + pm8916_pwrkey: pwrkey { compatible =3D "qcom,pm8941-pwrkey"; interrupts =3D <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; debounce =3D <15625>; @@ -210,6 +210,10 @@ pm8916_pwm: pwm { status =3D "disabled"; }; =20 + pm8916_spmi_regulators: regulators { + compatible =3D "qcom,pm8916-regulators"; + }; + pm8916_vib: vibrator@c000 { compatible =3D "qcom,pm8916-vib"; reg =3D <0xc000>; @@ -219,6 +223,9 @@ pm8916_vib: vibrator@c000 { pm8916_codec: audio-codec@f000 { compatible =3D "qcom,pm8916-wcd-analog-codec"; reg =3D <0xf000>; + reg-names =3D "pmic-codec-core"; + clocks =3D <&xo_board>; + clock-names =3D "mclk"; interrupt-parent =3D <&spmi_bus>; interrupts =3D <0x1 0xf0 0x0 IRQ_TYPE_NONE>, <0x1 0xf0 0x1 IRQ_TYPE_NONE>, --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E79301E1A05; Sat, 19 Oct 2024 11:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338658; cv=none; b=hfYYoBfn7DsDm/AdvaUgNzlBsilFatWfiEqb2xsFhIofUO5eZiPUAHtgZlecKM9qjRcZw/NRQq5SvfiiMWiX+qHmd8Afhz37FF5IihxWV6Px9Aam000qNYzv6EJXbWu7J1zoJk/v8Fz9viH8LukJHcOaJqCAHZhNbscW2IjrBvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338658; c=relaxed/simple; bh=2nPuAQAvXP8Cx7DIAPS1I1Ekpq+3eK6gff1nwVFbJG0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dfigfPT2j5YgfzNK0/eT9iFNiFXLoqJkf1n7uxkHz+jMzoOqIVOUs21kshebQuE/LxHtAMlOlgKX15ZBVby/8LUKH0jfknRfXpdCSZnYOUxI0pO6oEdaQGpu/djkWSjCb9x9Yhqrp8qZ2NnQ3jCNl10osLOy4tCND63XZ6CkgSM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=bkadrJpX; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="bkadrJpX" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id CF084E45A9; Sat, 19 Oct 2024 11:50:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338651; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kWQMQa89WI1DdQtCFYAl2tQmrPPsbbO0kBTe4esXkms=; b=bkadrJpXo7jF1loZpZ82CJWsQxSKxCbRCq34TxJd0owwJgk0yj+ZL9ShfsonuDWjWHjU60 EIZbeM3D5WXtLI1opMII0gjitL0hforW7a+nNahfAEakzwJPM4n6bNXkNlWVza3ufuT3Su vH0nDeVINuEQyHe+A0QK2znePxNKfx1HQM5dRNPlS+7dTQ4l0FzgtZ8xOzF27dXPDHnDIP 9IT7CUA44iEzX6ZUfU6e3/3u4XVvwE9UsbEjpr/9rgwfPbL0SDJmQ2SqWwfg3bkzjkU7Xn a1fcUjIKKGLZ+u/OOUN922U0rshRaAsZcWGYefA2AhiL+Fe03MhzoU5Am9z57Q== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:50 +0200 Subject: [PATCH RFC 13/14] dt-bindings: arm: qcom: Add Xiaomi Redmi 5A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-13-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=1227; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=2nPuAQAvXP8Cx7DIAPS1I1Ekpq+3eK6gff1nwVFbJG0=; b=kos7Z9FVbRHIVmbMRJdwDOMxeR2dsNnvYeKv9GB9lndF0p5UmbG9AqShRIkmCb2KAPhmA0lGK XPmOpb6AEaFBqDpmikFlmwM7A3M3257IwActlhEW9OGyyNUkD5Xt6s8 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document Xiaomi Remi 5A (riva). Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 0d451082570edef9f2f80e2c7544a953eebe9edc..0d545a1744662df6d3c17771ae3= cee80c89fb281 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -31,6 +31,7 @@ description: | mdm9615 msm8226 msm8916 + msm8917 msm8939 msm8953 msm8956 @@ -248,6 +249,11 @@ properties: - yiming,uz801-v3 - const: qcom,msm8916 =20 + - items: + - enum: + - xiaomi,riva + - const: qcom,msm8917 + - items: - enum: - motorola,potter @@ -1144,6 +1150,7 @@ allOf: - qcom,apq8026 - qcom,apq8094 - qcom,apq8096 + - qcom,msm8917 - qcom,msm8939 - qcom,msm8953 - qcom,msm8956 --=20 2.47.0 From nobody Tue Nov 26 08:31:26 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CD6A1E1A15; Sat, 19 Oct 2024 11:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338659; cv=none; b=IAOlAV5234j9zXh2kCe47Jt0Vb9ehSN0lG4r68PKjxSytEfXfhOzas2twa0NgIgP8fVTNbLs7wyNz9c3Hs9YR/VVp9aVdYDCoQ/JlSr1JNJQ1DVlEPt0nPFAy6r/entf0Tca7B8ejreBE0PYORTu2ccy6eQS0d3ckrnFDnbGUG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729338659; c=relaxed/simple; bh=+ht4DlMNaXgXRO8D2BEpmRFGbLZJwEQL59rC0tuSAeo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sgY4aknCULom2OdvyJgap4TGGe6/pX0bT3VmbXlW8wJwcPbD8DPQvm8Dx00imV+NnQaHlnj02sKcKCtY/wdMN8JdR3DfPzhdt4sCkGr71NaiOr0d+zqoHTgpPW0g5ZO58ka7VMZeHgIYivDOXPHN+LUkn+ITyVM4wJX9kBs8L8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=b/iPHZV1; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="b/iPHZV1" Received: from [192.168.1.130] (51B6DD9D.dsl.pool.telekom.hu [81.182.221.157]) by mail.mainlining.org (Postfix) with ESMTPSA id 6F498E4205; Sat, 19 Oct 2024 11:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1729338651; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0zp0tKVwTU8TS66qVxT5hpORGc3/VihCAGc5nVbSMSs=; b=b/iPHZV1oLAJ1Gy2NPxiM7ibY66wzTx4RYEZZIJBonPf88PFLhNPcM/kqCSSkD9CyLtNWr Wms3v8rZyfd/dTESfTRMA1LMIwGW+KWGG0Un6gCTdkLcPBKfnxcdJ6m+UPeDpXHvOIlfAZ yOE4v3hilzggLGtcvthtep2Hi6eHQU+YZYOqMyKFZ6hZCetQSFSlrG/65vRudxpVxv5cDJ Nd3IwwRRPgqeMpx/g4L9BOaBwGDL6AY84RjOKy3LW8BK0NG7UWzdynSiTxOkKKooSMEBfz e7Suit4aS70rSk/3Xf6s/Kf/QWLX0bOpzeUTqlN5yQyiSWwaOqxqI0IZMCCAMA== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 19 Oct 2024 13:50:51 +0200 Subject: [PATCH RFC 14/14] arm64: dts: qcom: Add Xiaomi Redmi 5A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-msm8917-v1-14-f1f3ca1d88e5@mainlining.org> References: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> In-Reply-To: <20241019-msm8917-v1-0-f1f3ca1d88e5@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729338640; l=8108; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=+ht4DlMNaXgXRO8D2BEpmRFGbLZJwEQL59rC0tuSAeo=; b=uGVA/xHEiShSUaCt76MsHKo4bryVydpN+sPm3T6n4mcGhBT3ZE/EXnlI8ZGmSfU8gtxFMA1X9 X1nfj8cWdzIB0GKu76S8xibOWXnRsKKg8BppDcxWPy1Wa4fTKI4I8Vz X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add initial support for Xiaomi Redmi 5A (riva). Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts | 295 +++++++++++++++++++= ++++ 2 files changed, 296 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 065bb19481c16db2affd291826d420c83a89c52a..79add0e07d8a5f3362d70b0aaaa= a9b8c48e31239 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt86518.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt86528.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8917-xiaomi-riva.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8929-wingtech-wt82918hd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-huawei-kiwi.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-longcheer-l9100.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts b/arch/arm64/= boot/dts/qcom/msm8917-xiaomi-riva.dts new file mode 100644 index 0000000000000000000000000000000000000000..7553f73603fc87797b0d424a2af= 6f2da65c90f5f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Barnabas Czeman + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "msm8917.dtsi" +#include "pm8937.dtsi" + +/ { + model =3D "Xiaomi Redmi 5A (riva)"; + compatible =3D "xiaomi,riva", "qcom,msm8917"; + chassis-type =3D "handset"; + + qcom,msm-id =3D ; + qcom,board-id =3D <0x1000b 2>, <0x2000b 2>; + + battery: battery { + compatible =3D "simple-battery"; + charge-full-design-microamp-hours =3D <3000000>; + energy-full-design-microwatt-hours =3D <11500000>; + constant-charge-current-max-microamp =3D <1000000>; + constant-charge-voltage-max-microvolt =3D <4400000>; + precharge-current-microamp =3D <256000>; + charge-term-current-microamp =3D <60000>; + voltage-min-design-microvolt =3D <3400000>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "framebuffer0"; + + framebuffer0: framebuffer@90001000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0x90001000 0x0 (720 * 1280 * 3)>; + width =3D <720>; + height =3D <1280>; + stride =3D <(720 * 3)>; + format =3D "r8g8b8"; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains =3D <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + key-volup { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + reserved-memory { + /delete-node/ reserved@85b00000; + qseecom_mem: reserved@84a00000 { + reg =3D <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer_mem: memory@90001000 { + reg =3D <0x0 0x90001000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp_i2c3 { + status =3D "okay"; + + touchscreen@38 { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x38>; + interrupt-parent =3D <&tlmm>; + interrupts =3D <65 0x2008>; + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&pm8937_l10>; + iovcc-supply =3D <&pm8937_l5>; + + touchscreen-size-x =3D <720>; + touchscreen-size-y =3D <1280>; + }; +}; + +&blsp_i2c5 { + status =3D "okay"; + + bq27426@55 { + compatible =3D "ti,bq27426"; + reg =3D <0x55>; + monitored-battery =3D <&battery>; + }; + + bq25601@6b{ + compatible =3D "ti,bq25601"; + reg =3D <0x6b>; + monitored-battery =3D <&battery>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <61 IRQ_TYPE_EDGE_FALLING>; + + input-voltage-limit-microvolt =3D <4400000>; + input-current-limit-microamp =3D <1000000>; + }; +}; + +&pm8937_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&pm8937_spmi_regulators { + pm8937_s5: s5 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&rpm_requests { + regulators-0 { + compatible =3D "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + + vdd_l1_l19-supply =3D <&pm8937_s3>; + vdd_l2_l23-supply =3D <&pm8937_s3>; + vdd_l3-supply =3D <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply =3D <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply =3D <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt =3D <1225000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; + +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8937_l8>; + vqmmc-supply =3D <&pm8937_l5>; + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&pm8937_l11>; + vqmmc-supply =3D <&pm8937_l12>; + status =3D "okay"; +}; + +&wcnss { + vddpx-supply =3D <&pm8937_l5>; + status =3D "okay"; + +}; + +&wcnss_iris { + compatible =3D "qcom,wcn3620"; + vddxo-supply =3D <&pm8937_l7>; + vddrfa-supply =3D <&pm8937_l19>; + vddpa-supply =3D <&pm8937_l9>; + vdddig-supply =3D <&pm8937_l5>; +}; + +&wcnss_mem { + status =3D "okay"; +}; --=20 2.47.0