From nobody Tue Nov 26 08:51:26 2024 Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.144.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A6CA18DF88; Fri, 18 Oct 2024 20:59:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.144.205 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729285168; cv=none; b=sSGvFp+MVhah+wdIUfnCqylwiY2TqG0D83eTP8ri7VEr++0vZwRpwK2UPNbYVen5d0WD7D0TbIdYROfzxkWqKw0gn4UxexMdciTpafuPMcry+aDa+3RnCEOnbFnRh8F/Me6fM5auudPzK3x7itWDrtF1pB9t1/ZJLiERsVqYjAw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729285168; c=relaxed/simple; bh=+tk2cpjGb3VNztKsp+kLY6AgcFI4WOO+Igx1tj7XyyM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=srm/634h1wTkyjLLI5eljSATBpyh5OQ2B5BVt+NvsgCO99eIx8SZmCC5EbOQfqFBFG4pd3Y2sect6WD4ZD/VZMIOQnbA8HdvwZA39rw/vPFbDj5j9jMusEJBeItuPxRNRLnJdEQW7h0a8sXRkJrkoEQVNxeEMjmdg6mvYzjQum4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=kPC/mYQ4; arc=none smtp.client-ip=192.19.144.205 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="kPC/mYQ4" Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.36.132.253]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 41CA6C003AC6; Fri, 18 Oct 2024 13:53:37 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 41CA6C003AC6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1729284817; bh=+tk2cpjGb3VNztKsp+kLY6AgcFI4WOO+Igx1tj7XyyM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kPC/mYQ4uyTcj1Qj8161HBaROhFebCA0lwe35Zi7cngX3PHuDg8qVgmfRgi5ga8Kw FH0UxRHEVFMovYUBwLgN7p6721mq3U6mfE/QO/jnzstcsZm1AYCvwZriqDySHMLvQC o9Sf2hgsXr15qUKVLgI2aB5WtF2Bbj1mZYS/i9x8= Received: from pcie-dev03.dhcp.broadcom.net (pcie-dev03.dhcp.broadcom.net [10.59.171.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPSA id 8E7AB18041CACA; Fri, 18 Oct 2024 13:53:36 -0700 (PDT) From: jitendra.vegiraju@broadcom.com To: netdev@vger.kernel.org Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, jitendra.vegiraju@broadcom.com, bcm-kernel-feedback-list@broadcom.com, richardcochran@gmail.com, ast@kernel.org, daniel@iogearbox.net, hawk@kernel.org, john.fastabend@gmail.com, fancer.lancer@gmail.com, rmk+kernel@armlinux.org.uk, ahalaney@redhat.com, xiaolei.wang@windriver.com, rohan.g.thomas@intel.com, Jianheng.Zhang@synopsys.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org, andrew@lunn.ch, linux@armlinux.org.uk, horms@kernel.org, florian.fainelli@broadcom.com, quic_abchauha@quicinc.com Subject: [PATCH net-next v6 1/5] net: stmmac: Add snps_id, dev_id to struct plat_stmmacenet_data Date: Fri, 18 Oct 2024 13:53:28 -0700 Message-Id: <20241018205332.525595-2-jitendra.vegiraju@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> References: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitendra Vegiraju Introduce new variables plat_stmmacenet_data::snps_id,dev_id to allow glue drivers to specify synopsys ID and device id respectively. These values take precedence over reading from HW register. This facility provides a mechansim to use setup function from stmmac core module and yet override MAC.VERSION CSR if the glue driver chooses to do so. Signed-off-by: Jitendra Vegiraju --- include/linux/stmmac.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index d79ff252cfdc..4c4965a5a0d0 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -183,6 +183,8 @@ struct dwmac4_addrs { #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12) =20 struct plat_stmmacenet_data { + u32 snps_id; + u32 dev_id; int bus_id; int phy_addr; /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media --=20 2.34.1 From nobody Tue Nov 26 08:51:26 2024 Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.144.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A67318D63A; Fri, 18 Oct 2024 20:59:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.144.205 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729285169; cv=none; b=hdgQVK5TPWxgWOP/YJCPRwce3He6z+MI+Ysh8dw0fp4x1EUpg5DP/ozW3659SUVgdv+cTJbE3LOFwliZ4zokR8ouAE8hhmM5o9LA5LLlfmJH8ZK4R8xR4pAiiNY9m7qWvukQIGJ3sYyARs2alZ1OWjFPNmsXMmg8VyP4lKKIFD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729285169; c=relaxed/simple; bh=GkQT8mwzUI+JJua/Chm0C8V76c7cOuqD0w/Rn/98ITY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J0RhbNDs2276eOU/IaAUYjmZL0SIPaIfEu8FpXstLHQNRiCwcNajKYHKjTumUlpcnyIVwn9RyAt8wd3ZBkNpelSOYwZx/A6ZT+TRl+ra1JuEf6rcKmv8AZOrNb5xpXuPJVhg9hpqSeC8Svcr8SXaFI2yWNjFHdPLGAO4cbJX0Mg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=iwJt2u76; arc=none smtp.client-ip=192.19.144.205 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="iwJt2u76" Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.36.132.253]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id B91DEC003ADD; Fri, 18 Oct 2024 13:53:37 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com B91DEC003ADD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1729284818; bh=GkQT8mwzUI+JJua/Chm0C8V76c7cOuqD0w/Rn/98ITY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iwJt2u76RpTlB1d6qFAyi1L+mrhjy5Y3NNzL21zN1JUWj1kknipH+1ON9OSwP/Fng Oq9iVQGAZgoTHjdgYxue/LtVRk6nvnBHrIBPM4Vs7p1DwTg16sQJTSHn+N/Zi6UpJf mT9akCvQvhP+f9KdlBg+USRU7UWYZ7fBMztZRPKk= Received: from pcie-dev03.dhcp.broadcom.net (pcie-dev03.dhcp.broadcom.net [10.59.171.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPSA id 0E73118041CAC6; Fri, 18 Oct 2024 13:53:37 -0700 (PDT) From: jitendra.vegiraju@broadcom.com To: netdev@vger.kernel.org Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, jitendra.vegiraju@broadcom.com, bcm-kernel-feedback-list@broadcom.com, richardcochran@gmail.com, ast@kernel.org, daniel@iogearbox.net, hawk@kernel.org, john.fastabend@gmail.com, fancer.lancer@gmail.com, rmk+kernel@armlinux.org.uk, ahalaney@redhat.com, xiaolei.wang@windriver.com, rohan.g.thomas@intel.com, Jianheng.Zhang@synopsys.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org, andrew@lunn.ch, linux@armlinux.org.uk, horms@kernel.org, florian.fainelli@broadcom.com, quic_abchauha@quicinc.com Subject: [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core Date: Fri, 18 Oct 2024 13:53:29 -0700 Message-Id: <20241018205332.525595-3-jitendra.vegiraju@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> References: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitendra Vegiraju The BCM8958x uses early adopter version of DWC_xgmac version 4.00a for Ethernet MAC. The DW25GMAC introduced in this version adds new DMA architecture called Hyper-DMA (HDMA) for virtualization scalability. This is realized by decoupling physical DMA channels(PDMA) from potentially large number of virtual DMA channels (VDMA). The VDMAs are software abstractions that map to PDMAs for frame transmission and reception. Define new macros DW25GMAC_CORE_4_00 and DW25GMAC_ID to identify DW25GMAC device. To support the new HDMA architecture, a new instance of stmmac_dma_ops dw25gmac400_dma_ops is added. To support the current needs, a simple one-to-one mapping of dw25gmac's logical VDMA (channel) to TC to PDMAs is used. Most of the other dma operation functions in existing dwxgamc2_dma.c file are reused where applicable. Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core. Signed-off-by: Jitendra Vegiraju --- drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +- drivers/net/ethernet/stmicro/stmmac/common.h | 4 + .../net/ethernet/stmicro/stmmac/dw25gmac.c | 161 ++++++++++++++++++ .../net/ethernet/stmicro/stmmac/dw25gmac.h | 92 ++++++++++ .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 1 + .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 42 +++++ .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 52 ++++++ drivers/net/ethernet/stmicro/stmmac/hwif.h | 1 + 8 files changed, 354 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index c2f0e91f6bf8..967e8a9aa432 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -6,7 +6,7 @@ stmmac-objs:=3D stmmac_main.o stmmac_ethtool.o stmmac_mdio.= o ring_mode.o \ mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \ dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \ stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \ - stmmac_xdp.o stmmac_est.o \ + stmmac_xdp.o stmmac_est.o dw25gmac.o \ $(stmmac-y) =20 stmmac-$(CONFIG_STMMAC_SELFTESTS) +=3D stmmac_selftests.o diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/eth= ernet/stmicro/stmmac/common.h index 684489156dce..9a747b89ba51 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -38,9 +38,11 @@ #define DWXGMAC_CORE_2_10 0x21 #define DWXGMAC_CORE_2_20 0x22 #define DWXLGMAC_CORE_2_00 0x20 +#define DW25GMAC_CORE_4_00 0x40 =20 /* Device ID */ #define DWXGMAC_ID 0x76 +#define DW25GMAC_ID 0x55 #define DWXLGMAC_ID 0x27 =20 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ @@ -563,6 +565,7 @@ struct mac_link { u32 speed2500; u32 speed5000; u32 speed10000; + u32 speed25000; } xgmii; struct { u32 speed25000; @@ -621,6 +624,7 @@ int dwmac100_setup(struct stmmac_priv *priv); int dwmac1000_setup(struct stmmac_priv *priv); int dwmac4_setup(struct stmmac_priv *priv); int dwxgmac2_setup(struct stmmac_priv *priv); +int dw25gmac_setup(struct stmmac_priv *priv); int dwxlgmac2_setup(struct stmmac_priv *priv); =20 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c b/drivers/net/e= thernet/stmicro/stmmac/dw25gmac.c new file mode 100644 index 000000000000..8d0b45a7607a --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Broadcom Corporation + */ +#include "stmmac.h" +#include "dwxgmac2.h" +#include "dw25gmac.h" + +u32 dw25gmac_decode_vdma_count(u32 regval) +{ + /* compressed encoding for vdma count */ + if (regval < 16) /* Direct mapping */ + return regval + 1; + else if (regval < 20) /* 20, 24, 28, 32 */ + return 20 + (regval - 16) * 4; + else if (regval < 24) /* 40, 48, 56, 64 */ + return 40 + (regval - 20) * 8; + else if (regval < 28) /* 80, 96, 112, 128 */ + return 80 + (regval - 24) * 16; + else /* not defined */ + return 0; +} + +static int rd_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel) +{ + u32 reg_val =3D 0; + + reg_val |=3D FIELD_PREP(XXVGMAC_MODE_SELECT, mode); + reg_val |=3D FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel); + reg_val |=3D XXVGMAC_CMD_TYPE | XXVGMAC_OB; + writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL); + return readl(ioaddr + XXVGMAC_DMA_CH_IND_DATA); +} + +static void wr_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel, u32 = val) +{ + u32 reg_val =3D 0; + + writel(val, ioaddr + XXVGMAC_DMA_CH_IND_DATA); + reg_val |=3D FIELD_PREP(XXVGMAC_MODE_SELECT, mode); + reg_val |=3D FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel); + reg_val |=3D XGMAC_OB; + writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL); +} + +void dw25gmac_dma_init(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg) +{ + u32 tx_pdmas, rx_pdmas; + u32 hw_cap; + u32 value; + u32 i; + + value =3D readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); + value &=3D ~(XGMAC_AAL | XGMAC_EAME); + if (dma_cfg->aal) + value |=3D XGMAC_AAL; + if (dma_cfg->eame) + value |=3D XGMAC_EAME; + writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); + + /* Get PDMA counts from HW */ + hw_cap =3D readl(ioaddr + XGMAC_HW_FEATURE2); + tx_pdmas =3D FIELD_GET(XGMAC_HWFEAT_TXQCNT, hw_cap) + 1; + rx_pdmas =3D FIELD_GET(XGMAC_HWFEAT_RXQCNT, hw_cap) + 1; + + /* Intialize all PDMAs with burst length fields */ + for (i =3D 0; i < tx_pdmas; i++) { + value =3D rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i); + value &=3D ~(XXVGMAC_TXPBL | XXVGMAC_TPBLX8_MODE); + if (dma_cfg->pblx8) + value |=3D XXVGMAC_TPBLX8_MODE; + value |=3D FIELD_PREP(XXVGMAC_TXPBL, dma_cfg->pbl); + wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i, value); + } + + for (i =3D 0; i < rx_pdmas; i++) { + value =3D rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i); + value &=3D ~(XXVGMAC_RXPBL | XXVGMAC_RPBLX8_MODE); + if (dma_cfg->pblx8) + value |=3D XXVGMAC_RPBLX8_MODE; + value |=3D FIELD_PREP(XXVGMAC_RXPBL, dma_cfg->pbl); + wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i, value); + } +} + +void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv, + void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_addr, u32 chan) +{ + u32 value; + u32 tc; + + /* Descriptor cache size and prefetch threshold size */ + value =3D rd_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan); + value &=3D ~XXVGMAC_TXDCSZ; + value |=3D FIELD_PREP(XXVGMAC_TXDCSZ, + XXVGMAC_TXDCSZ_256BYTES); + value &=3D ~XXVGMAC_TDPS; + value |=3D FIELD_PREP(XXVGMAC_TDPS, XXVGMAC_TDPS_HALF); + wr_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan, value); + + /* Use one-to-one mapping between VDMA, TC, and PDMA. */ + tc =3D chan; + + /* 1-to-1 PDMA to TC mapping */ + value =3D rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan); + value &=3D ~XXVGMAC_TP2TCMP; + value |=3D FIELD_PREP(XXVGMAC_TP2TCMP, tc); + wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan, value); + + /* 1-to-1 VDMA to TC mapping */ + value =3D readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + value &=3D ~XXVGMAC_TVDMA2TCMP; + value |=3D FIELD_PREP(XXVGMAC_TVDMA2TCMP, tc); + writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + + writel(upper_32_bits(dma_addr), + ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); + writel(lower_32_bits(dma_addr), + ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); +} + +void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv, + void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_addr, u32 chan) +{ + u32 value; + u32 tc; + + /* Descriptor cache size and prefetch threshold size */ + value =3D rd_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan); + value &=3D ~XXVGMAC_RXDCSZ; + value |=3D FIELD_PREP(XXVGMAC_RXDCSZ, + XXVGMAC_RXDCSZ_256BYTES); + value &=3D ~XXVGMAC_RDPS; + value |=3D FIELD_PREP(XXVGMAC_RDPS, XXVGMAC_RDPS_HALF); + wr_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan, value); + + /* Use one-to-one mapping between VDMA, TC, and PDMA. */ + tc =3D chan; + + /* 1-to-1 PDMA to TC mapping */ + value =3D rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan); + value &=3D ~XXVGMAC_RP2TCMP; + value |=3D FIELD_PREP(XXVGMAC_RP2TCMP, tc); + wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan, value); + + /* 1-to-1 VDMA to TC mapping */ + value =3D readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + value &=3D ~XXVGMAC_RVDMA2TCMP; + value |=3D FIELD_PREP(XXVGMAC_RVDMA2TCMP, tc); + writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + + writel(upper_32_bits(dma_addr), + ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); + writel(lower_32_bits(dma_addr), + ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); +} diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h b/drivers/net/e= thernet/stmicro/stmmac/dw25gmac.h new file mode 100644 index 000000000000..44f9601331d5 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2024 Broadcom Corporation + * DW25GMAC definitions. + */ +#ifndef __STMMAC_DW25GMAC_H__ +#define __STMMAC_DW25GMAC_H__ + +/* Hardware features */ +#define XXVGMAC_HWFEAT_VDMA_RXCNT GENMASK(16, 12) +#define XXVGMAC_HWFEAT_VDMA_TXCNT GENMASK(22, 18) + +/* DMA Indirect Registers*/ +#define XXVGMAC_DMA_CH_IND_CONTROL 0x00003080 +#define XXVGMAC_MODE_SELECT GENMASK(27, 24) +enum dma_ch_ind_modes { + MODE_TXEXTCFG =3D 0x0, /* Tx Extended Config */ + MODE_RXEXTCFG =3D 0x1, /* Rx Extended Config */ + MODE_TXDBGSTS =3D 0x2, /* Tx Debug Status */ + MODE_RXDBGSTS =3D 0x3, /* Rx Debug Status */ + MODE_TXDESCCTRL =3D 0x4, /* Tx Descriptor control */ + MODE_RXDESCCTRL =3D 0x5, /* Rx Descriptor control */ +}; + +#define XXVGMAC_ADDR_OFFSET GENMASK(14, 8) +#define XXVGMAC_AUTO_INCR GENMASK(5, 4) +#define XXVGMAC_CMD_TYPE BIT(1) +#define XXVGMAC_OB BIT(0) +#define XXVGMAC_DMA_CH_IND_DATA 0x00003084 + +/* TX Config definitions */ +#define XXVGMAC_TXPBL GENMASK(29, 24) +#define XXVGMAC_TPBLX8_MODE BIT(19) +#define XXVGMAC_TP2TCMP GENMASK(18, 16) +#define XXVGMAC_ORRQ GENMASK(13, 8) + +/* RX Config definitions */ +#define XXVGMAC_RXPBL GENMASK(29, 24) +#define XXVGMAC_RPBLX8_MODE BIT(19) +#define XXVGMAC_RP2TCMP GENMASK(18, 16) +#define XXVGMAC_OWRQ GENMASK(13, 8) + +/* Tx Descriptor control */ +#define XXVGMAC_TXDCSZ GENMASK(2, 0) +#define XXVGMAC_TXDCSZ_0BYTES 0 +#define XXVGMAC_TXDCSZ_64BYTES 1 +#define XXVGMAC_TXDCSZ_128BYTES 2 +#define XXVGMAC_TXDCSZ_256BYTES 3 +#define XXVGMAC_TDPS GENMASK(5, 3) +#define XXVGMAC_TDPS_ZERO 0 +#define XXVGMAC_TDPS_1_8TH 1 +#define XXVGMAC_TDPS_1_4TH 2 +#define XXVGMAC_TDPS_HALF 3 +#define XXVGMAC_TDPS_3_4TH 4 + +/* Rx Descriptor control */ +#define XXVGMAC_RXDCSZ GENMASK(2, 0) +#define XXVGMAC_RXDCSZ_0BYTES 0 +#define XXVGMAC_RXDCSZ_64BYTES 1 +#define XXVGMAC_RXDCSZ_128BYTES 2 +#define XXVGMAC_RXDCSZ_256BYTES 3 +#define XXVGMAC_RDPS GENMASK(5, 3) +#define XXVGMAC_RDPS_ZERO 0 +#define XXVGMAC_RDPS_1_8TH 1 +#define XXVGMAC_RDPS_1_4TH 2 +#define XXVGMAC_RDPS_HALF 3 +#define XXVGMAC_RDPS_3_4TH 4 + +/* DWCXG_DMA_CH(#i) Registers*/ +#define XXVGMAC_DSL GENMASK(20, 18) +#define XXVGMAC_MSS GENMASK(13, 0) +#define XXVGMAC_TFSEL GENMASK(30, 29) +#define XXVGMAC_TQOS GENMASK(27, 24) +#define XXVGMAC_IPBL BIT(15) +#define XXVGMAC_TVDMA2TCMP GENMASK(6, 4) +#define XXVGMAC_RPF BIT(31) +#define XXVGMAC_RVDMA2TCMP GENMASK(30, 28) +#define XXVGMAC_RQOS GENMASK(27, 24) + +u32 dw25gmac_decode_vdma_count(u32 regval); + +void dw25gmac_dma_init(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg); + +void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv, + void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_addr, u32 chan); +void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv, + void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_addr, u32 chan); +#endif /* __STMMAC_DW25GMAC_H__ */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 6a2c7d22df1e..c9424c5a6ce5 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -17,6 +17,7 @@ #define XGMAC_CONFIG_SS_OFF 29 #define XGMAC_CONFIG_SS_MASK GENMASK(31, 29) #define XGMAC_CONFIG_SS_10000 (0x0 << XGMAC_CONFIG_SS_OFF) +#define XGMAC_CONFIG_SS_25000 (0x1 << XGMAC_CONFIG_SS_OFF) #define XGMAC_CONFIG_SS_2500_GMII (0x2 << XGMAC_CONFIG_SS_OFF) #define XGMAC_CONFIG_SS_1000_GMII (0x3 << XGMAC_CONFIG_SS_OFF) #define XGMAC_CONFIG_SS_100_MII (0x4 << XGMAC_CONFIG_SS_OFF) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index f519d43738b0..96013b489af6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -11,6 +11,7 @@ #include "stmmac_ptp.h" #include "dwxlgmac2.h" #include "dwxgmac2.h" +#include "dw25gmac.h" =20 static void dwxgmac2_core_init(struct mac_device_info *hw, struct net_device *dev) @@ -1670,6 +1671,47 @@ int dwxgmac2_setup(struct stmmac_priv *priv) return 0; } =20 +int dw25gmac_setup(struct stmmac_priv *priv) +{ + struct mac_device_info *mac =3D priv->hw; + + dev_info(priv->device, "\tDW25GMAC\n"); + + priv->dev->priv_flags |=3D IFF_UNICAST_FLT; + mac->pcsr =3D priv->ioaddr; + mac->multicast_filter_bins =3D priv->plat->multicast_filter_bins; + mac->unicast_filter_entries =3D priv->plat->unicast_filter_entries; + mac->mcast_bits_log2 =3D 0; + + if (mac->multicast_filter_bins) + mac->mcast_bits_log2 =3D ilog2(mac->multicast_filter_bins); + + mac->link.caps =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_1000FD | MAC_2500FD | MAC_5000FD | + MAC_10000FD | MAC_25000FD; + mac->link.duplex =3D 0; + mac->link.speed10 =3D XGMAC_CONFIG_SS_10_MII; + mac->link.speed100 =3D XGMAC_CONFIG_SS_100_MII; + mac->link.speed1000 =3D XGMAC_CONFIG_SS_1000_GMII; + mac->link.speed2500 =3D XGMAC_CONFIG_SS_2500_GMII; + mac->link.xgmii.speed2500 =3D XGMAC_CONFIG_SS_2500; + mac->link.xgmii.speed5000 =3D XGMAC_CONFIG_SS_5000; + mac->link.xgmii.speed10000 =3D XGMAC_CONFIG_SS_10000; + mac->link.xgmii.speed25000 =3D XGMAC_CONFIG_SS_25000; + mac->link.speed_mask =3D XGMAC_CONFIG_SS_MASK; + + mac->mii.addr =3D XGMAC_MDIO_ADDR; + mac->mii.data =3D XGMAC_MDIO_DATA; + mac->mii.addr_shift =3D 16; + mac->mii.addr_mask =3D GENMASK(20, 16); + mac->mii.reg_shift =3D 0; + mac->mii.reg_mask =3D GENMASK(15, 0); + mac->mii.clk_csr_shift =3D 19; + mac->mii.clk_csr_mask =3D GENMASK(21, 19); + + return 0; +} + int dwxlgmac2_setup(struct stmmac_priv *priv) { struct mac_device_info *mac =3D priv->hw; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 7840bc403788..2e86eaafd16e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -7,6 +7,7 @@ #include #include "stmmac.h" #include "dwxgmac2.h" +#include "dw25gmac.h" =20 static int dwxgmac2_dma_reset(void __iomem *ioaddr) { @@ -500,6 +501,27 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioadd= r, return 0; } =20 +static int dw25gmac_get_hw_feature(void __iomem *ioaddr, + struct dma_features *dma_cap) + +{ + u32 hw_cap; + int ret; + + ret =3D dwxgmac2_get_hw_feature(ioaddr, dma_cap); + + /* For DW25GMAC VDMA channel count is channel count */ + hw_cap =3D readl(ioaddr + XGMAC_HW_FEATURE2); + dma_cap->number_tx_channel =3D + dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_TXCNT, + hw_cap)); + dma_cap->number_rx_channel =3D + dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_RXCNT, + hw_cap)); + + return ret; +} + static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *i= oaddr, u32 riwt, u32 queue) { @@ -641,3 +663,33 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops =3D { .enable_sph =3D dwxgmac2_enable_sph, .enable_tbs =3D dwxgmac2_enable_tbs, }; + +const struct stmmac_dma_ops dw25gmac400_dma_ops =3D { + .reset =3D dwxgmac2_dma_reset, + .init =3D dw25gmac_dma_init, + .init_chan =3D dwxgmac2_dma_init_chan, + .init_rx_chan =3D dw25gmac_dma_init_rx_chan, + .init_tx_chan =3D dw25gmac_dma_init_tx_chan, + .axi =3D dwxgmac2_dma_axi, + .dump_regs =3D dwxgmac2_dma_dump_regs, + .dma_rx_mode =3D dwxgmac2_dma_rx_mode, + .dma_tx_mode =3D dwxgmac2_dma_tx_mode, + .enable_dma_irq =3D dwxgmac2_enable_dma_irq, + .disable_dma_irq =3D dwxgmac2_disable_dma_irq, + .start_tx =3D dwxgmac2_dma_start_tx, + .stop_tx =3D dwxgmac2_dma_stop_tx, + .start_rx =3D dwxgmac2_dma_start_rx, + .stop_rx =3D dwxgmac2_dma_stop_rx, + .dma_interrupt =3D dwxgmac2_dma_interrupt, + .get_hw_feature =3D dw25gmac_get_hw_feature, + .rx_watchdog =3D dwxgmac2_rx_watchdog, + .set_rx_ring_len =3D dwxgmac2_set_rx_ring_len, + .set_tx_ring_len =3D dwxgmac2_set_tx_ring_len, + .set_rx_tail_ptr =3D dwxgmac2_set_rx_tail_ptr, + .set_tx_tail_ptr =3D dwxgmac2_set_tx_tail_ptr, + .enable_tso =3D dwxgmac2_enable_tso, + .qmode =3D dwxgmac2_qmode, + .set_bfsize =3D dwxgmac2_set_bfsize, + .enable_sph =3D dwxgmac2_enable_sph, + .enable_tbs =3D dwxgmac2_enable_tbs, +}; diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ether= net/stmicro/stmmac/hwif.h index d5a9f01ecac5..774ea8cd5ae9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h @@ -702,6 +702,7 @@ extern const struct stmmac_desc_ops dwxgmac210_desc_ops; extern const struct stmmac_mmc_ops dwmac_mmc_ops; extern const struct stmmac_mmc_ops dwxgmac_mmc_ops; extern const struct stmmac_est_ops dwmac510_est_ops; +extern const struct stmmac_dma_ops dw25gmac400_dma_ops; =20 #define GMAC_VERSION 0x00000020 /* GMAC CORE Version */ #define GMAC4_VERSION 0x00000110 /* GMAC4+ CORE Version */ --=20 2.34.1 From nobody Tue Nov 26 08:51:26 2024 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.144.207]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 240A518D64F; Fri, 18 Oct 2024 20:53:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 18 Oct 2024 13:53:37 -0700 (PDT) From: jitendra.vegiraju@broadcom.com To: netdev@vger.kernel.org Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, jitendra.vegiraju@broadcom.com, bcm-kernel-feedback-list@broadcom.com, richardcochran@gmail.com, ast@kernel.org, daniel@iogearbox.net, hawk@kernel.org, john.fastabend@gmail.com, fancer.lancer@gmail.com, rmk+kernel@armlinux.org.uk, ahalaney@redhat.com, xiaolei.wang@windriver.com, rohan.g.thomas@intel.com, Jianheng.Zhang@synopsys.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org, andrew@lunn.ch, linux@armlinux.org.uk, horms@kernel.org, florian.fainelli@broadcom.com, quic_abchauha@quicinc.com Subject: [PATCH net-next v6 3/5] net: stmmac: Integrate dw25gmac into stmmac hwif handling Date: Fri, 18 Oct 2024 13:53:30 -0700 Message-Id: <20241018205332.525595-4-jitendra.vegiraju@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> References: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitendra Vegiraju Integrate dw25gmac support into stmmac hardware interface handling. Added a new entry to the stmmac_hw table in hwif.c. Since BCM8958x is an early adopter device, the synopsis_id reported in HW is 0x32 and device_id is DWXGMAC_ID. Provide override support by giving preference to snps_id, dev_id values when initialized to non-zero values by glue driver. Signed-off-by: Jitendra Vegiraju --- drivers/net/ethernet/stmicro/stmmac/hwif.c | 26 +++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ether= net/stmicro/stmmac/hwif.c index 88cce28b2f98..b8ee7bf20037 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c @@ -257,6 +257,27 @@ static const struct stmmac_hwif_entry { .est =3D &dwmac510_est_ops, .setup =3D dwxgmac2_setup, .quirks =3D NULL, + }, { + .gmac =3D false, + .gmac4 =3D false, + .xgmac =3D true, + .min_id =3D DW25GMAC_CORE_4_00, + .dev_id =3D DW25GMAC_ID, + .regs =3D { + .ptp_off =3D PTP_XGMAC_OFFSET, + .mmc_off =3D MMC_XGMAC_OFFSET, + .est_off =3D EST_XGMAC_OFFSET, + }, + .desc =3D &dwxgmac210_desc_ops, + .dma =3D &dw25gmac400_dma_ops, + .mac =3D &dwxgmac210_ops, + .hwtimestamp =3D &stmmac_ptp, + .mode =3D NULL, + .tc =3D &dwmac510_tc_ops, + .mmc =3D &dwxgmac_mmc_ops, + .est =3D &dwmac510_est_ops, + .setup =3D dw25gmac_setup, + .quirks =3D NULL, }, { .gmac =3D false, .gmac4 =3D false, @@ -292,7 +313,10 @@ int stmmac_hwif_init(struct stmmac_priv *priv) u32 id, dev_id =3D 0; int i, ret; =20 - if (needs_gmac) { + if (priv->plat->snps_id && priv->plat->dev_id) { + id =3D priv->plat->snps_id; + dev_id =3D priv->plat->dev_id; + } else if (needs_gmac) { id =3D stmmac_get_id(priv, GMAC_VERSION); } else if (needs_gmac4 || needs_xgmac) { id =3D stmmac_get_id(priv, GMAC4_VERSION); --=20 2.34.1 From nobody Tue Nov 26 08:51:26 2024 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.144.208]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD1BF18D658; Fri, 18 Oct 2024 20:53:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.144.208 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729284828; cv=none; b=sE/JzvlUyGoPiRwmTbwwQE+QT3lu9hXSzaCvJgpYO6x9+Ftf1An+wU/6arp0AhBp/EcafzDazfdk5e58raJ3ydLFyiiG+EX8c93vwok14gXrmZ5FW4paXNbmrpIWoditL9sv2dxNULyNR16/NKPchcTLxJQEyM7BFmhTFWW8B74= ARC-Message-Signature: i=1; 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charset="utf-8" From: Jitendra Vegiraju Add PCI ethernet driver support for Broadcom BCM8958x SoC devices used in automotive applications. This SoC device has PCIe ethernet MAC attached to an integrated ethernet switch using XGMII interface. The PCIe ethernet controller is presented to the Linux host as PCI network device. The following block diagram gives an overview of the application. +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ | Host CPU/Linux | +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ || PCIe || +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ | +--------------+ | | | PCIE Endpoint| | | | Ethernet | | | | Controller | | | | DMA | | | +--------------+ | | | MAC | BCM8958X | | +--------------+ SoC | | || XGMII | | || | | +--------------+ | | | Ethernet | | | | switch | | | +--------------+ | | || || || || | +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ || || || || More external interfaces The MAC IP block on BCM8958x is based on Synopsis XGMAC 4.00a core. This driver uses common dwxgmac2 code where applicable. Driver functionality specific to this MAC is implemented in dw25gmac.c. Management of integrated ethernet switch on this SoC is not handled by the PCIe interface. Since BCM8958x is an early adopter device, override the hardware reported synopsis versions with actual DW25MAC versions that support hdma. This SoC device has PCIe ethernet MAC directly attached to an integrated ethernet switch using XGMII interface. Since device tree support is not available on this platform, a software node is created to enable fixed-link support using phylink driver. Signed-off-by: Jitendra Vegiraju --- .../net/ethernet/stmicro/stmmac/dwmac-brcm.c | 478 ++++++++++++++++++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 26 + 2 files changed, 504 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac-brcm.c new file mode 100644 index 000000000000..d245af503fe8 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c @@ -0,0 +1,478 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2024 Broadcom Corporation + * + * PCI driver for ethernet interface of BCM8958X automotive switch chip. + * + * High level block diagram of the device. + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ + * | Host CPU/Linux | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ + * || PCIe + * || + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ + * | +--------------+ | + * | | PCIE Endpoint| | + * | | Ethernet | | + * | | Controller | | + * | | DMA | | + * | +--------------+ | + * | | MAC | BCM8958X | + * | +--------------+ SoC | + * | || XGMII | + * | || | + * | +--------------+ | + * | | Ethernet | | + * | | switch | | + * | +--------------+ | + * | || || || || | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ + * || || || || More external interfaces + * + * This SoC device has PCIe ethernet MAC directly attached to an integrated + * ethernet switch using XGMII interface. Since devicetree support is not + * available on this platform, a software node is created to enable + * fixed-link support using phylink driver. + */ + +#include +#include +#include +#include + +#include "stmmac.h" +#include "dwxgmac2.h" +#include "dw25gmac.h" + +#define PCI_DEVICE_ID_BROADCOM_BCM8958X 0xa00d +#define BRCM_MAX_MTU 1500 + +/* TX and RX Queue counts */ +#define BRCM_TX_Q_COUNT 4 +#define BRCM_RX_Q_COUNT 4 + +#define BRCM_XGMAC_BAR0_MASK BIT(0) + +#define BRCM_XGMAC_IOMEM_MISC_REG_OFFSET 0x0 +#define BRCM_XGMAC_IOMEM_MBOX_REG_OFFSET 0x1000 +#define BRCM_XGMAC_IOMEM_CFG_REG_OFFSET 0x3000 + +#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW 0x940 +#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE 0x00000001 +#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH 0x944 +#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE 0x88000000 + +#define XGMAC_PCIE_MISC_MII_CTRL_OFFSET 0x4 +#define XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX BIT(0) +#define XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX BIT(1) +#define XGMAC_PCIE_MISC_MII_CTRL_LINK_UP BIT(2) +#define XGMAC_PCIE_MISC_PCIESS_CTRL_OFFSET 0x8 +#define XGMAC_PCIE_MISC_PCIESS_CTRL_EN_MSI_MSIX BIT(9) +#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET 0x90 +#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE 0x00000001 +#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET 0x94 +#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE 0x88000000 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_OFFSET 0x700 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_VALUE 1 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_OFFSET 0x704 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_VALUE 1 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_OFFSET 0x728 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_VALUE 1 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_OFFSET 0x740 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_VALUE 0 + +/* MSIX Vector map register starting offsets */ +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_RX0_PF0_OFFSET 0x840 +#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_TX0_PF0_OFFSET 0x890 +#define BRCM_MAX_DMA_CHANNEL_PAIRS 4 +#define BRCM_XGMAC_MSI_MAC_VECTOR 0 +#define BRCM_XGMAC_MSI_RX_VECTOR_START 1 +#define BRCM_XGMAC_MSI_TX_VECTOR_START 2 +#define BRCM_XGMAC_MSI_VECTOR_MAX (BRCM_XGMAC_MSI_RX_VECTOR_START + \ + BRCM_MAX_DMA_CHANNEL_PAIRS * 2) + +static char *fixed_link_node_name =3D "fixed-link"; + +static const struct property_entry fixed_link_properties[] =3D { + PROPERTY_ENTRY_U32("speed", 10000), + PROPERTY_ENTRY_BOOL("full-duplex"), + PROPERTY_ENTRY_BOOL("pause"), + { } +}; + +struct brcm_priv_data { + void __iomem *mbox_regs; /* MBOX Registers*/ + void __iomem *misc_regs; /* MISC Registers*/ + void __iomem *xgmac_regs; /* XGMAC Registers*/ + struct software_node fixed_link_node; +}; + +struct dwxgmac_brcm_pci_info { + int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); +}; + +static void misc_iowrite(struct brcm_priv_data *brcm_priv, + u32 reg, u32 val) +{ + iowrite32(val, brcm_priv->misc_regs + reg); +} + +static void dwxgmac_brcm_common_default_data(struct plat_stmmacenet_data *= plat) +{ + int i; + + plat->has_xgmac =3D 1; + plat->force_sf_dma_mode =3D 1; + plat->mac_port_sel_speed =3D SPEED_10000; + plat->clk_ptp_rate =3D 125000000; + plat->clk_ref_rate =3D 250000000; + plat->tx_coe =3D 1; + plat->rx_coe =3D 1; + plat->max_speed =3D SPEED_10000; + + /* Set default value for multicast hash bins */ + plat->multicast_filter_bins =3D HASH_TABLE_SIZE; + + /* Set default value for unicast filter entries */ + plat->unicast_filter_entries =3D 1; + + /* Set the maxmtu to device's default */ + plat->maxmtu =3D BRCM_MAX_MTU; + + /* Set default number of RX and TX queues to use */ + plat->tx_queues_to_use =3D BRCM_TX_Q_COUNT; + plat->rx_queues_to_use =3D BRCM_RX_Q_COUNT; + + plat->tx_sched_algorithm =3D MTL_TX_ALGORITHM_SP; + for (i =3D 0; i < plat->tx_queues_to_use; i++) { + plat->tx_queues_cfg[i].use_prio =3D false; + plat->tx_queues_cfg[i].prio =3D 0; + plat->tx_queues_cfg[i].mode_to_use =3D MTL_QUEUE_AVB; + } + + plat->rx_sched_algorithm =3D MTL_RX_ALGORITHM_SP; + for (i =3D 0; i < plat->rx_queues_to_use; i++) { + plat->rx_queues_cfg[i].use_prio =3D false; + plat->rx_queues_cfg[i].mode_to_use =3D MTL_QUEUE_AVB; + plat->rx_queues_cfg[i].pkt_route =3D 0x0; + plat->rx_queues_cfg[i].chan =3D i; + } +} + +static int dwxgmac_brcm_default_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + /* Set common default data first */ + dwxgmac_brcm_common_default_data(plat); + + plat->snps_id =3D DW25GMAC_CORE_4_00; + plat->dev_id =3D DW25GMAC_ID; + plat->bus_id =3D 0; + plat->phy_addr =3D 0; + plat->phy_interface =3D PHY_INTERFACE_MODE_XGMII; + + plat->dma_cfg->pbl =3D 32; + plat->dma_cfg->pblx8 =3D 0; + plat->dma_cfg->aal =3D 0; + plat->dma_cfg->eame =3D 1; + + plat->axi->axi_wr_osr_lmt =3D 31; + plat->axi->axi_rd_osr_lmt =3D 31; + plat->axi->axi_fb =3D 0; + plat->axi->axi_blen[0] =3D 4; + plat->axi->axi_blen[1] =3D 8; + plat->axi->axi_blen[2] =3D 16; + plat->axi->axi_blen[3] =3D 32; + plat->axi->axi_blen[4] =3D 64; + plat->axi->axi_blen[5] =3D 128; + plat->axi->axi_blen[6] =3D 256; + + return 0; +} + +static struct dwxgmac_brcm_pci_info dwxgmac_brcm_pci_info =3D { + .setup =3D dwxgmac_brcm_default_data, +}; + +static void brcm_config_misc_regs(struct pci_dev *pdev, + struct brcm_priv_data *brcm_priv) +{ + pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW, + XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE); + pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH, + XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE); + + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET, + XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE); + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET, + XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE); + + /* Enable Switch Link */ + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MII_CTRL_OFFSET, + XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX | + XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX | + XGMAC_PCIE_MISC_MII_CTRL_LINK_UP); +} + +static int brcm_config_multi_msi(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat, + struct stmmac_resources *res) +{ + int ret; + int i; + + ret =3D pci_alloc_irq_vectors(pdev, BRCM_XGMAC_MSI_VECTOR_MAX, + BRCM_XGMAC_MSI_VECTOR_MAX, + PCI_IRQ_MSI | PCI_IRQ_MSIX); + if (ret < 0) { + dev_err(&pdev->dev, "%s: multi MSI enablement failed\n", + __func__); + return ret; + } + + /* For RX MSI */ + for (i =3D 0; i < plat->rx_queues_to_use; i++) + res->rx_irq[i] =3D + pci_irq_vector(pdev, + BRCM_XGMAC_MSI_RX_VECTOR_START + i * 2); + + /* For TX MSI */ + for (i =3D 0; i < plat->tx_queues_to_use; i++) + res->tx_irq[i] =3D + pci_irq_vector(pdev, + BRCM_XGMAC_MSI_TX_VECTOR_START + i * 2); + + res->irq =3D pci_irq_vector(pdev, BRCM_XGMAC_MSI_MAC_VECTOR); + + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; + plat->flags |=3D STMMAC_FLAG_TSO_EN; + + return 0; +} + +static int dwxgmac_brcm_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct dwxgmac_brcm_pci_info *info =3D + (struct dwxgmac_brcm_pci_info *)id->driver_data; + struct plat_stmmacenet_data *plat; + struct brcm_priv_data *brcm_priv; + struct stmmac_resources res; + struct device *dev; + int rx_offset; + int tx_offset; + int vector; + int ret; + + dev =3D &pdev->dev; + + brcm_priv =3D devm_kzalloc(&pdev->dev, sizeof(*brcm_priv), GFP_KERNEL); + if (!brcm_priv) + return -ENOMEM; + + plat =3D devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); + if (!plat) + return -ENOMEM; + + plat->dma_cfg =3D devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), + GFP_KERNEL); + if (!plat->dma_cfg) + return -ENOMEM; + + plat->axi =3D devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL); + if (!plat->axi) + return -ENOMEM; + + /* This device is directly attached to the switch chip internal to the + * SoC using XGMII interface. Since no MDIO is present, register + * fixed-link software_node to create phylink. + */ + plat->port_node =3D fwnode_create_software_node(NULL, NULL); + brcm_priv->fixed_link_node.name =3D fixed_link_node_name; + brcm_priv->fixed_link_node.properties =3D fixed_link_properties; + brcm_priv->fixed_link_node.parent =3D to_software_node(plat->port_node); + device_add_software_node(dev, &brcm_priv->fixed_link_node); + + /* Disable D3COLD as our device does not support it */ + pci_d3cold_disable(pdev); + + /* Enable PCI device */ + ret =3D pcim_enable_device(pdev); + if (ret) { + dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", + __func__); + return ret; + } + + /* Get the base address of device */ + ret =3D pcim_iomap_regions(pdev, BRCM_XGMAC_BAR0_MASK, pci_name(pdev)); + if (ret) + return ret; + pci_set_master(pdev); + + memset(&res, 0, sizeof(res)); + res.addr =3D pcim_iomap_table(pdev)[0]; + /* MISC Regs */ + brcm_priv->misc_regs =3D res.addr + BRCM_XGMAC_IOMEM_MISC_REG_OFFSET; + /* MBOX Regs */ + brcm_priv->mbox_regs =3D res.addr + BRCM_XGMAC_IOMEM_MBOX_REG_OFFSET; + /* XGMAC config Regs */ + res.addr +=3D BRCM_XGMAC_IOMEM_CFG_REG_OFFSET; + brcm_priv->xgmac_regs =3D res.addr; + + plat->bsp_priv =3D brcm_priv; + + ret =3D info->setup(pdev, plat); + if (ret) + return ret; + + pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW, + XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE); + pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH, + XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE); + + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET, + XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE); + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET, + XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE); + + /* SBD Interrupt */ + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_OFFSET, + XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_VALUE); + /* EP_DOORBELL Interrupt */ + misc_iowrite(brcm_priv, + XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_OFFSET, + XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_VALUE); + /* EP_H0 Interrupt */ + misc_iowrite(brcm_priv, + XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_OFFSET, + XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_VALUE); + /* EP_H1 Interrupt */ + misc_iowrite(brcm_priv, + XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_OFFSET, + XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_VALUE); + + rx_offset =3D XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_RX0_PF0_OFFSET; + tx_offset =3D XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_TX0_PF0_OFFSET; + vector =3D BRCM_XGMAC_MSI_RX_VECTOR_START; + for (int i =3D 0; i < BRCM_MAX_DMA_CHANNEL_PAIRS; i++) { + /* RX Interrupt */ + misc_iowrite(brcm_priv, rx_offset, vector++); + /* TX Interrupt */ + misc_iowrite(brcm_priv, tx_offset, vector++); + rx_offset +=3D 4; + tx_offset +=3D 4; + } + + /* Enable Switch Link */ + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MII_CTRL_OFFSET, + XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX | + XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX | + XGMAC_PCIE_MISC_MII_CTRL_LINK_UP); + /* Enable MSI-X */ + misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_PCIESS_CTRL_OFFSET, + XGMAC_PCIE_MISC_PCIESS_CTRL_EN_MSI_MSIX); + + ret =3D brcm_config_multi_msi(pdev, plat, &res); + if (ret) { + dev_err(&pdev->dev, + "%s: ERROR: failed to enable IRQ\n", __func__); + goto err_disable_msi; + } + + ret =3D stmmac_dvr_probe(&pdev->dev, plat, &res); + if (ret) + goto err_disable_msi; + + return ret; + +err_disable_msi: + pci_free_irq_vectors(pdev); + + return ret; +} + +static void dwxgmac_brcm_software_node_remove(struct pci_dev *pdev) +{ + struct fwnode_handle *fwnode; + struct stmmac_priv *priv; + struct net_device *ndev; + struct device *dev; + + dev =3D &pdev->dev; + ndev =3D dev_get_drvdata(dev); + priv =3D netdev_priv(ndev); + fwnode =3D priv->plat->port_node; + + fwnode_remove_software_node(fwnode); + device_remove_software_node(dev); +} + +static void dwxgmac_brcm_pci_remove(struct pci_dev *pdev) +{ + stmmac_dvr_remove(&pdev->dev); + pci_free_irq_vectors(pdev); + pcim_iounmap_regions(pdev, BRCM_XGMAC_BAR0_MASK); + pci_clear_master(pdev); + dwxgmac_brcm_software_node_remove(pdev); +} + +static int __maybe_unused dwxgmac_brcm_pci_suspend(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + int ret; + + ret =3D stmmac_suspend(dev); + if (ret) + return ret; + + ret =3D pci_save_state(pdev); + if (ret) + return ret; + + pci_disable_device(pdev); + pci_wake_from_d3(pdev, true); + + return 0; +} + +static int __maybe_unused dwxgmac_brcm_pci_resume(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + struct stmmac_priv *priv; + struct net_device *ndev; + + ndev =3D dev_get_drvdata(dev); + priv =3D netdev_priv(ndev); + brcm_config_misc_regs(pdev, priv->plat->bsp_priv); + + pci_restore_state(pdev); + pci_set_power_state(pdev, PCI_D0); + + return stmmac_resume(dev); +} + +static SIMPLE_DEV_PM_OPS(dwxgmac_brcm_pm_ops, + dwxgmac_brcm_pci_suspend, + dwxgmac_brcm_pci_resume); + +static const struct pci_device_id dwxgmac_brcm_id_table[] =3D { + { PCI_DEVICE_DATA(BROADCOM, BCM8958X, &dwxgmac_brcm_pci_info) }, + {} +}; + +MODULE_DEVICE_TABLE(pci, dwxgmac_brcm_id_table); + +static struct pci_driver dwxgmac_brcm_pci_driver =3D { + .name =3D "brcm-bcm8958x", + .id_table =3D dwxgmac_brcm_id_table, + .probe =3D dwxgmac_brcm_pci_probe, + .remove =3D dwxgmac_brcm_pci_remove, + .driver =3D { + .pm =3D &dwxgmac_brcm_pm_ops, + }, +}; + +module_pci_driver(dwxgmac_brcm_pci_driver); + +MODULE_DESCRIPTION("Broadcom 10G Automotive Ethernet PCIe driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index d3895d7eecfc..5b2ff7dbd47e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1040,6 +1040,32 @@ static void stmmac_mac_link_up(struct phylink_config= *config, default: return; } + } else if (interface =3D=3D PHY_INTERFACE_MODE_XGMII) { + switch (speed) { + case SPEED_25000: + ctrl |=3D priv->hw->link.xgmii.speed25000; + break; + case SPEED_10000: + ctrl |=3D priv->hw->link.xgmii.speed10000; + break; + case SPEED_5000: + ctrl |=3D priv->hw->link.xgmii.speed5000; + break; + case SPEED_2500: + ctrl |=3D priv->hw->link.xgmii.speed2500; + break; + case SPEED_1000: + ctrl |=3D priv->hw->link.speed1000; + break; + case SPEED_100: + ctrl |=3D priv->hw->link.speed100; + break; + case SPEED_10: + ctrl |=3D priv->hw->link.speed10; + break; + default: + return; + } } else if (interface =3D=3D PHY_INTERFACE_MODE_XLGMII) { switch (speed) { case SPEED_100000: --=20 2.34.1 From nobody Tue Nov 26 08:51:26 2024 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.144.209]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABE5718D650; Fri, 18 Oct 2024 20:53:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.144.209 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729284827; cv=none; b=eGZRatEDcPusxrqIDBo0X3gaSNhTdGYMkQ87r1diV6/i6i3lKxjwCPyrQuvDaUisIvHIx7rt0WXPFUIjT+tgZsd5w6+7kfMCFcksf4rd0zfeMpD2VhP799PoITMCssIoksfrG2JQKjaJj1dN3zmfpyf+vqEqRJYyRsKolpKE6n4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729284827; c=relaxed/simple; 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Fri, 18 Oct 2024 13:53:39 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 3294FC003ABA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1729284819; bh=B5pHMQe6V0dWAA56a9Ep6qiKIoCxDAhjKJta+dS+6/0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cCfO/fPYCA+519rhhFetz0g8qOyEBrpselvj9Vya4G5HLdPoRUb6GNOiofUN8PBVq g2RIeSpWbGC++rs6YCe3bETjhxo3+vi0uvy/ie/jy6hHh0UIT/HknNEc100fKOq2Xm 7Hptqwh1ZypKP97gKNhC0TSyp+qhVhrLTfbdMO8E= Received: from pcie-dev03.dhcp.broadcom.net (pcie-dev03.dhcp.broadcom.net [10.59.171.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPSA id 80F5818041CAC6; Fri, 18 Oct 2024 13:53:38 -0700 (PDT) From: jitendra.vegiraju@broadcom.com To: netdev@vger.kernel.org Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, jitendra.vegiraju@broadcom.com, bcm-kernel-feedback-list@broadcom.com, richardcochran@gmail.com, ast@kernel.org, daniel@iogearbox.net, hawk@kernel.org, john.fastabend@gmail.com, fancer.lancer@gmail.com, rmk+kernel@armlinux.org.uk, ahalaney@redhat.com, xiaolei.wang@windriver.com, rohan.g.thomas@intel.com, Jianheng.Zhang@synopsys.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org, andrew@lunn.ch, linux@armlinux.org.uk, horms@kernel.org, florian.fainelli@broadcom.com, quic_abchauha@quicinc.com Subject: [PATCH net-next v6 5/5] net: stmmac: Add BCM8958x driver to build system Date: Fri, 18 Oct 2024 13:53:32 -0700 Message-Id: <20241018205332.525595-6-jitendra.vegiraju@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> References: <20241018205332.525595-1-jitendra.vegiraju@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitendra Vegiraju Add PCI driver for BCM8958x to the linux build system and update MAINTAINERS file. Signed-off-by: Jitendra Vegiraju --- MAINTAINERS | 8 ++++++++ drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +++++++++++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + 3 files changed, 20 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d678a58c0205..f5ded80446d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4464,6 +4464,14 @@ N: brcmstb N: bcm7038 N: bcm7120 =20 +BROADCOM BCM8958X ETHERNET DRIVER +M: Jitendra Vegiraju +R: Broadcom internal kernel review list +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/stmicro/stmmac/dw25gmac.* +F: drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c + BROADCOM BCMBCA ARM ARCHITECTURE M: William Zhang M: Anand Gore diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 05cc07b8f48c..47c9db123b03 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -298,6 +298,17 @@ config DWMAC_LOONGSON This selects the LOONGSON PCI bus support for the stmmac driver, Support for ethernet controller on Loongson-2K1000 SoC and LS7A1000 bri= dge. =20 +config DWMAC_BRCM + tristate "Broadcom XGMAC support" + depends on STMMAC_ETH && PCI + depends on COMMON_CLK + help + Support for ethernet controllers on Broadcom BCM8958x SoCs. + + This selects Broadcom XGMAC specific PCI bus support for the + stmmac driver. This driver provides the glue layer on top of the + stmmac driver required for the Broadcom BCM8958x SoC devices. + config STMMAC_PCI tristate "STMMAC PCI bus support" depends on STMMAC_ETH && PCI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index 967e8a9aa432..517981b9e93a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -41,4 +41,5 @@ dwmac-altr-socfpga-objs :=3D dwmac-socfpga.o obj-$(CONFIG_STMMAC_PCI) +=3D stmmac-pci.o obj-$(CONFIG_DWMAC_INTEL) +=3D dwmac-intel.o obj-$(CONFIG_DWMAC_LOONGSON) +=3D dwmac-loongson.o +obj-$(CONFIG_DWMAC_BRCM) +=3D dwmac-brcm.o stmmac-pci-objs:=3D stmmac_pci.o --=20 2.34.1