From nobody Tue Nov 26 10:53:46 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9088A212D1A; Fri, 18 Oct 2024 20:31:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729283502; cv=none; b=npA5Hy/KJBSqBvs2u1VLBk3FFqfhuyGlmgJfbG/jWOtWsU+ENn8hB7l+/vTM30tCikaGiLz8kbSbfPbBdQNEuagFMX6hqJhr6IzIU4DOzAgN8It17IZ1VuGiY6gG8xu7kpFIlQytM229KsXUc2h8YJPY0oLiVPzRqVAjYBaj3h0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729283502; c=relaxed/simple; bh=Fj/8NKTV5uK5CJ66XD0//mKsX90Okyu8DByGYjiDSeA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=npkELlfQ+xV4y2pWNpQWOM5NOiVFuB9SSxsZux1mUn+ezFbacAbhaag6crPn3+s2Ufh6zaDkZx45WTv2dFNE5jic2OMKnL37xInnIdF19aCzZAiq2GmSG0tIvrW+rN9GnXcV0iE1vpe9H9STIFOXb5l6O1u9ulY+CCGUgolwBf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=ByTccqxF; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="ByTccqxF" Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49IEPYPH001361; Fri, 18 Oct 2024 13:31:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=m aWJua9+JGzP7BnlMk+LeZpIIL5TRzHIue5sz8vH9Q4=; b=ByTccqxF1mzqhN4mn sm9mzihO3PdSh1h7lUmKLirSG1gXYO8w20bnxTsvQkej1rpPLlfIrY09DJsSR7WP 1jWdoM46W9/QfAmgljP/n4u+d+L/YeJzAxqm4lMk+0DuRgnRQj8Nsc0QRhxgyGDN WXlxGagrXb0ltM8WMxcznkcxrevghPmynIthpLUHJ18TUwJ9La55RFUdss8osMhx TLyWjK8oBzoceZZexVpZV31eivIOt7E+dCPwm1ELH0y1nF5M4uMIEd+WwT/WeROx +IxzP9thImHhFqKMU1i2wytWPRl4b5/TM/+l4vlmcaYKCDPYysVwycXZS5OKr9cE CA5qg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 42bse6ru97-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Oct 2024 13:31:32 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 18 Oct 2024 13:31:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 18 Oct 2024 13:31:30 -0700 Received: from hyd1425.marvell.com (unknown [10.29.37.152]) by maili.marvell.com (Postfix) with ESMTP id 1E8593F704C; Fri, 18 Oct 2024 13:31:26 -0700 (PDT) From: Sai Krishna To: , , , , , , , , , , , CC: Sai Krishna Subject: [net-next PATCH 6/6] octeontx2-pf: CN20K mbox implementation between PF-VF Date: Sat, 19 Oct 2024 02:00:58 +0530 Message-ID: <20241018203058.3641959-7-saikrishnag@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018203058.3641959-1-saikrishnag@marvell.com> References: <20241018203058.3641959-1-saikrishnag@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Z-MdKzW6TrQSXnP-PYgimHTu7-OtU5mK X-Proofpoint-GUID: Z-MdKzW6TrQSXnP-PYgimHTu7-OtU5mK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" This patch implements the CN20k MBOX communication between PF and it's VFs. CN20K silicon got extra interrupt of MBOX response for trigger interrupt. Also few of the CSR offsets got changed in CN20K against prior series of silicons. Signed-off-by: Sunil Kovvuri Goutham Signed-off-by: Sai Krishna --- .../ethernet/marvell/octeontx2/nic/cn20k.c | 142 ++++++++++++++++++ .../ethernet/marvell/octeontx2/nic/cn20k.h | 3 + .../marvell/octeontx2/nic/otx2_common.h | 2 + .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 59 ++++++-- 4 files changed, 193 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn20k.c index 219a0b1d0c9b..8a130a2771b1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c @@ -13,6 +13,7 @@ static struct dev_hw_ops cn20k_hw_ops =3D { .pfaf_mbox_intr_handler =3D cn20k_pfaf_mbox_intr_handler, .vfaf_mbox_intr_handler =3D cn20k_vfaf_mbox_intr_handler, + .pfvf_mbox_intr_handler =3D cn20k_pfvf_mbox_intr_handler, }; =20 int cn20k_init(struct otx2_nic *pfvf) @@ -110,3 +111,144 @@ irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, voi= d *vf_irq) =20 return IRQ_HANDLED; } + +void cn20k_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) +{ + /* Clear PF <=3D> VF mailbox IRQ */ + otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(1), ~0ull); + + /* Enable PF <=3D> VF mailbox IRQ */ + otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(0), INTR_MASK(numvfs)); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(0), INTR_MASK(numvfs)); + if (numvfs > 64) { + numvfs -=3D 64; + otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(1), + INTR_MASK(numvfs)); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(1), + INTR_MASK(numvfs)); + } +} + +void cn20k_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) +{ + int vector, intr_vec, vec =3D 0; + + /* Disable PF <=3D> VF mailbox IRQ */ + otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(0), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(1), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(0), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(1), ~0ull); + + otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull); + + if (numvfs > 64) { + otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull); + otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(1), ~0ull); + } + + for (intr_vec =3D RVU_MBOX_PF_INT_VEC_VFPF_MBOX0; intr_vec <=3D + RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1; intr_vec++, vec++) { + vector =3D pci_irq_vector(pf->pdev, intr_vec); + free_irq(vector, pf->hw.pfvf_irq_devid[vec]); + } +} + +irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq) +{ + struct pf_irq_data *irq_data =3D (struct pf_irq_data *)(pf_irq); + struct otx2_nic *pf =3D irq_data->pf; + struct mbox *mbox; + u64 intr; + + /* Sync with mbox memory region */ + rmb(); + + /* Clear interrupts */ + intr =3D otx2_read64(pf, irq_data->intr_status); + otx2_write64(pf, irq_data->intr_status, intr); + mbox =3D pf->mbox_pfvf; + + if (intr) + trace_otx2_msg_interrupt(pf->pdev, "VF(s) to PF", intr); + + irq_data->pf_queue_work_hdlr(mbox, pf->mbox_pfvf_wq, irq_data->start, + irq_data->mdevs, intr); + + return IRQ_HANDLED; +} + +int cn20k_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) +{ + struct otx2_hw *hw =3D &pf->hw; + struct pf_irq_data *irq_data; + int intr_vec, ret, vec =3D 0; + char *irq_name; + + /* irq data for 4 PF intr vectors */ + irq_data =3D devm_kcalloc(pf->dev, 4, + sizeof(struct pf_irq_data), GFP_KERNEL); + if (!irq_data) + return -ENOMEM; + + for (intr_vec =3D RVU_MBOX_PF_INT_VEC_VFPF_MBOX0; intr_vec <=3D + RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1; intr_vec++, vec++) { + switch (intr_vec) { + case RVU_MBOX_PF_INT_VEC_VFPF_MBOX0: + irq_data[vec].intr_status =3D + RVU_MBOX_PF_VFPF_INTX(0); + irq_data[vec].start =3D 0; + irq_data[vec].mdevs =3D 64; + break; + case RVU_MBOX_PF_INT_VEC_VFPF_MBOX1: + irq_data[vec].intr_status =3D + RVU_MBOX_PF_VFPF_INTX(1); + irq_data[vec].start =3D 64; + irq_data[vec].mdevs =3D 96; + break; + case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0: + irq_data[vec].intr_status =3D + RVU_MBOX_PF_VFPF1_INTX(0); + irq_data[vec].start =3D 0; + irq_data[vec].mdevs =3D 64; + break; + case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1: + irq_data[vec].intr_status =3D + RVU_MBOX_PF_VFPF1_INTX(1); + irq_data[vec].start =3D 64; + irq_data[vec].mdevs =3D 96; + break; + } + irq_data[vec].pf_queue_work_hdlr =3D otx2_queue_vf_work; + irq_data[vec].vec_num =3D intr_vec; + irq_data[vec].pf =3D pf; + + /* Register mailbox interrupt handler */ + irq_name =3D &hw->irq_name[intr_vec * NAME_SIZE]; + if (pf->pcifunc) + snprintf(irq_name, NAME_SIZE, + "RVUPF%d_VF%d Mbox%d", rvu_get_pf(pf->pcifunc), + vec / 2, vec % 2); + else + snprintf(irq_name, NAME_SIZE, "RVUPF_VF%d Mbox%d", + vec / 2, vec % 2); + + hw->pfvf_irq_devid[vec] =3D &irq_data[vec]; + ret =3D request_irq(pci_irq_vector(pf->pdev, intr_vec), + pf->hw_ops->pfvf_mbox_intr_handler, 0, + irq_name, + &irq_data[vec]); + if (ret) { + dev_err(pf->dev, + "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); + return ret; + } + } + + cn20k_enable_pfvf_mbox_intr(pf, numvfs); + + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn20k.h index da6210042c62..763acaa31650 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h @@ -11,4 +11,7 @@ #include "otx2_common.h" =20 int cn20k_init(struct otx2_nic *pfvf); +int cn20k_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs); +void cn20k_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs); +void cn20k_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs); #endif /* CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index edebdd9ce1e1..e56df7aa1d57 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -57,6 +57,7 @@ irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq); irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq); irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, void *vf_irq); +irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq); irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq); =20 enum arua_mapped_qtypes { @@ -382,6 +383,7 @@ struct dev_hw_ops { void (*aura_freeptr)(void *dev, int aura, u64 buf); irqreturn_t (*pfaf_mbox_intr_handler)(int irq, void *pf_irq); irqreturn_t (*vfaf_mbox_intr_handler)(int irq, void *pf_irq); + irqreturn_t (*pfvf_mbox_intr_handler)(int irq, void *pf_irq); }; =20 #define CN10K_MCS_SA_PER_SC 4 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 148a5c91af55..cd7d6472f5e1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -565,6 +565,23 @@ irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void = *pf_irq) return IRQ_HANDLED; } =20 +static void *cn20k_pfvf_mbox_alloc(struct otx2_nic *pf, int numvfs) +{ + struct qmem *mbox_addr; + int err; + + err =3D qmem_alloc(&pf->pdev->dev, &mbox_addr, numvfs, MBOX_SIZE); + if (err) { + dev_err(pf->dev, "qmem alloc fail\n"); + return ERR_PTR(-ENOMEM); + } + + otx2_write64(pf, RVU_PF_VF_MBOX_ADDR, (u64)mbox_addr->iova); + pf->pfvf_mbox_addr =3D mbox_addr; + + return mbox_addr->base; +} + static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) { void __iomem *hwbase; @@ -586,20 +603,28 @@ static int otx2_pfvf_mbox_init(struct otx2_nic *pf, i= nt numvfs) if (!pf->mbox_pfvf_wq) return -ENOMEM; =20 - /* On CN10K platform, PF <-> VF mailbox region follows after - * PF <-> AF mailbox region. + /* For CN20K, PF allocates mbox memory in DRAM and writes PF/VF + * regions/offsets in RVU_PF_VF_MBOX_ADDR, the RVU_PFX_FUNC_PFAF_MBOX + * gives the aliased address to access PF/VF mailbox regions. */ - if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) - base =3D pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + - MBOX_SIZE; - else - base =3D readq((void __iomem *)((u64)pf->reg_base + + if (is_cn20k(pf->pdev)) { + hwbase =3D cn20k_pfvf_mbox_alloc(pf, numvfs); + } else { + /* On CN10K platform, PF <-> VF mailbox region follows after + * PF <-> AF mailbox region. + */ + if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) + base =3D pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + + MBOX_SIZE; + else + base =3D readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR)); =20 - hwbase =3D ioremap_wc(base, MBOX_SIZE * pf->total_vfs); - if (!hwbase) { - err =3D -ENOMEM; - goto free_wq; + hwbase =3D ioremap_wc(base, MBOX_SIZE * pf->total_vfs); + if (!hwbase) { + err =3D -ENOMEM; + goto free_wq; + } } =20 mbox =3D &pf->mbox_pfvf[0]; @@ -623,7 +648,7 @@ static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int= numvfs) return 0; =20 free_iomem: - if (hwbase) + if (hwbase && !(is_cn20k(pf->pdev))) iounmap(hwbase); free_wq: destroy_workqueue(pf->mbox_pfvf_wq); @@ -642,8 +667,10 @@ static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) pf->mbox_pfvf_wq =3D NULL; } =20 - if (mbox->mbox.hwbase) + if (mbox->mbox.hwbase && !is_cn20k(pf->pdev)) iounmap(mbox->mbox.hwbase); + else + qmem_free(&pf->pdev->dev, pf->pfvf_mbox_addr); =20 otx2_mbox_destroy(&mbox->mbox); } @@ -667,6 +694,9 @@ static void otx2_disable_pfvf_mbox_intr(struct otx2_nic= *pf, int numvfs) { int vector; =20 + if (is_cn20k(pf->pdev)) + return cn20k_disable_pfvf_mbox_intr(pf, numvfs); + /* Disable PF <=3D> VF mailbox IRQ */ otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); @@ -688,6 +718,9 @@ static int otx2_register_pfvf_mbox_intr(struct otx2_nic= *pf, int numvfs) char *irq_name; int err; =20 + if (is_cn20k(pf->pdev)) + return cn20k_register_pfvf_mbox_intr(pf, numvfs); + /* Register MBOX0 interrupt handler */ irq_name =3D &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; if (pf->pcifunc) --=20 2.25.1