From nobody Tue Nov 26 13:51:40 2024 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76DA91D7E4C; Fri, 18 Oct 2024 10:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248919; cv=none; b=mjsMW6JJaDNgk7gi8+RI5lP1lQrutXj6+JhPT+fuij0FxvuhSAsI7ha8T4Boew5/dwBdKOQfGvPljX9BPbz76OY+VARZphlQ5ZPtsOwEFOlZp/5TTzoAyDGn3RP/BqLVocYKm0avxY55evxhtJEPifUN8GDq9TW4LRXudL+yrnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248919; c=relaxed/simple; bh=dXlcSJAgvLlmp2SbcO9+GbAsPb/hnuby0rypYVZ0vDI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RcTYQ5PxHblWRrPevVR7yFRGQcZn7XpdqEH0aMJT2A13zCMU69nLuaKgVR/qLPqQBJEWPHjSgMDkgdS1mNRR8Lk1fy54bZe6RloiL4FLSe9J9JTza8Qi5X5EbwQnt/keNACl+KMGRBCXDa0sdpPd0eD3MDD4JsCFXad2HlRRKUE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=uskH01RT; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="uskH01RT" Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 0BC201FAAF; Fri, 18 Oct 2024 12:55:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1729248912; bh=RpL7cRHFX05ZvjNV5sS2C29Zp9ge2OM147LKWy4YLsM=; h=From:To:Subject; b=uskH01RTuMuv/c8d7OfFlEum4z0Q9/xT726MJjjbn1MoYrwRJFF67YGIwg0QB/tXI a9BZ1NE6qqninYumkUTXwVv/I05BGfMzTcQrDiY3DcCTe8TwinRFnJfj4yxucm9tBx UmIAXLgRoddmNraHrmkGF49sJ9ODF97caZ9MTLGblpmf3ewjhxZXccJwyHsnyYSmIA Xf7YFtwRsWht2BHmcZbWS+Cc3I4TuFjZEOFACaP1tXtR08KNSyptxMtjrKmYRW52iF OugdYFwmHbrJTPj91HEQEXT2PfSdAaAT7LgqCE1hdjQNsO7GA0Eevfd60ki0cQOVS+ 0zF8vri7IvFNg== From: Francesco Dolcini To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathias Nyman , Francesco Dolcini Cc: Parth Pancholi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: usb: add TUSB73x0 PCIe Date: Fri, 18 Oct 2024 12:55:04 +0200 Message-Id: <20241018105505.28005-2-francesco@dolcini.it> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241018105505.28005-1-francesco@dolcini.it> References: <20241018105505.28005-1-francesco@dolcini.it> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI host controller. The controller supports software configuration through PCIe registers, such as controlling the PWRONx polarity via the USB control register (E0h). Similar generic PCIe-based bindings can be found as qcom,ath11k-pci.yaml as an example. Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf Signed-off-by: Parth Pancholi Signed-off-by: Francesco Dolcini --- v3: use lowercase hex in compatible v2: rename property to ti,tusb7320-pwron-active-high and change type to flag --- .../bindings/usb/ti,tusb73x0-pci.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.y= aml diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/D= ocumentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml new file mode 100644 index 000000000000..7083e24d279c --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) + +maintainers: + - Francesco Dolcini + +description: + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports = up + to four downstream ports. + +properties: + compatible: + const: pci104c,8241 + + reg: + maxItems: 1 + + ti,tusb7320-pwron-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the polarity of the PWRONx# signals. When this is present,= the PWRONx# + pins are active high and their internal pull-down resistors are disa= bled. + When this is absent, the PWRONx# pins are active low (default) and t= heir internal + pull-down resistors are enabled. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pcie { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + usb@0 { + compatible =3D "pci104c,8241"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + ti,tusb7320-pwron-active-high; + }; + }; + }; --=20 2.39.5