From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49CB02022CC; Fri, 18 Oct 2024 10:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248831; cv=none; b=gvyTpo9FJ/nTfRSa6J3HErEB9LbEIW/Wmk0zOyPeGzbZaJxSZ+n1V0gqIeLekMAUY2J3MXVOyfdK2qI+owNBtaw26FWHOJA2vAHoXiNq9Nhdq3rWQr/MFIcu6Jj69FlourFKxW8dwvPnHZbvSlFYxm0l3Jwz59PckySHZQJsHC8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248831; c=relaxed/simple; bh=DZdDj/aIIhcCK6l9+AXaZhv9BAkv4yb0qLfhakRpDnA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NSjjta4TD5xVFnBOsTMYTypv+MB+lIRdUzz9eKh/O0L+pRHdpIddyrV5mROpNfINPPWMQ3vzp77wGv8b5rzFg4ZwbFX2eqiIAbemfhgYs237QKR+wPimKcON08LNQtfgBxTWVesgnY50xB055cN/mdxxZzRnQspyQ+kc9NiWcuk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=H2m1XKgs; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="H2m1XKgs" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-20cdda5cfb6so19673685ad.3; Fri, 18 Oct 2024 03:53:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248827; x=1729853627; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X1yN2IB0IthqJ3mkj/MErjPn6DWPx9oN43GA1c0kTSw=; b=H2m1XKgsJYYtuhhy6lzUl6M11eeqCoI7RcxmtwJMj12OzTBoHmhm/5NnAkX/U68/qg A74e94g/s8pJRNTy0q1NkYHp1/oGS30PkZh8dg2xuKWWqfEPaGbja+N7XoL3ZpeObdZ5 7zl+osvFQcTsArgHmWdsDS4o1lwtFDvgHR47ZUur3CepD+zGZjUzDoDwlOvJ5HR+BMLf iyR0Jn4+psfFlAw+9hh/gZSWbs4+NnFsbOc3EIi3a86wJUcsBcyJpMr9yAwsKCHLg6wk NcYj5NAmQJqUVKAwRHpSOeuj4JqDGO/hALciI/SVr7BmqAowuCsLgJHe595kXAd20xaJ PrPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248827; x=1729853627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X1yN2IB0IthqJ3mkj/MErjPn6DWPx9oN43GA1c0kTSw=; b=TtjgaoN36tgyKEGgN1U+oPFqmLmUeSnHhfw9mBhi6xMXGuOl5tqTiDkFu/xDogi4jJ fX3ekBTfRbjjT5sO6QYeLs7e0LI6r085T6oWjvNcLQzBQtAOjO97s4YO4ERR1qS3F612 g8nSsY2Z/VjDg63lyIk0DSbff/LFD3H4kgaBGakSD9oER9L1qg0/s0AuuZZ2TLZEzNJA f/KdGWf3zp/+Fthw+13S1FWV4uNI4oPzRpzC6Oh5CJdBbxABFGo01EZTn03D1+O3Lxbq qqf8cu49Q1r3YKlsy1qeKQx0Qz85lOmeGKt2jgsxPMrK6PAdwnkX8xvjomgGSx8kMBAN S1ug== X-Forwarded-Encrypted: i=1; AJvYcCXDSudw/LTrBkUYeArRJlbYb+rUTjo2rqOstpUVUokxP90DuPqLomjyQF8NUSwCGwxbvIAuHl9PaotWMNw=@vger.kernel.org X-Gm-Message-State: AOJu0YxrQj/9YbDpWmk6QhkDmvza7uW4GEpXX+Zdx4EnL0cSreLv9Ay/ TdryEOLXtrQDpb1ogc3gfAL8dJ6ZCk5yFZegcxH4ZJx2ZclFHgKF X-Google-Smtp-Source: AGHT+IHlUxF2nad9S9x3+1E4UCN59at4D2k13rxtsaeMlNz5lO140SmZAgLiTrncO8oVKO6qARchFg== X-Received: by 2002:a17:902:e5ca:b0:20b:70b4:69d8 with SMTP id d9443c01a7336-20e5a951189mr20730195ad.37.1729248827148; Fri, 18 Oct 2024 03:53:47 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:53:46 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Jason Lai , Victor Shih Subject: [PATCH V23 01/16] mmc: core: Support UHS-II card control and access Date: Fri, 18 Oct 2024 18:53:18 +0800 Message-Id: <20241018105333.4569-2-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih Embed UHS-II access/control functionality into the MMC request processing flow. Signed-off-by: Ulf Hansson Signed-off-by: Jason Lai Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V23: - Remove mmc_uhs2_card_prepare_cmd() function. - Remove mmc_sd_can_poweroff_notify() function. - Modify ios.timing setting in the sd_uhs2_power_off() function. - Restore the position of assign the host->card to original position in the sd_uhs2_init_card() function. - Remove unnecessary error handle in the sd_uhs2_init_card() function. - Add oldcard judgment to skip some programs in the sd_uhs2_legacy_init() function. - Remove unnecessary error handle in the sd_uhs2_legacy_init() function. - Remove mmc_card_set_present() function in the sd_uhs2_reinit()function. Updates in V16: - Separate the Error Recovery mechanism into a separate patch#8. Updates in V15: - Move struct uhs2_command uhs2_cmd to struct mmc_request and modify whatever other changers to make it work. - Refer the SD Host Controller Standard Specification Section 3.10 to add Error Recovery mechanism to recover the command error. Updates in V13: - Separate __mmc_go_idle() into one patch for re-factorring the code. - Move mmc_decode_scr declaration to sd.h. - Ues uhs2_sd_tran to stead MMC_UHS2_SD_TRAN.=20 - Drop unnecessary comment. Updates in V12: - Use mmc_op_multi() to check DCMD which supports multi read/write in mmc_uhs2_prepare_cmd(). Updates in V10: - Move some definitions of PatchV9[02/23] to PatchV10[06/23]. - Move some definitions of PatchV9[05/23] to PatchV10[06/23]. - Drop do_multi in the mmc_blk_rw_rq_prep(). - Use tmode_half_duplex to instead of uhs2_tmode0_flag. - Move entire control of the tmode into mmc_uhs2_prepare_cmd(). Updates in V8: - Add MMC_UHS2_SUPPORT to be cleared in sd_uhs2_detect(). - Modify return value in sd_uhs2_attach(). Updates in V7: - Add mmc_uhs2_card_prepare_cmd helper function in sd_ops.h. - Drop uhs2_state in favor of ios->timing. - Remove unnecessary functions. --- drivers/mmc/core/core.c | 8 +- drivers/mmc/core/sd.c | 8 +- drivers/mmc/core/sd.h | 5 + drivers/mmc/core/sd_ops.c | 9 + drivers/mmc/core/sd_ops.h | 2 + drivers/mmc/core/sd_uhs2.c | 1097 ++++++++++++++++++++++++++++++++++-- include/linux/mmc/core.h | 17 + include/linux/mmc/host.h | 15 + 8 files changed, 1122 insertions(+), 39 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 54ca9dc2114c..a499f3c59de5 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -354,6 +354,9 @@ int mmc_start_request(struct mmc_host *host, struct mmc= _request *mrq) if (err) return err; =20 + if (host->uhs2_sd_tran) + mmc_uhs2_prepare_cmd(host, mrq); + led_trigger_event(host->led, LED_FULL); __mmc_start_request(host, mrq); =20 @@ -453,6 +456,9 @@ int mmc_cqe_start_req(struct mmc_host *host, struct mmc= _request *mrq) if (err) goto out_err; =20 + if (host->uhs2_sd_tran) + mmc_uhs2_prepare_cmd(host, mrq); + err =3D host->cqe_ops->cqe_request(host, mrq); if (err) goto out_err; @@ -1135,7 +1141,7 @@ u32 mmc_select_voltage(struct mmc_host *host, u32 ocr) return 0; } =20 - if (host->caps2 & MMC_CAP2_FULL_PWR_CYCLE) { + if (!mmc_card_uhs2(host) && host->caps2 & MMC_CAP2_FULL_PWR_CYCLE) { bit =3D ffs(ocr) - 1; ocr &=3D 3 << bit; mmc_power_cycle(host, ocr); diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 918b86bf8bbb..f3811b523f68 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -200,7 +200,7 @@ static int mmc_decode_csd(struct mmc_card *card, bool i= s_sduc) /* * Given a 64-bit response, decode to our card SCR structure. */ -static int mmc_decode_scr(struct mmc_card *card) +int mmc_decode_scr(struct mmc_card *card) { struct sd_scr *scr =3D &card->scr; unsigned int scr_struct; @@ -903,7 +903,7 @@ int mmc_sd_get_csd(struct mmc_card *card, bool is_sduc) return 0; } =20 -static int mmc_sd_get_ro(struct mmc_host *host) +int mmc_sd_get_ro(struct mmc_host *host) { int ro; =20 @@ -1635,7 +1635,7 @@ static void mmc_sd_detect(struct mmc_host *host) } } =20 -static int sd_can_poweroff_notify(struct mmc_card *card) +int sd_can_poweroff_notify(struct mmc_card *card) { return card->ext_power.feature_support & SD_EXT_POWER_OFF_NOTIFY; } @@ -1663,7 +1663,7 @@ static int sd_busy_poweroff_notify_cb(void *cb_data, = bool *busy) return 0; } =20 -static int sd_poweroff_notify(struct mmc_card *card) +int sd_poweroff_notify(struct mmc_card *card) { struct sd_busy_data cb_data; u8 *reg_buf; diff --git a/drivers/mmc/core/sd.h b/drivers/mmc/core/sd.h index 7e8beface2ca..0060accc3a31 100644 --- a/drivers/mmc/core/sd.h +++ b/drivers/mmc/core/sd.h @@ -11,10 +11,15 @@ struct mmc_card; =20 int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid, u32 *rocr); int mmc_sd_get_csd(struct mmc_card *card, bool is_sduc); +int mmc_decode_scr(struct mmc_card *card); +int mmc_sd_get_ro(struct mmc_host *host); void mmc_decode_cid(struct mmc_card *card); int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card, bool reinit); unsigned mmc_sd_get_max_clock(struct mmc_card *card); int mmc_sd_switch_hs(struct mmc_card *card); =20 +int sd_can_poweroff_notify(struct mmc_card *card); +int sd_poweroff_notify(struct mmc_card *card); + #endif diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index 50d1380e93b8..cd86463dd306 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -42,6 +42,15 @@ int mmc_app_cmd(struct mmc_host *host, struct mmc_card *= card) if (WARN_ON(card && card->host !=3D host)) return -EINVAL; =20 + /* + * UHS2 packet has APP bit so only set APP_CMD flag here. + * Will set the APP bit when assembling UHS2 packet. + */ + if (host->uhs2_sd_tran) { + host->uhs2_app_cmd =3D true; + return 0; + } + cmd.opcode =3D MMC_APP_CMD; =20 if (card) { diff --git a/drivers/mmc/core/sd_ops.h b/drivers/mmc/core/sd_ops.h index fd3f10b9cf86..a86c0cfa0aae 100644 --- a/drivers/mmc/core/sd_ops.h +++ b/drivers/mmc/core/sd_ops.h @@ -11,6 +11,7 @@ #include =20 struct mmc_card; +struct mmc_command; struct mmc_host; =20 int mmc_app_set_bus_width(struct mmc_card *card, int width); @@ -22,6 +23,7 @@ int mmc_app_send_scr(struct mmc_card *card); int mmc_app_sd_status(struct mmc_card *card, void *ssr); int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card); int mmc_send_ext_addr(struct mmc_host *host, u32 addr); +void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq); =20 #endif =20 diff --git a/drivers/mmc/core/sd_uhs2.c b/drivers/mmc/core/sd_uhs2.c index 19d62d45e1ec..4e6889430957 100644 --- a/drivers/mmc/core/sd_uhs2.c +++ b/drivers/mmc/core/sd_uhs2.c @@ -1,23 +1,51 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Linaro Ltd - * * Author: Ulf Hansson * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + * Author: Yi Sun + * + * Copyright (C) 2020 Genesys Logic, Inc. + * Authors: Ben Chuang + * + * Copyright (C) 2020 Linaro Limited + * Author: AKASHI Takahiro + * + * Copyright (C) 2022 Genesys Logic, Inc. + * Authors: Jason Lai + * + * Copyright (C) 2023 Genesys Logic, Inc. + * Authors: Victor Shih + * * Support for SD UHS-II cards */ #include +#include =20 #include #include +#include +#include +#include =20 +#include "card.h" #include "core.h" #include "bus.h" #include "sd.h" +#include "sd_ops.h" #include "mmc_ops.h" =20 +#define UHS2_WAIT_CFG_COMPLETE_PERIOD_US (1 * 1000) +#define UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS 100 + static const unsigned int sd_uhs2_freqs[] =3D { 52000000, 26000000 }; =20 +struct sd_uhs2_wait_active_state_data { + struct mmc_host *host; + struct mmc_command *cmd; +}; + static int sd_uhs2_power_up(struct mmc_host *host) { int err; @@ -42,12 +70,46 @@ static int sd_uhs2_power_off(struct mmc_host *host) =20 host->ios.vdd =3D 0; host->ios.clock =3D 0; + /* Must set UHS2 timing to identify UHS2 mode */ host->ios.timing =3D MMC_TIMING_LEGACY; host->ios.power_mode =3D MMC_POWER_OFF; + host->uhs2_sd_tran =3D false; =20 return host->ops->uhs2_control(host, UHS2_SET_IOS); } =20 +/* + * sd_uhs2_cmd_assemble() - build up UHS-II command packet which is embedd= ed in + * mmc_command structure + * @cmd: MMC command to executed + * @uhs2_cmd: UHS2 command corresponded to MMC command + * @header: Header field of UHS-II command cxpacket + * @arg: Argument field of UHS-II command packet + * @payload: Payload field of UHS-II command packet + * @plen: Payload length + * @resp: Response buffer is allocated by caller and it is used to keep + * the response of CM-TRAN command. For SD-TRAN command, uhs2= _resp + * should be null and SD-TRAN command response should be stor= ed in + * resp of mmc_command. + * @resp_len: Response buffer length + * + * The uhs2_command structure contains message packets which are transmite= d/ + * received on UHS-II bus. This function fills in the contents of uhs2_com= mand + * structure and embededs UHS2 command into mmc_command structure, which i= s used + * in legacy SD operation functions. + * + */ +static void sd_uhs2_cmd_assemble(struct mmc_command *cmd, + struct uhs2_command *uhs2_cmd, + u8 plen, u8 resp_len) +{ + uhs2_cmd->payload_len =3D plen * sizeof(u32); + uhs2_cmd->packet_len =3D uhs2_cmd->payload_len + 4; + + cmd->uhs2_cmd =3D uhs2_cmd; + cmd->uhs2_cmd->uhs2_resp_len =3D resp_len; +} + /* * Run the phy initialization sequence, which mainly relies on the UHS-II = host * to check that we reach the expected electrical state, between the host = and @@ -55,7 +117,15 @@ static int sd_uhs2_power_off(struct mmc_host *host) */ static int sd_uhs2_phy_init(struct mmc_host *host) { - return 0; + int err; + + err =3D host->ops->uhs2_control(host, UHS2_PHY_INIT); + if (err) { + pr_err("%s: failed to initial phy for UHS-II!\n", + mmc_hostname(host)); + } + + return err; } =20 /* @@ -64,6 +134,83 @@ static int sd_uhs2_phy_init(struct mmc_host *host) */ static int sd_uhs2_dev_init(struct mmc_host *host) { + struct mmc_command cmd =3D {0}; + struct uhs2_command uhs2_cmd =3D {}; + u32 cnt; + u32 dap, gap, resp_gap; + u8 gd =3D 0; + int err; + + dap =3D host->uhs2_caps.dap; + gap =3D host->uhs2_caps.gap; + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-21 to see DEVICE_INIT C= CMD format. + * Head: + * - Control Write(R/W=3D1) with 4-Byte payload(PLEN=3D01b). + * - IOADR =3D CMD_BASE + 002h + * Payload: + * - bit [3:0] : GAP(Group Allocated Power) + * - bit [7:4] : GD(Group Descriptor) + * - bit [11] : Complete Flag + * - bit [15:12]: DAP(Device Allocated Power) + */ + uhs2_cmd.header =3D UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; + uhs2_cmd.arg =3D ((UHS2_DEV_CMD_DEVICE_INIT & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_DEVICE_INIT >> 8); + + /* + * Refer to UHS-II Addendum Version 1.02 section 6.3.1. + * Max. time from DEVICE_INIT CCMD EOP reception on Device + * Rx to its SOP transmission on Device Tx(Tfwd_init_cmd) is + * 1 second. + */ + cmd.busy_timeout =3D 1000; + + /* + * Refer to UHS-II Addendum Version 1.02 section 6.2.6.3. + * Let's retry the DEVICE_INIT command no more than 30 times. + */ + for (cnt =3D 0; cnt < 30; cnt++) { + uhs2_cmd.payload[0] =3D ((dap & 0xF) << 12) | + UHS2_DEV_INIT_COMPLETE_FLAG | + ((gd & 0xF) << 4) | + (gap & 0xF); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_DEV_INIT_PAYLOAD_LEN, + UHS2_DEV_INIT_RESP_LEN); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + continue; + } + + if (uhs2_cmd.uhs2_resp[3] !=3D (UHS2_DEV_CMD_DEVICE_INIT & 0xFF)) { + pr_err("%s: DEVICE_INIT response is wrong!\n", + mmc_hostname(host)); + return -EIO; + } + + if (uhs2_cmd.uhs2_resp[5] & 0x8) { + host->uhs2_caps.group_desc =3D gd; + return 0; + } + resp_gap =3D uhs2_cmd.uhs2_resp[4] & 0x0F; + if (gap =3D=3D resp_gap) + gd++; + } + + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + return 0; } =20 @@ -74,6 +221,48 @@ static int sd_uhs2_dev_init(struct mmc_host *host) */ static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) { + struct mmc_command cmd =3D {0}; + struct uhs2_command uhs2_cmd =3D {}; + u8 id_f =3D 0xF, id_l =3D 0x0; + int err; + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-28 to see ENUMERATE CCM= D format. + * Header: + * - Control Write(R/W=3D1) with 4-Byte payload(PLEN=3D01b). + * - IOADR =3D CMD_BASE + 003h + * Payload: + * - bit [3:0]: ID_L(Last Node ID) + * - bit [7:4]: ID_F(First Node ID) + */ + uhs2_cmd.header =3D UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; + uhs2_cmd.arg =3D ((UHS2_DEV_CMD_ENUMERATE & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_ENUMERATE >> 8); + + uhs2_cmd.payload[0] =3D (id_f << 4) | id_l; + uhs2_cmd.payload[0] =3D cpu_to_be32(uhs2_cmd.payload[0]); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_DEV_ENUM_PAYLOAD_LEN, UHS2_DEV= _ENUM_RESP_LEN); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if (uhs2_cmd.uhs2_resp[3] !=3D (UHS2_DEV_CMD_ENUMERATE & 0xFF)) { + pr_err("%s: ENUMERATE response is wrong!\n", + mmc_hostname(host)); + return -EIO; + } + + id_f =3D (uhs2_cmd.uhs2_resp[4] >> 4) & 0xF; + id_l =3D uhs2_cmd.uhs2_resp[4] & 0xF; + *node_id =3D id_f; + return 0; } =20 @@ -84,6 +273,180 @@ static int sd_uhs2_enum(struct mmc_host *host, u32 *no= de_id) */ static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *car= d) { + struct mmc_command cmd =3D {0}; + struct uhs2_command uhs2_cmd =3D {}; + u32 cap; + int err; + + /* + * Use Control Read CCMD to read Generic Capability from Configuration Re= gister. + * - Control Write(R/W=3D1) with 4-Byte payload(PLEN=3D01b). + * - IOADR =3D Generic Capability Register(CFG_BASE + 000h) + */ + uhs2_cmd.header =3D UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uh= s2_config.node_id; + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_GEN_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CONFIG_GEN_CAPS >> 8); + + /* + * There is no payload because per spec, there should be + * no payload field for read CCMD. + * Plen is set in arg. Per spec, plen for read CCMD + * represents the len of read data which is assigned in payload + * of following RES (p136). + */ + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Generic Capability Register: + * bit [7:0] : Reserved + * bit [13:8] : Device-Specific Number of Lanes and Functionality + * bit 8: 2L-HD + * bit 9: 2D-1U FD + * bit 10: 1D-2U FD + * bit 11: 2D-2U FD + * Others: Reserved + * bit [14] : DADR Length + * 0: 4 bytes + * 1: Reserved + * bit [23:16]: Application Type + * bit 16: 0=3DNon-SD memory, 1=3DSD memory + * bit 17: 0=3DNon-SDIO, 1=3DSDIO + * bit 18: 0=3DCard, 1=3DEmbedded + * bit [63:24]: Reserved + */ + cap =3D cmd.resp[0]; + card->uhs2_config.n_lanes =3D + (cap >> UHS2_DEV_CONFIG_N_LANES_POS) & + UHS2_DEV_CONFIG_N_LANES_MASK; + card->uhs2_config.dadr_len =3D + (cap >> UHS2_DEV_CONFIG_DADR_POS) & + UHS2_DEV_CONFIG_DADR_MASK; + card->uhs2_config.app_type =3D + (cap >> UHS2_DEV_CONFIG_APP_POS) & + UHS2_DEV_CONFIG_APP_MASK; + + /* + * Use Control Read CCMD to read PHY Capability from Configuration Regist= er. + * - Control Write(R/W=3D1) with 8-Byte payload(PLEN=3D10b). + * - IOADR =3D PHY Capability Register(CFG_BASE + 002h) + */ + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_PHY_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_PHY_CAPS >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * PHY Capability Register: + * bit [3:0] : PHY Minor Revision + * bit [5:4] : PHY Major Revision + * bit [15] : Support Hibernate Mode + * 0: Not support Hibernate Mode + * 1: Support Hibernate Mode + * bit [31:16]: Reserved + * bit [35:32]: Device-Specific N_LSS_SYN + * bit [39:36]: Device-Specific N_LSS_DIR + * bit [63:40]: Reserved + */ + cap =3D cmd.resp[0]; + card->uhs2_config.phy_minor_rev =3D + cap & UHS2_DEV_CONFIG_PHY_MINOR_MASK; + card->uhs2_config.phy_major_rev =3D + (cap >> UHS2_DEV_CONFIG_PHY_MAJOR_POS) & + UHS2_DEV_CONFIG_PHY_MAJOR_MASK; + card->uhs2_config.can_hibernate =3D + (cap >> UHS2_DEV_CONFIG_CAN_HIBER_POS) & + UHS2_DEV_CONFIG_CAN_HIBER_MASK; + + cap =3D cmd.resp[1]; + card->uhs2_config.n_lss_sync =3D + cap & UHS2_DEV_CONFIG_N_LSS_SYN_MASK; + card->uhs2_config.n_lss_dir =3D + (cap >> UHS2_DEV_CONFIG_N_LSS_DIR_POS) & + UHS2_DEV_CONFIG_N_LSS_DIR_MASK; + if (card->uhs2_config.n_lss_sync =3D=3D 0) + card->uhs2_config.n_lss_sync =3D 16 << 2; + else + card->uhs2_config.n_lss_sync <<=3D 2; + + if (card->uhs2_config.n_lss_dir =3D=3D 0) + card->uhs2_config.n_lss_dir =3D 16 << 3; + else + card->uhs2_config.n_lss_dir <<=3D 3; + + /* + * Use Control Read CCMD to read LINK/TRAN Capability from Configuration = Register. + * - Control Write(R/W=3D1) with 8-Byte payload(PLEN=3D10b). + * - IOADR =3D LINK/TRAN Capability Register(CFG_BASE + 004h) + */ + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_LINK_TRAN_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_LINK_TRAN_CAPS >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * LINK/TRAN Capability Register: + * bit [3:0] : LINK_TRAN Minor Revision + * bit [5:4] : LINK/TRAN Major Revision + * bit [7:6] : Reserved + * bit [15:8] : Device-Specific N_FCU + * bit [18:16]: Device Type + * 001b=3DHost + * 010b=3DDevice + * 011b=3DReserved for CMD issuable Device + * bit [19] : Reserved + * bit [31:20]: Device-Specific MAX_BLKLEN + * bit [39:32]: Device-Specific N_DATA_GAP + * bit [63:40]: Reserved + */ + cap =3D cmd.resp[0]; + card->uhs2_config.link_minor_rev =3D + cap & UHS2_DEV_CONFIG_LT_MINOR_MASK; + card->uhs2_config.link_major_rev =3D + (cap >> UHS2_DEV_CONFIG_LT_MAJOR_POS) & + UHS2_DEV_CONFIG_LT_MAJOR_MASK; + card->uhs2_config.n_fcu =3D + (cap >> UHS2_DEV_CONFIG_N_FCU_POS) & + UHS2_DEV_CONFIG_N_FCU_MASK; + card->uhs2_config.dev_type =3D + (cap >> UHS2_DEV_CONFIG_DEV_TYPE_POS) & + UHS2_DEV_CONFIG_DEV_TYPE_MASK; + card->uhs2_config.maxblk_len =3D + (cap >> UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) & + UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK; + + cap =3D cmd.resp[1]; + card->uhs2_config.n_data_gap =3D + cap & UHS2_DEV_CONFIG_N_DATA_GAP_MASK; + if (card->uhs2_config.n_fcu =3D=3D 0) + card->uhs2_config.n_fcu =3D 256; + return 0; } =20 @@ -98,26 +461,350 @@ static int sd_uhs2_config_read(struct mmc_host *host,= struct mmc_card *card) */ static int sd_uhs2_config_write(struct mmc_host *host, struct mmc_card *ca= rd) { + struct mmc_command cmd =3D {0}; + struct uhs2_command uhs2_cmd =3D {}; + u8 nMinDataGap; + int err; + + /* + * Use Control Write CCMD to set Generic Setting in Configuration Registe= r. + * - Control Write(R/W=3D1) with 8-Byte payload(PLEN=3D10b). + * - IOADR =3D Generic Setting Register(CFG_BASE + 008h) + * - Payload =3D New contents to be written to Generic Setting Register + */ + uhs2_cmd.header =3D UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uh= s2_config.node_id; + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + /* + * Most UHS-II cards only support FD and 2L-HD mode. Other lane numbers + * defined in UHS-II addendem Ver1.01 are optional. + */ + host->uhs2_caps.n_lanes_set =3D UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; + card->uhs2_config.n_lanes_set =3D UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; + + uhs2_cmd.payload[0] =3D card->uhs2_config.n_lanes_set << UHS2_DEV_CONFIG_= N_LANES_POS; + uhs2_cmd.payload[1] =3D 0; + uhs2_cmd.payload[0] =3D cpu_to_be32(uhs2_cmd.payload[0]); + uhs2_cmd.payload[1] =3D cpu_to_be32(uhs2_cmd.payload[1]); + + /* + * There is no payload because per spec, there should be + * no payload field for read CCMD. + * Plen is set in arg. Per spec, plen for read CCMD + * represents the len of read data which is assigned in payload + * of following RES (p136). + */ + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, 0); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Write CCMD to set PHY Setting in Configuration Register. + * - Control Write(R/W=3D1) with 8-Byte payload(PLEN=3D10b). + * - IOADR =3D PHY Setting Register(CFG_BASE + 00Ah) + * - Payload =3D New contents to be written to PHY Setting Register + */ + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_PHY_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_PHY_SET >> 8); + + if (host->uhs2_caps.speed_range =3D=3D UHS2_DEV_CONFIG_PHY_SET_SPEED_B) { + if (card->uhs2_config.n_lanes =3D=3D UHS2_DEV_CONFIG_2L_HD_FD && + host->uhs2_caps.n_lanes =3D=3D UHS2_DEV_CONFIG_2L_HD_FD) { + /* Support HD */ + host->ios.timing =3D MMC_TIMING_UHS2_SPEED_B_HD; + nMinDataGap =3D 1; + } else { + /* Only support 2L-FD so far */ + host->ios.timing =3D MMC_TIMING_UHS2_SPEED_B; + nMinDataGap =3D 3; + } + card->uhs2_config.speed_range_set =3D UHS2_DEV_CONFIG_PHY_SET_SPEED_B; + } else { + if (card->uhs2_config.n_lanes =3D=3D UHS2_DEV_CONFIG_2L_HD_FD && + host->uhs2_caps.n_lanes =3D=3D UHS2_DEV_CONFIG_2L_HD_FD) { + /* Support HD */ + host->ios.timing =3D MMC_TIMING_UHS2_SPEED_A_HD; + nMinDataGap =3D 1; + } else { + /* Only support 2L-FD so far */ + host->ios.timing =3D MMC_TIMING_UHS2_SPEED_A; + nMinDataGap =3D 3; + } + card->uhs2_config.speed_range_set =3D UHS2_DEV_CONFIG_PHY_SET_SPEED_A; + } + + uhs2_cmd.payload[0] =3D + card->uhs2_config.speed_range_set << UHS2_DEV_CONFIG_PHY_SET_SPEED_POS; + + card->uhs2_config.n_lss_sync_set =3D (max(card->uhs2_config.n_lss_sync, + host->uhs2_caps.n_lss_sync) >> 2) & + UHS2_DEV_CONFIG_N_LSS_SYN_MASK; + host->uhs2_caps.n_lss_sync_set =3D card->uhs2_config.n_lss_sync_set; + + card->uhs2_config.n_lss_dir_set =3D (max(card->uhs2_config.n_lss_dir, + host->uhs2_caps.n_lss_dir) >> 3) & + UHS2_DEV_CONFIG_N_LSS_DIR_MASK; + host->uhs2_caps.n_lss_dir_set =3D card->uhs2_config.n_lss_dir_set; + + uhs2_cmd.payload[1] =3D (card->uhs2_config.n_lss_dir_set << UHS2_DEV_CONF= IG_N_LSS_DIR_POS) | + card->uhs2_config.n_lss_sync_set; + uhs2_cmd.payload[0] =3D cpu_to_be32(uhs2_cmd.payload[0]); + uhs2_cmd.payload[1] =3D cpu_to_be32(uhs2_cmd.payload[1]); + + memset(uhs2_cmd.uhs2_resp, 0, sizeof(uhs2_cmd.uhs2_resp)); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, + UHS2_CFG_WRITE_PHY_SET_RESP_LEN); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if ((uhs2_cmd.uhs2_resp[2] & 0x80)) { + pr_err("%s: %s: UHS2 CMD not accepted, resp=3D 0x%x!\n", + mmc_hostname(host), __func__, uhs2_cmd.uhs2_resp[2]); + return -EIO; + } + + /* + * Use Control Write CCMD to set LINK/TRAN Setting in Configuration Regis= ter. + * - Control Write(R/W=3D1) with 8-Byte payload(PLEN=3D10b). + * - IOADR =3D LINK/TRAN Setting Register(CFG_BASE + 00Ch) + * - Payload =3D New contents to be written to LINK/TRAN Setting Register + */ + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_LINK_TRAN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_LINK_TRAN_SET >> 8); + + if (card->uhs2_config.app_type =3D=3D UHS2_DEV_CONFIG_APP_SD_MEM) + card->uhs2_config.maxblk_len_set =3D UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN; + else + card->uhs2_config.maxblk_len_set =3D min(card->uhs2_config.maxblk_len, + host->uhs2_caps.maxblk_len); + host->uhs2_caps.maxblk_len_set =3D card->uhs2_config.maxblk_len_set; + + card->uhs2_config.n_fcu_set =3D min(card->uhs2_config.n_fcu, host->uhs2_c= aps.n_fcu); + host->uhs2_caps.n_fcu_set =3D card->uhs2_config.n_fcu_set; + + card->uhs2_config.n_data_gap_set =3D max(nMinDataGap, card->uhs2_config.n= _data_gap); + host->uhs2_caps.n_data_gap_set =3D card->uhs2_config.n_data_gap_set; + + host->uhs2_caps.max_retry_set =3D 3; + card->uhs2_config.max_retry_set =3D host->uhs2_caps.max_retry_set; + + uhs2_cmd.payload[0] =3D + (card->uhs2_config.maxblk_len_set << UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) | + (card->uhs2_config.max_retry_set << UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_PO= S) | + (card->uhs2_config.n_fcu_set << UHS2_DEV_CONFIG_N_FCU_POS); + uhs2_cmd.payload[1] =3D card->uhs2_config.n_data_gap_set; + uhs2_cmd.payload[0] =3D cpu_to_be32(uhs2_cmd.payload[0]); + uhs2_cmd.payload[1] =3D cpu_to_be32(uhs2_cmd.payload[1]); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, 0); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Write CCMD to set Config Completion(payload bit 63) in Gen= eric Setting + * Register. + * Header: + * - Control Write(R/W=3D1) with 8-Byte payload(PLEN=3D10b). + * - IOADR =3D PGeneric Setting Register(CFG_BASE + 008h) + * Payload: + * - bit [63]: Config Completion + * + * DLSM transits to Active state immediately when Config Completion is se= t to 1. + */ + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + uhs2_cmd.payload[0] =3D 0; + uhs2_cmd.payload[1] =3D UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE; + uhs2_cmd.payload[0] =3D cpu_to_be32(uhs2_cmd.payload[0]); + uhs2_cmd.payload[1] =3D cpu_to_be32(uhs2_cmd.payload[1]); + + memset(uhs2_cmd.uhs2_resp, 0, sizeof(uhs2_cmd.uhs2_resp)); + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_CFG_WRITE_PAYLOAD_LEN, + UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* Set host Config Setting registers */ + err =3D host->ops->uhs2_control(host, UHS2_SET_CONFIG); + if (err) { + pr_err("%s: %s: UHS2 SET_CONFIG fail!\n", mmc_hostname(host), __func__); + return err; + } + + return 0; +} + +static int sd_uhs2_go_dormant(struct mmc_host *host, u32 node_id) +{ + struct mmc_command cmd =3D {0}; + struct uhs2_command uhs2_cmd =3D {}; + int err; + + /* Disable Normal INT */ + err =3D host->ops->uhs2_control(host, UHS2_DISABLE_INT); + if (err) { + pr_err("%s: %s: UHS2 DISABLE_INT fail!\n", + mmc_hostname(host), __func__); + return err; + } + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-17 to see GO_DORMANT_ST= ATE CCMD format. + * Header: + * - Control Write(R/W=3D1) with 4-Byte payload(PLEN=3D01b). + * - IOADR =3D CMD_BASE + 001h + * Payload: + * - bit [7]: HBR(Entry to Hibernate Mode) + * 1: Host intends to enter Hibernate mode during Dormant= state. + * The default setting is 0 because hibernate is currentl= y not supported. + */ + uhs2_cmd.header =3D UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; + uhs2_cmd.arg =3D ((UHS2_DEV_CMD_GO_DORMANT_STATE & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_GO_DORMANT_STATE >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, UHS2_GO_DORMANT_PAYLOAD_LEN, 0); + + err =3D mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* Check Dormant State in Present */ + err =3D host->ops->uhs2_control(host, UHS2_CHECK_DORMANT); + if (err) + return err; + + /* Disable UHS2 card clock */ + err =3D host->ops->uhs2_control(host, UHS2_DISABLE_CLK); + if (err) + return err; + + /* Restore sd clock */ + mmc_delay(5); + err =3D host->ops->uhs2_control(host, UHS2_ENABLE_CLK); + if (err) + return err; + + /* Enable Normal INT */ + err =3D host->ops->uhs2_control(host, UHS2_ENABLE_INT); + if (err) + return err; + + /* Detect UHS2 */ + err =3D host->ops->uhs2_control(host, UHS2_PHY_INIT); + if (err) + return err; + return 0; } =20 -/* - * Initialize the UHS-II card through the SD-TRAN transport layer. This en= ables - * commands/requests to be backwards compatible through the legacy SD prot= ocol. - * UHS-II cards has a specific power limit specified for VDD1/VDD2, that s= hould - * be set through a legacy CMD6. Note that, the power limit that becomes s= et, - * survives a soft reset through the GO_DORMANT_STATE command. - */ -static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *car= d) +static int sd_uhs2_wait_active_state_cb(void *cb_data, bool *busy) +{ + struct sd_uhs2_wait_active_state_data *data =3D cb_data; + struct mmc_host *host =3D data->host; + struct mmc_command *cmd =3D data->cmd; + int err; + + err =3D mmc_wait_for_cmd(host, cmd, 0); + if (err) + return err; + + if (cmd->resp[1] & UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE) + *busy =3D false; + else + *busy =3D true; + + return 0; +} + +static int sd_uhs2_go_dormant_state(struct mmc_host *host, u32 node_id) { + struct mmc_command cmd =3D {0}; + struct uhs2_command uhs2_cmd =3D {}; + int err; + struct sd_uhs2_wait_active_state_data cb_data =3D { + .host =3D host, + .cmd =3D &cmd + }; + + err =3D sd_uhs2_go_dormant(host, node_id); + if (err) { + pr_err("%s: %s: UHS2 GO_DORMANT_STATE fail, err=3D 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Read CCMD to check Config Completion(bit 63) in Generic Se= tting Register. + * - Control Read(R/W=3D0) with 8-Byte payload(PLEN=3D10b). + * - IOADR =3D Generic Setting Register(CFG_BASE + 008h) + * + * When UHS-II card been switched to new speed mode, it will set Config C= ompletion to 1. + */ + uhs2_cmd.header =3D UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; + uhs2_cmd.arg =3D ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, 0, 0); + err =3D __mmc_poll_for_busy(host, UHS2_WAIT_CFG_COMPLETE_PERIOD_US, + UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS, + &sd_uhs2_wait_active_state_cb, &cb_data); + if (err) { + pr_err("%s: %s: Not switch to Active in 100 ms\n", mmc_hostname(host), _= _func__); + return err; + } + return 0; } =20 +static void sd_uhs2_remove(struct mmc_host *host) +{ + mmc_remove_card(host->card); + host->card =3D NULL; +} + /* * Allocate the data structure for the mmc_card and run the UHS-II specific * initialization sequence. */ -static int sd_uhs2_init_card(struct mmc_host *host) +static int sd_uhs2_init_card(struct mmc_host *host, struct mmc_card *oldca= rd) { struct mmc_card *card; u32 node_id =3D 0; @@ -131,33 +818,211 @@ static int sd_uhs2_init_card(struct mmc_host *host) if (err) return err; =20 - card =3D mmc_alloc_card(host, &sd_type); - if (IS_ERR(card)) - return PTR_ERR(card); + if (oldcard) { + card =3D oldcard; + } else { + card =3D mmc_alloc_card(host, &sd_type); + if (IS_ERR(card)) + return PTR_ERR(card); + } =20 card->uhs2_config.node_id =3D node_id; card->type =3D MMC_TYPE_SD; =20 err =3D sd_uhs2_config_read(host, card); if (err) - goto err; + return err; =20 err =3D sd_uhs2_config_write(host, card); if (err) - goto err; + return err; =20 host->card =3D card; + /* If change speed to Range B, need to GO_DORMANT_STATE */ + if (host->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_B || + host->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_B_HD) { + err =3D sd_uhs2_go_dormant_state(host, node_id); + if (err) + return err; + } + + host->uhs2_sd_tran =3D true; + + return 0; +} + +/* + * Initialize the UHS-II card through the SD-TRAN transport layer. This en= ables + * commands/requests to be backwards compatible through the legacy SD prot= ocol. + * UHS-II cards has a specific power limit specified for VDD1/VDD2, that s= hould + * be set through a legacy CMD6. Note that, the power limit that becomes s= et, + * survives a soft reset through the GO_DORMANT_STATE command. + */ +static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *car= d, + struct mmc_card *oldcard) +{ + int err; + u32 cid[4]; + u32 ocr; + u32 rocr; + u8 *status; + int ro; + + /* Send CMD0 to reset SD card */ + err =3D __mmc_go_idle(host); + if (err) + return err; + + mmc_delay(1); + + /* Send CMD8 to communicate SD interface operation condition */ + err =3D mmc_send_if_cond(host, host->ocr_avail); + if (err) { + dev_warn(mmc_dev(host), "CMD8 error\n"); + goto err; + } + + /* + * Probe SD card working voltage. + */ + err =3D mmc_send_app_op_cond(host, 0, &ocr); + if (err) + goto err; + + card->ocr =3D ocr; + + /* + * Some SD cards claims an out of spec VDD voltage range. Let's treat + * these bits as being in-valid and especially also bit7. + */ + ocr &=3D ~0x7FFF; + rocr =3D mmc_select_voltage(host, ocr); + /* + * Some cards have zero value of rocr in UHS-II mode. Assign host's + * ocr value to rocr. + */ + if (!rocr) + rocr =3D host->ocr_avail; + + rocr |=3D (SD_OCR_CCS | SD_OCR_XPC); + + /* Wait SD power on ready */ + ocr =3D rocr; + + err =3D mmc_send_app_op_cond(host, ocr, &rocr); + if (err) + goto err; + + err =3D mmc_send_cid(host, cid); + if (err) + goto err; + + if (oldcard) { + if (memcmp(cid, oldcard->raw_cid, sizeof(cid)) !=3D 0) { + pr_debug("%s: Perhaps the card was replaced\n", + mmc_hostname(host)); + return -ENOENT; + } + + card =3D oldcard; + } else { + memcpy(card->raw_cid, cid, sizeof(card->raw_cid)); + mmc_decode_cid(card); + } + + /* + * For native busses: get card RCA and quit open drain mode. + */ + err =3D mmc_send_relative_addr(host, &card->rca); + if (err) + goto err; + + err =3D mmc_sd_get_csd(card, false); + if (err) + goto err; + + /* + * Select card, as all following commands rely on that. + */ + err =3D mmc_select_card(card); + if (err) + goto err; + + /* + * Fetch SCR from card. + */ + err =3D mmc_app_send_scr(card); + if (err) + goto err; + + err =3D mmc_decode_scr(card); + if (err) + goto err; + + /* + * Switch to high power consumption mode. + * Even switch failed, sd card can still work at lower power consumption = mode, but + * performance will be lower than high power consumption mode. + */ + status =3D kmalloc(64, GFP_KERNEL); + if (!status) + return -ENOMEM; + + if (!(card->csd.cmdclass & CCC_SWITCH)) { + pr_warn("%s: card lacks mandatory switch function, performance might suf= fer\n", + mmc_hostname(card->host)); + } else { + /* send CMD6 to set Maximum Power Consumption to get better performance = */ + err =3D mmc_sd_switch(card, 0, 3, SD4_SET_POWER_LIMIT_1_80W, status); + if (!err) + err =3D mmc_sd_switch(card, 1, 3, SD4_SET_POWER_LIMIT_1_80W, status); + + err =3D 0; + } + + /* + * Check if read-only switch is active. + */ + ro =3D mmc_sd_get_ro(host); + if (ro < 0) { + pr_warn("%s: host does not support read-only switch, assuming write-enab= le\n", + mmc_hostname(host)); + } else if (ro > 0) { + mmc_card_set_readonly(card); + } + + /* + * NOTE: + * Should we read Externsion Register to check power notification feature= here? + */ + + kfree(status); + return 0; =20 err: - mmc_remove_card(card); return err; } =20 -static void sd_uhs2_remove(struct mmc_host *host) +static int sd_uhs2_reinit(struct mmc_host *host) { - mmc_remove_card(host->card); - host->card =3D NULL; + struct mmc_card *card =3D host->card; + int err; + + sd_uhs2_power_up(host); + err =3D sd_uhs2_phy_init(host); + if (err) + return err; + + err =3D sd_uhs2_init_card(host, card); + if (err) + return err; + + err =3D sd_uhs2_legacy_init(host, card, card); + if (err) + return err; + + return err; } =20 static int sd_uhs2_alive(struct mmc_host *host) @@ -183,34 +1048,188 @@ static void sd_uhs2_detect(struct mmc_host *host) } } =20 +static int _sd_uhs2_suspend(struct mmc_host *host) +{ + struct mmc_card *card =3D host->card; + int err =3D 0; + + mmc_claim_host(host); + + if (mmc_card_suspended(card)) + goto out; + + if (sd_can_poweroff_notify(card)) + err =3D sd_poweroff_notify(card); + + if (!err) { + sd_uhs2_power_off(host); + mmc_card_set_suspended(card); + } + +out: + mmc_release_host(host); + return err; +} + +/* + * Callback for suspend + */ static int sd_uhs2_suspend(struct mmc_host *host) { - return 0; + int err; + + err =3D _sd_uhs2_suspend(host); + if (!err) { + pm_runtime_disable(&host->card->dev); + pm_runtime_set_suspended(&host->card->dev); + } + + return err; +} + +/* + * This function tries to determine if the same card is still present + * and, if so, restore all state to it. + */ +static int _mmc_sd_uhs2_resume(struct mmc_host *host) +{ + int err =3D 0; + + mmc_claim_host(host); + + if (!mmc_card_suspended(host->card)) + goto out; + + /* Power up UHS2 SD card and re-initialize it. */ + err =3D sd_uhs2_reinit(host); + mmc_card_clr_suspended(host->card); + +out: + mmc_release_host(host); + return err; } =20 +/* + * Callback for resume + */ static int sd_uhs2_resume(struct mmc_host *host) { + pm_runtime_enable(&host->card->dev); return 0; } =20 +/* + * Callback for runtime_suspend. + */ static int sd_uhs2_runtime_suspend(struct mmc_host *host) { - return 0; + int err; + + if (!(host->caps & MMC_CAP_AGGRESSIVE_PM)) + return 0; + + err =3D _sd_uhs2_suspend(host); + if (err) + pr_err("%s: error %d doing aggressive suspend\n", mmc_hostname(host), er= r); + + return err; } =20 static int sd_uhs2_runtime_resume(struct mmc_host *host) { - return 0; + int err; + + err =3D _mmc_sd_uhs2_resume(host); + if (err && err !=3D -ENOMEDIUM) + pr_err("%s: error %d doing runtime resume\n", mmc_hostname(host), err); + + return err; } =20 -static int sd_uhs2_shutdown(struct mmc_host *host) +static int sd_uhs2_hw_reset(struct mmc_host *host) { - return 0; + int err; + + sd_uhs2_power_off(host); + /* Wait at least 1 ms according to SD spec */ + mmc_delay(1); + sd_uhs2_power_up(host); + + err =3D sd_uhs2_reinit(host); + + return err; } =20 -static int sd_uhs2_hw_reset(struct mmc_host *host) +/* + * mmc_uhs2_prepare_cmd - prepare for SD command packet + * @host: MMC host + * @mrq: MMC request + * + * Initialize and fill in a header and a payload of SD command packet. + * The caller should allocate uhs2_command in host->cmd->uhs2_cmd in + * advance. + * + * Return: 0 on success, non-zero error on failure + */ +void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq) { - return 0; + struct mmc_command *cmd; + struct uhs2_command *uhs2_cmd; + u8 plen; + + cmd =3D mrq->cmd; + cmd->uhs2_cmd =3D &mrq->uhs2_cmd; + uhs2_cmd =3D cmd->uhs2_cmd; + uhs2_cmd->header =3D host->card->uhs2_config.node_id; + if ((cmd->flags & MMC_CMD_MASK) =3D=3D MMC_CMD_ADTC) + uhs2_cmd->header |=3D UHS2_PACKET_TYPE_DCMD; + else + uhs2_cmd->header |=3D UHS2_PACKET_TYPE_CCMD; + + uhs2_cmd->arg =3D cmd->opcode << UHS2_SD_CMD_INDEX_POS; + if (host->uhs2_app_cmd) { + uhs2_cmd->arg |=3D UHS2_SD_CMD_APP; + host->uhs2_app_cmd =3D false; + } + + /* + * UHS-II Addendum 7.2.1.2 + * Host may set DM to 1 for DCMD which supports multi-block read/write re= gardless of + * data transfer length (e.g., CMD18, CMD25). Otherwise, it shall not set= DM to 1. + * (e.g., CMD6, CMD17, CMD24). These rules are also applied to other mult= i-block read/write + * commands defined in other Part of SD specifications (for example, Host= may set DM to 1 + * for ACMD18 or ACMD25). + */ + if (mmc_op_multi(cmd->opcode)) + cmd->uhs2_cmd->tmode_half_duplex =3D mmc_card_uhs2_hd_mode(host); + else + cmd->uhs2_cmd->tmode_half_duplex =3D 0; + + uhs2_cmd =3D cmd->uhs2_cmd; + plen =3D 2; /* at the maximum */ + + if ((cmd->flags & MMC_CMD_MASK) =3D=3D MMC_CMD_ADTC && + cmd->uhs2_cmd->tmode_half_duplex) { + if (mmc_card_uhs2_hd_mode(host)) + uhs2_cmd->arg |=3D UHS2_DCMD_2L_HD_MODE; + + uhs2_cmd->arg |=3D UHS2_DCMD_LM_TLEN_EXIST; + + if (cmd->data->blocks =3D=3D 1 && + cmd->data->blksz !=3D 512 && + cmd->opcode !=3D MMC_READ_SINGLE_BLOCK && + cmd->opcode !=3D MMC_WRITE_BLOCK) { + uhs2_cmd->arg |=3D UHS2_DCMD_TLUM_BYTE_MODE; + uhs2_cmd->payload[1] =3D cpu_to_be32(cmd->data->blksz); + } else { + uhs2_cmd->payload[1] =3D cpu_to_be32(cmd->data->blocks); + } + } else { + plen =3D 1; + } + + uhs2_cmd->payload[0] =3D cpu_to_be32(cmd->arg); + sd_uhs2_cmd_assemble(cmd, uhs2_cmd, plen, 0); } =20 static const struct mmc_bus_ops sd_uhs2_ops =3D { @@ -221,7 +1240,7 @@ static const struct mmc_bus_ops sd_uhs2_ops =3D { .resume =3D sd_uhs2_resume, .runtime_suspend =3D sd_uhs2_runtime_suspend, .runtime_resume =3D sd_uhs2_runtime_resume, - .shutdown =3D sd_uhs2_shutdown, + .shutdown =3D sd_uhs2_suspend, .hw_reset =3D sd_uhs2_hw_reset, }; =20 @@ -237,11 +1256,11 @@ static int sd_uhs2_attach(struct mmc_host *host) if (err) goto err; =20 - err =3D sd_uhs2_init_card(host); + err =3D sd_uhs2_init_card(host, NULL); if (err) goto err; =20 - err =3D sd_uhs2_legacy_init(host, host->card); + err =3D sd_uhs2_legacy_init(host, host->card, NULL); if (err) goto err; =20 @@ -254,21 +1273,31 @@ static int sd_uhs2_attach(struct mmc_host *host) goto remove_card; =20 mmc_claim_host(host); + return 0; =20 remove_card: - mmc_remove_card(host->card); - host->card =3D NULL; + sd_uhs2_remove(host); mmc_claim_host(host); - mmc_detach_bus(host); + err: + mmc_detach_bus(host); sd_uhs2_power_off(host); return err; } =20 +/** + * mmc_attach_sd_uhs2 - select UHS2 interface + * @host: MMC host + * + * Try to select UHS2 interface and initialize the bus for a given + * frequency, @freq. + * + * Return: 0 on success, non-zero error on failure + */ int mmc_attach_sd_uhs2(struct mmc_host *host) { - int i, err =3D 0; + int i, err; =20 if (!(host->caps2 & MMC_CAP2_SD_UHS2)) return -EOPNOTSUPP; diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index a890a71288ef..56972bd78462 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -11,6 +11,20 @@ struct mmc_data; struct mmc_request; =20 +#define UHS2_MAX_PAYLOAD_LEN 2 +#define UHS2_MAX_RESP_LEN 20 + +struct uhs2_command { + u16 header; + u16 arg; + __be32 payload[UHS2_MAX_PAYLOAD_LEN]; + u8 payload_len; + u8 packet_len; + u8 tmode_half_duplex; + u8 uhs2_resp[UHS2_MAX_RESP_LEN]; /* UHS2 native cmd resp */ + u8 uhs2_resp_len; /* UHS2 native cmd resp len */ +}; + struct mmc_command { u32 opcode; u32 arg; @@ -97,6 +111,8 @@ struct mmc_command { struct mmc_data *data; /* data segment associated with cmd */ struct mmc_request *mrq; /* associated request */ =20 + struct uhs2_command *uhs2_cmd; /* UHS2 command */ + /* for SDUC */ bool has_ext_addr; u8 ext_addr; @@ -158,6 +174,7 @@ struct mmc_request { const struct bio_crypt_ctx *crypto_ctx; int crypto_key_slot; #endif + struct uhs2_command uhs2_cmd; }; =20 struct mmc_card; diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 0980d06ed419..b4c00dbcaf0b 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -127,6 +127,13 @@ struct sd_uhs2_caps { }; =20 enum sd_uhs2_operation { + UHS2_PHY_INIT =3D 0, + UHS2_SET_CONFIG, + UHS2_ENABLE_INT, + UHS2_DISABLE_INT, + UHS2_ENABLE_CLK, + UHS2_DISABLE_CLK, + UHS2_CHECK_DORMANT, UHS2_SET_IOS, }; =20 @@ -453,6 +460,8 @@ struct mmc_host { #endif #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT en= try at a non-standard location */ =20 + bool uhs2_sd_tran; + bool uhs2_app_cmd; /* Host UHS-II APP Command */ struct sd_uhs2_caps uhs2_caps; /* Host UHS-II capabilities */ =20 int fixed_drv_type; /* fixed driver type for non-removable media */ @@ -714,6 +723,12 @@ static inline void mmc_debugfs_err_stats_inc(struct mm= c_host *host, host->err_stats[stat] +=3D 1; } =20 +static inline int mmc_card_uhs2_hd_mode(struct mmc_host *host) +{ + return host->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_A_HD || + host->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_B_HD; +} + int mmc_sd_switch(struct mmc_card *card, bool mode, int group, u8 value, u8 *resp); int mmc_send_status(struct mmc_card *card, u32 *status); --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 911DA2022C3; Fri, 18 Oct 2024 10:53:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248834; cv=none; b=bnnZu/2Y/6oKQ8bTG8gV6FNWzpQGfwIK7XXkel6gWH/BstIN5WbSVFlZqAtKN58xXqd/0pkAwp5whCkZv25qSX5Rh8CYtX+G6Xs38bACXFeRzKq2xvNAM12oa/u2pocz8Eel/Cq+kjG9nF8BGfb6rbE0W1RMWIZST6XCpaW2sHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248834; c=relaxed/simple; bh=+sXmC7kyTGMKohOvh+2960PDmDNpZmnGORRSwgB2iKg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Pyl0qRszm8AjsEnAmWmlQXzs00FoBGl96EnYMy7d5a1YHAjlrpkkf8dsTHS29GS17V3ymeKv9d8agAOw0hFpdL+Z40sxwZ6RphvxDzTsXsePwaAI8i0/dLKGrqUXH5pTSURp5vhq1ZlsdsguZEPgcNDHrNuNTMygb/DEFVQEbpc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gPveVIoe; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gPveVIoe" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-20c70abba48so16918315ad.0; Fri, 18 Oct 2024 03:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248832; x=1729853632; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2BiV+abCFUR4wsdfncjsvsUIyTpX7pruMJBcr6f4UWM=; b=gPveVIoeKmxBKrhASH69Y/Y79rZ9Iq+4fxYPp2U5mLmpkCKZ1VpUuefQSvxFZgkuwN c/3NO2HTswss6Soo6c0el6uSwfGe2ORwMbKjvXR9trrixlHWxy9HiZkAZAKxT1OrxX53 pudHSwPjpMohTffW3wSNUqUgdNhdyFvhatEnMlsFzRIMnGIPeM8sxJl9TCOQSGdNQD+x BzcFFr3wueM2fXuWp3rIB9mWaM3YeqBHtzxeK8kURkomsxiqz4pFDxqH/rPri02BvvSn uGD3//Tg80BHTLVYWbZvZ595ciVWfljDSQZQ0vL2ZHs/1MQd7dsjOvgaqt4F0XmJBLZ5 SxNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248832; x=1729853632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2BiV+abCFUR4wsdfncjsvsUIyTpX7pruMJBcr6f4UWM=; b=Jsck7kPaM2X8lNRaM54eBkL91o125kyOMIx0Mk4mZsdUdk+mD8vJEO4bMJwbHwCLrN Gn40cNnKd9hvzuwsXlfMaxA0jnufKvSZYM8JxfnL07IHWWo2NsITljGhH3GvvdpDkgFT iorgpbbZknqHT2AnEu8HDC30FD+P3CTVGiMjVWvLQXLWvx1zmpQ/sF0UNvk12w6XiRq9 tRegcWzX6RiKJXhZ7m8ne27MRGHJ+s7LJHWG8t8CRHIuAhILMk2baZyhMlNuue5KpTaJ UHLhP/lMC5z30GLEj1V657qGTi/3JU4KpskecOS7s6iHGPTFVfkBMQ8x41alaVOnacvV iyVw== X-Forwarded-Encrypted: i=1; AJvYcCUYxGWSIJ6gDbOGFB2KOEX/SzjLN2O+Y4VUMxWg0jlJBCe3FnFB3US22+7vxuir+L0tTm+rITyC5aygMYw=@vger.kernel.org X-Gm-Message-State: AOJu0Yw27b01VBYwU293ko9K6ifxA8U2ad5teJybmXfN7z4SWkM08S5L 3Pr6u9aM2OKkFdIUi4gRXYmTqhTuGMesYm+URGUNtOvSFVuBHxVu X-Google-Smtp-Source: AGHT+IEP+zI+sq1RhoN98JcBwM8bWRrHMOamQZw8CYiKMfYZ83iinpN58nU0P4+tZLaU8kECSSskaw== X-Received: by 2002:a17:903:2303:b0:20c:a175:1942 with SMTP id d9443c01a7336-20e5a89e79emr24913795ad.24.1729248831656; Fri, 18 Oct 2024 03:53:51 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.53.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:53:51 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 02/16] mmc: sdhci: add UHS-II related definitions in headers Date: Fri, 18 Oct 2024 18:53:19 +0800 Message-Id: <20241018105333.4569-3-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih Add UHS-II related definitions in sdhci.h and sdhci-uhs2.h. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V9: - Modify the commit message. Updates in V8: - Use tabs instead of spaces. Updates in V7: - Reorder values and positions of definitions. Updates in V6: - Rename definitions. - Use BIT() GENMASK() instead of bitwise operations. --- drivers/mmc/host/sdhci-uhs2.h | 177 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 54 ++++++++++- 2 files changed, 230 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-uhs2.h diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h new file mode 100644 index 000000000000..e993f41ffb7f --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * linux/drivers/mmc/host/sdhci-uhs2.h - Secure Digital Host Controller I= nterface driver + * + * Header file for Host Controller UHS2 related registers. + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + */ +#ifndef __SDHCI_UHS2_H +#define __SDHCI_UHS2_H + +#include + +/* SDHCI Category C registers : UHS2 usage */ + +#define SDHCI_UHS2_CM_TRAN_RESP 0x10 +#define SDHCI_UHS2_SD_TRAN_RESP 0x18 +#define SDHCI_UHS2_SD_TRAN_RESP_1 0x1C + +/* SDHCI Category B registers : UHS2 only */ + +#define SDHCI_UHS2_BLOCK_SIZE 0x80 +#define SDHCI_UHS2_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blks= z) & 0xFFF)) + +#define SDHCI_UHS2_BLOCK_COUNT 0x84 + +#define SDHCI_UHS2_CMD_PACKET 0x88 +#define SDHCI_UHS2_CMD_PACK_MAX_LEN 20 + +#define SDHCI_UHS2_TRANS_MODE 0x9C +#define SDHCI_UHS2_TRNS_DMA BIT(0) +#define SDHCI_UHS2_TRNS_BLK_CNT_EN BIT(1) +#define SDHCI_UHS2_TRNS_DATA_TRNS_WRT BIT(4) +#define SDHCI_UHS2_TRNS_BLK_BYTE_MODE BIT(5) +#define SDHCI_UHS2_TRNS_RES_R5 BIT(6) +#define SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN BIT(7) +#define SDHCI_UHS2_TRNS_RES_INT_DIS BIT(8) +#define SDHCI_UHS2_TRNS_WAIT_EBSY BIT(14) +#define SDHCI_UHS2_TRNS_2L_HD BIT(15) + +#define SDHCI_UHS2_CMD 0x9E +#define SDHCI_UHS2_CMD_SUB_CMD BIT(2) +#define SDHCI_UHS2_CMD_DATA BIT(5) +#define SDHCI_UHS2_CMD_TRNS_ABORT BIT(6) +#define SDHCI_UHS2_CMD_CMD12 BIT(7) +#define SDHCI_UHS2_CMD_DORMANT GENMASK(7, 6) +#define SDHCI_UHS2_CMD_PACK_LEN_MASK GENMASK(12, 8) + +#define SDHCI_UHS2_RESPONSE 0xA0 +#define SDHCI_UHS2_RESPONSE_MAX_LEN 20 + +#define SDHCI_UHS2_MSG_SELECT 0xB4 +#define SDHCI_UHS2_MSG_SELECT_CURR 0x0 +#define SDHCI_UHS2_MSG_SELECT_ONE 0x1 +#define SDHCI_UHS2_MSG_SELECT_TWO 0x2 +#define SDHCI_UHS2_MSG_SELECT_THREE 0x3 + +#define SDHCI_UHS2_MSG 0xB8 + +#define SDHCI_UHS2_DEV_INT_STATUS 0xBC + +#define SDHCI_UHS2_DEV_SELECT 0xBE +#define SDHCI_UHS2_DEV_SEL_MASK GENMASK(3, 0) +#define SDHCI_UHS2_DEV_SEL_INT_MSG_EN BIT(7) + +#define SDHCI_UHS2_DEV_INT_CODE 0xBF + +#define SDHCI_UHS2_SW_RESET 0xC0 +#define SDHCI_UHS2_SW_RESET_FULL BIT(0) +#define SDHCI_UHS2_SW_RESET_SD BIT(1) + +#define SDHCI_UHS2_TIMER_CTRL 0xC2 +#define SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK GENMASK(7, 4) + +#define SDHCI_UHS2_INT_STATUS 0xC4 +#define SDHCI_UHS2_INT_STATUS_ENABLE 0xC8 +#define SDHCI_UHS2_INT_SIGNAL_ENABLE 0xCC +#define SDHCI_UHS2_INT_HEADER_ERR BIT(0) +#define SDHCI_UHS2_INT_RES_ERR BIT(1) +#define SDHCI_UHS2_INT_RETRY_EXP BIT(2) +#define SDHCI_UHS2_INT_CRC BIT(3) +#define SDHCI_UHS2_INT_FRAME_ERR BIT(4) +#define SDHCI_UHS2_INT_TID_ERR BIT(5) +#define SDHCI_UHS2_INT_UNRECOVER BIT(7) +#define SDHCI_UHS2_INT_EBUSY_ERR BIT(8) +#define SDHCI_UHS2_INT_ADMA_ERROR BIT(15) +#define SDHCI_UHS2_INT_CMD_TIMEOUT BIT(16) +#define SDHCI_UHS2_INT_DEADLOCK_TIMEOUT BIT(17) +#define SDHCI_UHS2_INT_VENDOR_ERR BIT(27) +#define SDHCI_UHS2_INT_ERROR_MASK ( \ + SDHCI_UHS2_INT_HEADER_ERR | \ + SDHCI_UHS2_INT_RES_ERR | \ + SDHCI_UHS2_INT_RETRY_EXP | \ + SDHCI_UHS2_INT_CRC | \ + SDHCI_UHS2_INT_FRAME_ERR | \ + SDHCI_UHS2_INT_TID_ERR | \ + SDHCI_UHS2_INT_UNRECOVER | \ + SDHCI_UHS2_INT_EBUSY_ERR | \ + SDHCI_UHS2_INT_ADMA_ERROR | \ + SDHCI_UHS2_INT_CMD_TIMEOUT | \ + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) +#define SDHCI_UHS2_INT_CMD_ERR_MASK ( \ + SDHCI_UHS2_INT_HEADER_ERR | \ + SDHCI_UHS2_INT_RES_ERR | \ + SDHCI_UHS2_INT_FRAME_ERR | \ + SDHCI_UHS2_INT_TID_ERR | \ + SDHCI_UHS2_INT_CMD_TIMEOUT) +/* CRC Error occurs during a packet receiving */ +#define SDHCI_UHS2_INT_DATA_ERR_MASK ( \ + SDHCI_UHS2_INT_RETRY_EXP | \ + SDHCI_UHS2_INT_CRC | \ + SDHCI_UHS2_INT_UNRECOVER | \ + SDHCI_UHS2_INT_EBUSY_ERR | \ + SDHCI_UHS2_INT_ADMA_ERROR | \ + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) + +#define SDHCI_UHS2_SETTINGS_PTR 0xE0 +#define SDHCI_UHS2_GEN_SETTINGS_POWER_LOW BIT(0) +#define SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK GENMASK(11, 8) +#define SDHCI_UHS2_FD_OR_2L_HD 0x0 /* 2 lanes */ +#define SDHCI_UHS2_2D1U_FD 0x2 /* 3 lanes, 2 down, 1 up, full duplex */ +#define SDHCI_UHS2_1D2U_FD 0x3 /* 3 lanes, 1 down, 2 up, full duplex */ +#define SDHCI_UHS2_2D2U_FD 0x4 /* 4 lanes, 2 down, 2 up, full duplex */ + +#define SDHCI_UHS2_PHY_SET_SPEED_B BIT(6) +#define SDHCI_UHS2_PHY_HIBERNATE_EN BIT(12) +#define SDHCI_UHS2_PHY_N_LSS_SYN_MASK GENMASK(19, 16) +#define SDHCI_UHS2_PHY_N_LSS_DIR_MASK GENMASK(23, 20) + +#define SDHCI_UHS2_TRAN_N_FCU_MASK GENMASK(15, 8) +#define SDHCI_UHS2_TRAN_RETRY_CNT_MASK GENMASK(17, 16) +#define SDHCI_UHS2_TRAN_1_N_DAT_GAP_MASK GENMASK(7, 0) + +#define SDHCI_UHS2_CAPS_PTR 0xE2 +#define SDHCI_UHS2_CAPS_OFFSET 0 +#define SDHCI_UHS2_CAPS_DAP_MASK GENMASK(3, 0) +#define SDHCI_UHS2_CAPS_GAP_MASK GENMASK(7, 4) +#define SDHCI_UHS2_CAPS_GAP(gap) ((gap) * 360) +#define SDHCI_UHS2_CAPS_LANE_MASK GENMASK(13, 8) +#define SDHCI_UHS2_CAPS_2L_HD_FD 1 +#define SDHCI_UHS2_CAPS_2D1U_FD 2 +#define SDHCI_UHS2_CAPS_1D2U_FD 4 +#define SDHCI_UHS2_CAPS_2D2U_FD 8 +#define SDHCI_UHS2_CAPS_ADDR_64 BIT(14) +#define SDHCI_UHS2_CAPS_BOOT BIT(15) +#define SDHCI_UHS2_CAPS_DEV_TYPE_MASK GENMASK(17, 16) +#define SDHCI_UHS2_CAPS_DEV_TYPE_RMV 0 +#define SDHCI_UHS2_CAPS_DEV_TYPE_EMB 1 +#define SDHCI_UHS2_CAPS_DEV_TYPE_EMB_RMV 2 +#define SDHCI_UHS2_CAPS_NUM_DEV_MASK GENMASK(21, 18) +#define SDHCI_UHS2_CAPS_BUS_TOPO_MASK GENMASK(23, 22) +#define SDHCI_UHS2_CAPS_BUS_TOPO_SHIFT 22 +#define SDHCI_UHS2_CAPS_BUS_TOPO_P2P 0 +#define SDHCI_UHS2_CAPS_BUS_TOPO_RING 1 +#define SDHCI_UHS2_CAPS_BUS_TOPO_HUB 2 +#define SDHCI_UHS2_CAPS_BUS_TOPO_HUB_RING 3 + +#define SDHCI_UHS2_CAPS_PHY_OFFSET 4 +#define SDHCI_UHS2_CAPS_PHY_REV_MASK GENMASK(5, 0) +#define SDHCI_UHS2_CAPS_PHY_RANGE_MASK GENMASK(7, 6) +#define SDHCI_UHS2_CAPS_PHY_RANGE_A 0 +#define SDHCI_UHS2_CAPS_PHY_RANGE_B 1 +#define SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK GENMASK(19, 16) +#define SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK GENMASK(23, 20) +#define SDHCI_UHS2_CAPS_TRAN_OFFSET 8 +#define SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK GENMASK(5, 0) +#define SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK GENMASK(15, 8) +#define SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK GENMASK(18, 16) +#define SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK GENMASK(31, 20) + +#define SDHCI_UHS2_CAPS_TRAN_1_OFFSET 12 +#define SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK GENMASK(7, 0) + +#define SDHCI_UHS2_EMBED_CTRL_PTR 0xE6 +#define SDHCI_UHS2_VENDOR_PTR 0xE8 + +#endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f531b617f28d..e1013925e91e 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -43,8 +43,23 @@ #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 =20 +/* + * Defined in Host Version 4.0. + */ +#define SDHCI_TRNS_RES_TYPE 0x40 +#define SDHCI_TRNS_RES_ERR_CHECK 0x80 +#define SDHCI_TRNS_RES_INT_DIS 0x0100 + #define SDHCI_COMMAND 0x0E #define SDHCI_CMD_RESP_MASK 0x03 + +/* + * Host Version 4.10 adds this bit to distinguish a main command or + * sub command. + * For example with SDIO, CMD52 (sub command) issued during CMD53 (main co= mmand). + */ +#define SDHCI_CMD_SUB_CMD 0x04 + #define SDHCI_CMD_CRC 0x08 #define SDHCI_CMD_INDEX 0x10 #define SDHCI_CMD_DATA 0x20 @@ -65,6 +80,9 @@ #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT 0x00000001 #define SDHCI_DATA_INHIBIT 0x00000002 + +#define SDHCI_DAT_4_TO_7_LVL_MASK 0x000000F0 + #define SDHCI_DOING_WRITE 0x00000100 #define SDHCI_DOING_READ 0x00000200 #define SDHCI_SPACE_AVAILABLE 0x00000400 @@ -80,6 +98,15 @@ #define SDHCI_DATA_0_LVL_MASK 0x00100000 #define SDHCI_CMD_LVL 0x01000000 =20 +/* Host Version 4.10 */ + +#define SDHCI_HOST_REGULATOR_STABLE 0x02000000 +#define SDHCI_CMD_NOT_ISSUED_ERR 0x08000000 +#define SDHCI_SUB_CMD_STATUS 0x10000000 +#define SDHCI_UHS2_IN_DORMANT_STATE 0x20000000 +#define SDHCI_UHS2_LANE_SYNC 0x40000000 +#define SDHCI_UHS2_IF_DETECT 0x80000000 + #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED 0x01 #define SDHCI_CTRL_4BITBUS 0x02 @@ -117,7 +144,7 @@ #define SDHCI_CLOCK_CONTROL 0x2C #define SDHCI_DIVIDER_SHIFT 8 #define SDHCI_DIVIDER_HI_SHIFT 6 -#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK 0xFF #define SDHCI_DIV_MASK_LEN 8 #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 @@ -146,6 +173,10 @@ #define SDHCI_INT_CARD_REMOVE 0x00000080 #define SDHCI_INT_CARD_INT 0x00000100 #define SDHCI_INT_RETUNE 0x00001000 + +/* Host Version 4.10 */ +#define SDHCI_INT_FX_EVENT 0x00002000 + #define SDHCI_INT_CQE 0x00004000 #define SDHCI_INT_ERROR 0x00008000 #define SDHCI_INT_TIMEOUT 0x00010000 @@ -160,6 +191,9 @@ #define SDHCI_INT_ADMA_ERROR 0x02000000 #define SDHCI_INT_TUNING_ERROR 0x04000000 =20 +/* Host Version 4.0 */ +#define SDHCI_INT_RESP_ERR 0x08000000 + #define SDHCI_INT_NORMAL_MASK 0x00007FFF #define SDHCI_INT_ERROR_MASK 0xFFFF8000 =20 @@ -186,6 +220,9 @@ #define SDHCI_AUTO_CMD_END_BIT 0x00000008 #define SDHCI_AUTO_CMD_INDEX 0x00000010 =20 +/* Host Version 4.10 */ +#define SDHCI_AUTO_CMD_RESP_ERR 0x0020 + #define SDHCI_HOST_CONTROL2 0x3E #define SDHCI_CTRL_UHS_MASK 0x0007 #define SDHCI_CTRL_UHS_SDR12 0x0000 @@ -194,6 +231,7 @@ #define SDHCI_CTRL_UHS_SDR104 0x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_UHS2 0x0007 #define SDHCI_CTRL_VDD_180 0x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 @@ -202,9 +240,12 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_UHS2_ENABLE 0x0100 +#define SDHCI_CTRL_ADMA2_LEN_MODE 0x0400 #define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 =20 #define SDHCI_CAPABILITIES 0x40 @@ -227,11 +268,13 @@ #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INT 0x20000000 =20 #define SDHCI_CAPABILITIES_1 0x44 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 #define SDHCI_SUPPORT_DDR50 0x00000004 +#define SDHCI_SUPPORT_UHS2 0x00000008 #define SDHCI_DRIVER_TYPE_A 0x00000010 #define SDHCI_DRIVER_TYPE_C 0x00000020 #define SDHCI_DRIVER_TYPE_D 0x00000040 @@ -240,6 +283,7 @@ #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) #define SDHCI_CAN_DO_ADMA3 0x08000000 +#define SDHCI_CAN_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */ #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ =20 #define SDHCI_MAX_CURRENT 0x48 @@ -247,11 +291,14 @@ #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) +#define SDHCI_MAX_CURRENT_1 0x4C +#define SDHCI_MAX_CURRENT_VDD2_180_MASK GENMASK(7, 0) /* UHS2 */ #define SDHCI_MAX_CURRENT_MULTIPLIER 4 =20 /* 4C-4F reserved for more max current */ =20 #define SDHCI_SET_ACMD12_ERROR 0x50 +/* Host Version 4.10 */ #define SDHCI_SET_INT_ERROR 0x52 =20 #define SDHCI_ADMA_ERROR 0x54 @@ -270,10 +317,15 @@ #define SDHCI_PRESET_FOR_SDR104 0x6C #define SDHCI_PRESET_FOR_DDR50 0x6E #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ + +/* UHS2 */ +#define SDHCI_PRESET_FOR_UHS2 0x74 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) #define SDHCI_PRESET_CLKGEN_SEL BIT(10) #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) =20 +#define SDHCI_ADMA3_ADDRESS 0x78 + #define SDHCI_SLOT_INT_STATUS 0xFC =20 #define SDHCI_HOST_VERSION 0xFE --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E04362038DF; Fri, 18 Oct 2024 10:53:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248838; cv=none; b=G9QoMDLIN7XQIshsAPX3kBI52z04EUvwpoT+gdttuH7OnrLz8aEpLjkxoBTIKl1CAOPB6NF/CLPYowZkzmnNqMyWi5MWkFntAqmnaUcz4sM0kiBW7bnw2y0/KxocUxGK3sG13vYpIOut3jtW+QTiXD2XmkSQ3h76KiQAeIxrSnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248838; c=relaxed/simple; bh=BwlaZItjOFI0S0BMaprRVSJVkucKk6rCBi3r2JVKQsE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qlnqKDhd3obgJBkyQWqkDClBBGDc+njMIJv6QPF8ioOao+CMlgjf6f176O2eLLQfo9YqkSyvhubWxOYsIA/07h0BhWSgKZtmuBfwkIMmokYcchhkcZbJ0vq9GN2oU3LWvbdCAHd4Tv29atJbymjUlkEqmrxBmqkN9QvA243heJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hQ7rwBYT; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hQ7rwBYT" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-20cdda5cfb6so19674875ad.3; Fri, 18 Oct 2024 03:53:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248836; x=1729853636; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vQmQrgyNCodGsShz8Y8raLHteS/hxhDy8ogZA9Qt0jw=; b=hQ7rwBYTVaousbg1BTAQjEOH6oxbw0nbXHSgc7i9FuA+hDw62GGL21nM1bnICOOmhc MOgkhtV98XDelmXXo//rT/oP4+aX0P6KJCPlSvc1BpgCijkwp++vcKkUDATj3pe6GH5a WwEqnodGhhNv3qgEd5kUk/EQpUlIWtHbk82RGZSf/J4AGE4xBeaaBZX5nRWAT5Pfzdhm H4igWR3jp2VlXfiUmFtJ59jQy8vtGwZprWImrZTEIq06SSwdKKhC26RtycoVGdWq83Rm FmwBhPOG0RalFAPDkE3aTypQw7GctShhksLYwcu1EzQLR1S4fL7yC1mDYnyPZ4HHT6TQ cKVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248836; x=1729853636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vQmQrgyNCodGsShz8Y8raLHteS/hxhDy8ogZA9Qt0jw=; b=YFT8VNbXMraSYhEp8fFNpVn7gyF1N7GgUxcljsnxVYRrwpgU9BD9/lQxYsmWl1D3Vz gNbfu0vcherMaQxNlNA3t0NgOFjF1gq29fsezccg90pw8SBglrA3euJuI054B5zNi08S CtsNooJm5wGtRIdO9ei4i7vHKEPAHbdR534sFi9DAkdR4GX9bV6OD2W1At6zYARAI6yD tmPpteaHu1lFPbhHUMj577cJRyW0sZ1mlSdKkDFbL9iVzRt6zUJerULOEPOvYGPZw8Ye 2FAd0z1ke+nuVQCdYTSX5yvgCwFL7MdDo9RrYv+BebvePCD/XYAlsQ1Tf2DCoCLMd1KF SRQQ== X-Forwarded-Encrypted: i=1; AJvYcCWrKA2peIApU892x9aNYC99lsiNsKafLSHBD2SaKrfkbjghjbDLHT67ydlhfjbCJkIfvuQrR67G2EMTh6w=@vger.kernel.org X-Gm-Message-State: AOJu0Yw8M2M9gm3uZ+VSKU2WeEKUhbiEuF1PeyDMsDB8dWOwrpN54Sad Ca7CFmXXSIBzvGF0e6kHvdnNT83a9uj3m7NAs0ZWZfpmMMQvsNY+UZUIQA== X-Google-Smtp-Source: AGHT+IHhf7t8DbD3XLuf+75IAUKYiofwBuzdKdmc03Pw2z9hf9gb80JFfjeTm6OjYdDdzRHUdlBpvQ== X-Received: by 2002:a17:902:e807:b0:20c:5e86:9b53 with SMTP id d9443c01a7336-20e5a79f738mr23510345ad.3.1729248836073; Fri, 18 Oct 2024 03:53:56 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:53:55 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 03/16] mmc: sdhci: add UHS-II module and add a kernel configuration Date: Fri, 18 Oct 2024 18:53:20 +0800 Message-Id: <20241018105333.4569-4-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This patch adds sdhci-uhs2.c as a module for UHS-II support. This is a skeleton for further development in this patch series. This kernel configuration, CONFIG_MMC_SDHCI_UHS2, will be used in the following commits to indicate UHS-II specific code in sdhci controllers. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V22: - Remove defined but not used code. Updates in V9: - Modify the commit message. Updates in V8: - Modify MODULE_LICENSE from "GPL v2" to "GPL". Updates in V6: - Merage V5 of patch[7] and patch[9] in to V6 of patch[8]. --- drivers/mmc/host/Kconfig | 9 ++++++++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-uhs2.c | 41 +++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) create mode 100644 drivers/mmc/host/sdhci-uhs2.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 0ba5a9f769fb..45df8ddb8918 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -98,6 +98,15 @@ config MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER =20 This is the case for the Nintendo Wii SDHCI. =20 +config MMC_SDHCI_UHS2 + tristate "UHS2 support on SDHCI controller" + depends on MMC_SDHCI + help + This option is selected by SDHCI controller drivers that want to + support UHS2-capable devices. + + If you have a controller with this feature, say Y or M here. + config MMC_SDHCI_PCI tristate "SDHCI support on PCI bus" depends on MMC_SDHCI && PCI diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 3ccffebbe59b..5147467ec825 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_PXA) +=3D pxamci.o obj-$(CONFIG_MMC_MXC) +=3D mxcmmc.o obj-$(CONFIG_MMC_MXS) +=3D mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) +=3D sdhci.o +obj-$(CONFIG_MMC_SDHCI_UHS2) +=3D sdhci-uhs2.o obj-$(CONFIG_MMC_SDHCI_PCI) +=3D sdhci-pci.o sdhci-pci-y +=3D sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o= \ sdhci-pci-dwc-mshc.o sdhci-pci-gli.o diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c new file mode 100644 index 000000000000..9ec1d6abb47c --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * linux/drivers/mmc/host/sdhci_uhs2.c - Secure Digital Host Controller + * Interface driver + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + * Copyright (C) 2020 Genesys Logic, Inc. + * Authors: Ben Chuang + * Copyright (C) 2020 Linaro Limited + * Author: AKASHI Takahiro + */ + +#include + +#include "sdhci.h" +#include "sdhci-uhs2.h" + +#define DRIVER_NAME "sdhci_uhs2" +#define DBG(f, x...) \ + pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) + +/*************************************************************************= ****\ + * = * + * Driver init/exit = * + * = * +\*************************************************************************= ****/ + +static int __init sdhci_uhs2_mod_init(void) +{ + return 0; +} +module_init(sdhci_uhs2_mod_init); + +static void __exit sdhci_uhs2_mod_exit(void) +{ +} +module_exit(sdhci_uhs2_mod_exit); + +MODULE_AUTHOR("Intel, Genesys Logic, Linaro"); +MODULE_DESCRIPTION("MMC UHS-II Support"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A3B220408C; Fri, 18 Oct 2024 10:54:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248842; cv=none; b=shNe2J8VF6oVqF5+0RIW5Vzki/z4w5SiBbU2sPPMMa2iVSrgcsbLGz7twe1+n6B7SAEyQi4138fS3oqOY+MbEmJD+y4iKFwWdQz4zAmvahxhLRQRnohOwHq4U2yZXZZ8W8dSUxtjmOVtf6pvz5N70ojB43cQoPZJWQ1LbAVF2ow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248842; c=relaxed/simple; bh=xwFiWQ5tOpWStPyh3+9Y+jsJxfVLG9TjYX8BQUYRy6U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JkHJV3G32SA1VCZLSgpeLEwHYm9tzaxViwkiUW0F9bezwkBByjKltOrBKUFbDB5E+BBGfIW0VpMeMSh4lrUcFQG9uNPfoPkX8ropbwSeQvDCK68Lf958tmRt0jGam48FCeTJ3sMsV+CQNOGnoQzaI/eXsf/pfw8DVpUt4hbyoZc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bzg9F5Wz; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bzg9F5Wz" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-20c8b557f91so20992165ad.2; Fri, 18 Oct 2024 03:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248840; x=1729853640; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tY1jYPZ8EM+61uC7VsYBzo9x1mBBtiuwXTRSGcxof4I=; b=bzg9F5WzFvqqyVNal4J1v0yRdBvszvkC31+mv0J2fiNEa2csxoezqe0js7WU/FQrfc T0/e43/4BgBPW8psRjd+XCFU0VwLBccN9o5zr9kEGbR+MATX+rrPVH6kn89cdhQU+HQs dhSW+xb08XM9ii61DEKUfjyTNps75gZ4qMA9M6vRHkBwd7UOiat+BDJ6t477WzkR4+z8 pejuWA3K/JIKtbdajL+WdXTfq3uFymqU+4IUstQbND35exwdW1d+IRoT2cAIfG7N0Xs4 lhFO3H83GGKlFr9iwSaf/WGBtmF6sUg559Xh11+Lg24hmJjtyOZwLu/TRpMjCzyUIrkN Fa2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248840; x=1729853640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tY1jYPZ8EM+61uC7VsYBzo9x1mBBtiuwXTRSGcxof4I=; b=MIsRTZGdQoeq3VOIP6SYEFbo1Dqw977W0Zctu918wdTgCWsX15mE+PAUkkPzFS2ZTb BkquIzmoU6ta0vdI5F7N95mP0Y/453B9I9AxCLgxpR2Yrc+OJlSt5J77aEHhOi2TzygM +Gpv3CM4w8bi5t4quM2p/X26QuOF0MQl2lVQBjuE4jKrSs3GeoCdh9PlnBG8VUORCNJG gVXEe+yhooi5ipf9Y4tGxMCiTpMbfJ+gO19rRo+cAzNwKqEIAzQ3y6pZl80fekyw4/Zv 93wmpaJKoBpBnoNQfqCD0+TXykZdUY4gOjM4+xs0NzK8LL5PKa1nDzq0wLZnr72nIMtV 8iAA== X-Forwarded-Encrypted: i=1; AJvYcCXVLH4yA2ZATc0VGzAudb+TOGxSVK4szi5clcAxf0kvXm1df1OkQC4UATZuMKMya0T1WTgaSMHi1cpEP6E=@vger.kernel.org X-Gm-Message-State: AOJu0YyAYQjvB0MXmEZBDx2YMLf4NLStv9JtKvbeAKUkGfjky/ikR/tM Rr79eSW7ifPy6fvvCWIBz1jiXgBa6QqfEBzoE+dPBJntTUuD+aLk X-Google-Smtp-Source: AGHT+IFiQzqWTXZBnEku2Up+j+doO27pnfDz8PRF8/S6R9GPczV1BhE0SnbLm8tvz1g6NVFdh1k+PA== X-Received: by 2002:a17:902:ec8e:b0:206:aac4:b844 with SMTP id d9443c01a7336-20e5a709796mr27794305ad.6.1729248840498; Fri, 18 Oct 2024 03:54:00 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:00 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 04/16] mmc: sdhci-uhs2: dump UHS-II registers Date: Fri, 18 Oct 2024 18:53:21 +0800 Message-Id: <20241018105333.4569-5-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih Dump UHS-II specific registers, if available, in sdhci_dumpregs() for informative/debugging use. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V14: - Use mmc_card_uhs2() to stead sdhci_uhs2_mode() in the sdhci_uhs2_dump_regs(). Updates in V7: - Use sdhci_uhs2_mode() to simplify code. Updates in V6: - Remove unnecessary code. --- drivers/mmc/host/sdhci-uhs2.c | 30 ++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 4 ++++ drivers/mmc/host/sdhci.c | 3 +++ drivers/mmc/host/sdhci.h | 1 + 4 files changed, 38 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 9ec1d6abb47c..14514710e763 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -18,6 +18,36 @@ #define DRIVER_NAME "sdhci_uhs2" #define DBG(f, x...) \ pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) +#define SDHCI_UHS2_DUMP(f, x...) \ + pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) + +void sdhci_uhs2_dump_regs(struct sdhci_host *host) +{ + if (!(mmc_card_uhs2(host->mmc))) + return; + + SDHCI_UHS2_DUMP("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D UHS2 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); + SDHCI_UHS2_DUMP("Blk Size: 0x%08x | Blk Cnt: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_BLOCK_SIZE), + sdhci_readl(host, SDHCI_UHS2_BLOCK_COUNT)); + SDHCI_UHS2_DUMP("Cmd: 0x%08x | Trn mode: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_CMD), + sdhci_readw(host, SDHCI_UHS2_TRANS_MODE)); + SDHCI_UHS2_DUMP("Int Stat: 0x%08x | Dev Sel : 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_DEV_INT_STATUS), + sdhci_readb(host, SDHCI_UHS2_DEV_SELECT)); + SDHCI_UHS2_DUMP("Dev Int Code: 0x%08x\n", + sdhci_readb(host, SDHCI_UHS2_DEV_INT_CODE)); + SDHCI_UHS2_DUMP("Reset: 0x%08x | Timer: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_SW_RESET), + sdhci_readw(host, SDHCI_UHS2_TIMER_CTRL)); + SDHCI_UHS2_DUMP("ErrInt: 0x%08x | ErrIntEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_INT_STATUS), + sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE)); + SDHCI_UHS2_DUMP("ErrSigEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_INT_SIGNAL_ENABLE)); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); =20 /*************************************************************************= ****\ * = * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index e993f41ffb7f..2bfe18d29bca 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -174,4 +174,8 @@ #define SDHCI_UHS2_EMBED_CTRL_PTR 0xE6 #define SDHCI_UHS2_VENDOR_PTR 0xE8 =20 +struct sdhci_host; + +void sdhci_uhs2_dump_regs(struct sdhci_host *host); + #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 4b91c9e96635..5a5fe3528bb4 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -110,6 +110,9 @@ void sdhci_dumpregs(struct sdhci_host *host) } } =20 + if (host->ops->dump_uhs2_regs) + host->ops->dump_uhs2_regs(host); + if (host->ops->dump_vendor_regs) host->ops->dump_vendor_regs(host); =20 diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index e1013925e91e..66ab90bd4017 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -719,6 +719,7 @@ struct sdhci_ops { void (*request_done)(struct sdhci_host *host, struct mmc_request *mrq); void (*dump_vendor_regs)(struct sdhci_host *host); + void (*dump_uhs2_regs)(struct sdhci_host *host); }; =20 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C01D202649; Fri, 18 Oct 2024 10:54:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248847; cv=none; b=OnkrMPIE//7IymkOVNJXlBpqcjsULT61h5i7p9lACLxBr29h4af55cIIXxZoLf6k74TLiV5uIR7Qf2npQKdIbkHuaAaHb6nzgAa5nfz2aoHWQNq462gn98peuC/a73q8SJCey8jYYxh1vZn5wFIjDtqiZ9LixqJ/VN728TSaB8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248847; c=relaxed/simple; bh=CdA3SI06ubeqqm9CRejDKr9MVIb3Sm3bm+DpHuLlSdk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kTutHia2/rdBfSV2mxSAfkch/b83Od/ZkJ3+Vq4CUA0BJgUc9Oe4nW8tzqWd7HXeMYOG1RXeXWtNjuaaeD6v/kz2dJCL1EEMwOZ234uOziwJSmNPKI4jQ+3xibqHNNFgopS/rM+5ZbiCevhd5WhDCGjDHX4C0jnrIMisgbutDNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JpqOSyLu; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JpqOSyLu" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-20b5affde14so13851245ad.3; Fri, 18 Oct 2024 03:54:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248845; x=1729853645; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tpaYtlLd3mQ+A9z10aDKxE+hmD+tiwgrXgbBd5u7JA4=; b=JpqOSyLuFoBSsPaUiEFqRiUreOGRmJciMi4Rjle3lfGWxBJb8UD6uz49XrP7jrZylv ZLYEkGvfLDsEvL++jjx4Af5iat6AJ56COOAM+NUlZyzG97cr0SPjq4GYnOTCF+PgzsC2 fUnkIwKNYJa2dy7qYiHVpelcKWtc5oaSuDfsJbRm5w2ZtHsGWYUrXooQej3UEfmW2uOG lkGqLjphovNf8DbgtQ/UqXXwIljVAejSpvTbyqaO1qYsGtLpTmENMRFqEjCTga6ygLUf /SMvmdbNjTw2bOLpe9rAbZ4no/v9Jb02NeoUeAKnUrCfYiJyoY1q5N5YclS9FqKnc8Sy yO0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248845; x=1729853645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tpaYtlLd3mQ+A9z10aDKxE+hmD+tiwgrXgbBd5u7JA4=; b=RaDoYmiojeQJ1AhDnD995gVQbt6GTNZiqUUxGJyZFR1mAP/qLqm18CPQ0uwG7k+2FK aTqa8dxYC7hfJaOAh9cDksZCbKxlbJxbkre+u6STzXfShLe998HABxow8IrvGyiD9Id7 RhLbexGLHMSPSANTM5aw4QLyeFTnJfasA8SN5iIu3kDScL4hNZxIp9GYn5XrBoDHitG+ pg2Tkjz+TmDYpaqUeZjSM9ThE2j3ho8VXYS0Wcy89MxD+nEKLpkt/FOLCjbNvfQrSGmk 0fMn1OwHuDV7ztHcis9kLFnac5xB5Qk7veLfDEz3+xgZfOJlHJzQWcFz/qd4fzUXBBA+ 8LsQ== X-Forwarded-Encrypted: i=1; AJvYcCX73/bb3dv3H/fLYfuG9v1YWZ7bfIlg50M3Zbvw2mlKNKQ1yNGmrj1KLT9SZKfvV/u3l7XMMhfTijzTAGM=@vger.kernel.org X-Gm-Message-State: AOJu0YwIhkJuEZ2x84ZcpH3//ze3aJ+kaGlojNJmC5qbno+tRmo+/Xl8 UxW4ZMpb8f9umuk7nqAQK8dO5qHsj3hGUG1Xs1AN2eccprND+5tH X-Google-Smtp-Source: AGHT+IEwk7mdcOEMVWejwyQAdFkTXJjHgCrwya9POzb0LiOF9F0qebux0nNG9SdsXoohvLdv9+lGqg== X-Received: by 2002:a17:903:2303:b0:20c:ab29:8133 with SMTP id d9443c01a7336-20e5a89a930mr25317875ad.27.1729248844856; Fri, 18 Oct 2024 03:54:04 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:04 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 05/16] mmc: sdhci-uhs2: add reset function Date: Fri, 18 Oct 2024 18:53:22 +0800 Message-Id: <20241018105333.4569-6-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih Sdhci_uhs2_reset() does a UHS-II specific reset operation. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V17: - Move the sdhci_uhs2_reset_cmd_data() to the other patch it was used for the first time. Updates in V16: - Add sdhci_uhs2_reset_cmd_data() function. Updates in V15: - Refer the SD Host Controller Standard Specification Section 3.10 to add reset command data mechanism. Updates in V14: - Since mmc_card_uhs2() is the same as sdhci_uhs2_mode(), so drop sdhci_uhs2_mode() and use mmc_card_uhs2() instead of sdhci_uhs2_mode(). Updates in V13: - Use ios timing to stead MMC_UHS2_SUPPORT for indicate the UHS2 mode. Updates in V8: - Adjust the position of matching brackets. Updates in V6: - Remove unnecessary functions and simplify code. --- drivers/mmc/host/sdhci-uhs2.c | 37 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 1 + 2 files changed, 38 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 14514710e763..71c60952a40a 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -10,7 +10,9 @@ * Author: AKASHI Takahiro */ =20 +#include #include +#include =20 #include "sdhci.h" #include "sdhci-uhs2.h" @@ -21,6 +23,8 @@ #define SDHCI_UHS2_DUMP(f, x...) \ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) =20 +#define UHS2_RESET_TIMEOUT_100MS 100000 + void sdhci_uhs2_dump_regs(struct sdhci_host *host) { if (!(mmc_card_uhs2(host->mmc))) @@ -49,6 +53,39 @@ void sdhci_uhs2_dump_regs(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); =20 +/*************************************************************************= ****\ + * = * + * Low level functions = * + * = * +\*************************************************************************= ****/ + +/** + * sdhci_uhs2_reset - invoke SW reset + * @host: SDHCI host + * @mask: Control mask + * + * Invoke SW reset, depending on a bit in @mask and wait for completion. + */ +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) +{ + u32 val; + + sdhci_writew(host, mask, SDHCI_UHS2_SW_RESET); + + if (mask & SDHCI_UHS2_SW_RESET_FULL) + host->clock =3D 0; + + /* hw clears the bit when it's done */ + if (read_poll_timeout_atomic(sdhci_readw, val, !(val & mask), 10, + UHS2_RESET_TIMEOUT_100MS, true, host, SDHCI_UHS2_SW_RESET)) { + pr_warn("%s: %s: Reset 0x%x never completed. %s: clean reset bit.\n", __= func__, + mmc_hostname(host->mmc), (int)mask, mmc_hostname(host->mmc)); + sdhci_writeb(host, 0, SDHCI_UHS2_SW_RESET); + return; + } +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); + /*************************************************************************= ****\ * = * * Driver init/exit = * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 2bfe18d29bca..caaf9fba4975 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -177,5 +177,6 @@ struct sdhci_host; =20 void sdhci_uhs2_dump_regs(struct sdhci_host *host); +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); =20 #endif /* __SDHCI_UHS2_H */ --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE31A2038CC; Fri, 18 Oct 2024 10:54:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248851; cv=none; b=mFxe0euYqG5FT5cqNEgfaRFd5LNv+XFKVQh+6oG/AVs8oxMFgrzozMN29AI81KV8Bj3G7177eD0VvpthSXpflqJ9vk0Iq9BTQSv8sU2i4Z4RSK016PkDyNP4tpJb4n+QC+F7Sz0ol2McmQyb66Y/sYXAw7xe7oxHOFJ7F+llTqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248851; c=relaxed/simple; bh=fQDWYr+jQmoqQTUgp8mWV6Y4NfpYcaQOSSQVxtmALkc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fZiH6Ar10D0NrRNrXbObNnf4Z+dpxjnZDaW627k1VsOA2ywRtGHXpYj/JpEY6nWXMqXXuzV6dMTrn5edCydNL9p5etLlQS42+XuGuF7Dj4jjy5WNJzvaiJZYCFOzEkJ6Ilg54rfMs4Blh9UoscK/LZI0cy9c/5iwGhgcMqBtODQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HYbF3M7g; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HYbF3M7g" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-20caccadbeeso21649065ad.2; Fri, 18 Oct 2024 03:54:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248849; x=1729853649; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KkFVFuS/YN350pgqfr+BTG2ZvmKtP6VzC+KxRi2hVRs=; b=HYbF3M7gwhtNh+syso3rP+UXDmgDJVUjBT3AAQM0DDPVH00b0RLYW2ijNrfFTPnrf0 8sCNtEzkH57Xf3p5qn8vMkyC4wsW+iynM9G626Z+1AzVreesQMX0w/3NVvbw3sM4GbRe +WEWa6ZlVbG3iuBW1F63HuNKUj8FxzKw9JMCpf4AxGAMAvtBNKQbLTho0sqCoULHxDsN mSTzNLWXzNM2PuYK70Vo8Ie2RtyxJXTxS4x4OimctjWxDzBNHFtwdoLc8F1TMEZjFeIT +FfrMI7rYbsGssY1X4gPrSXNVnpCNIjEn3atK6i36jmt/nN61rJxjXYNdVxANbDmOGwJ u8yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248849; x=1729853649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KkFVFuS/YN350pgqfr+BTG2ZvmKtP6VzC+KxRi2hVRs=; b=YrvTz3MYxndN+3Q1YF1UoQYzxr2zwoNgQ6HBpP6vCHjCR5smT3D1gctygmMmpz9YoW WV6GIBdwErcqbJ0PuNxPEhmwR2ErYJq25617ss3nYEXw9iEOqOoTsRMiNoEAX/jcv46E 71sLAtC5cvWM3Aezh9DjwKLTHngHjGw2LKfUzDqdRiqWCdF4vnySghGnaJXSrrRyrA2c 9JL1VKwlwm2k8n9sgKqcdSdyu9sPIY+soip3vpUadlucXHO2LH5DH8vSNgjw+r8JzDPw UByGBT1JEU8RaIB30GieAsfEaC5FcLnXaQuqlabU3PvKrHVSAJq1NXEe7t6e//ad6SP0 l7Jg== X-Forwarded-Encrypted: i=1; AJvYcCVL/TFGxQI3snFLhaO3/M1beBY8d2jwflCYTL370qXVHm8gY89k8KYxRmgl9dFNKn2UzLzxl4cAIsnbF6o=@vger.kernel.org X-Gm-Message-State: AOJu0Yx5J6AFqHnDYNzfQIjLh4zLV084RdWtJBrC4r/XHxdM0Edvrxef QLEMekybBVtgjVu49iQ0tfJAnZNtEh2OcJZpY1bGvByew9Df8jKy X-Google-Smtp-Source: AGHT+IF3png9daJoIgbcloAFlJLpLWLNQEycbZWwcXgiVkLYEPxsFRxqT39vcV7aD0ggBQQql/585w== X-Received: by 2002:a17:902:cec3:b0:20c:d469:ba95 with SMTP id d9443c01a7336-20e5a8b03c0mr21873175ad.16.1729248849053; Fri, 18 Oct 2024 03:54:09 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:08 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 06/16] mmc: sdhci-uhs2: add set_power() to support vdd2 Date: Fri, 18 Oct 2024 18:53:23 +0800 Message-Id: <20241018105333.4569-7-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This is a UHS-II version of sdhci's set_power operation. Use sdhci_uhs2_set_power() to set VDD2 for support UHS2 interface. VDD2, as well as VDD, is handled here. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V17: - Export sdhci_uhs2_set_power() function. Updates in V13: - Drop use vmmc2. - Modify comment message. Updates in V10: - Move some definitions of PatchV9[05/23] to PatchV10[11/23]. Updates in V9: - Modify annotations in sdhci_get_vdd_value(). Updates in V8: - Adjust the position of matching brackets. - Add the initial value of the pwr in sdhci_uhs2_set_power(). Updates in V7: - Add clear the power reg before setting a new value in sdhci_uhs2_set_power(). - Add MMC_VDD_34_35 case and MMC_VDD_35_36 case in sdhci_get_vdd_value(). - Drop pwr variable in sdhci_get_vdd_value(). Updates in V6: - Add mmc_opt_regulator_set_ocr(). - Remove unnecessary functions. --- drivers/mmc/host/sdhci-uhs2.c | 49 ++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 1 + drivers/mmc/host/sdhci.c | 61 +++++++++++++++++++---------------- drivers/mmc/host/sdhci.h | 1 + 4 files changed, 84 insertions(+), 28 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 71c60952a40a..756e44d84b87 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -59,6 +59,13 @@ EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); * = * \*************************************************************************= ****/ =20 +static inline int mmc_opt_regulator_set_ocr(struct mmc_host *mmc, + struct regulator *supply, + unsigned short vdd_bit) +{ + return IS_ERR_OR_NULL(supply) ? 0 : mmc_regulator_set_ocr(mmc, supply, vd= d_bit); +} + /** * sdhci_uhs2_reset - invoke SW reset * @host: SDHCI host @@ -86,6 +93,48 @@ void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) } EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); =20 +void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, uns= igned short vdd) +{ + struct mmc_host *mmc =3D host->mmc; + u8 pwr =3D 0; + + if (mode !=3D MMC_POWER_OFF) { + pwr =3D sdhci_get_vdd_value(vdd); + if (!pwr) + WARN(1, "%s: Invalid vdd %#x\n", + mmc_hostname(host->mmc), vdd); + pwr |=3D SDHCI_VDD2_POWER_180; + } + + if (host->pwr =3D=3D pwr) + return; + host->pwr =3D pwr; + + if (pwr =3D=3D 0) { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + mmc_regulator_set_vqmmc2(mmc, &mmc->ios); + } else { + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + /* support 1.8v only for now */ + mmc_regulator_set_vqmmc2(mmc, &mmc->ios); + + /* Clear the power reg before setting a new value */ + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + /* vdd first */ + pwr |=3D SDHCI_POWER_ON; + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + mdelay(5); + + pwr |=3D SDHCI_VDD2_POWER_ON; + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + mdelay(5); + } +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_set_power); + /*************************************************************************= ****\ * = * * Driver init/exit = * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index caaf9fba4975..3efa8dd690bf 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -178,5 +178,6 @@ struct sdhci_host; =20 void sdhci_uhs2_dump_regs(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); +void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, uns= igned short vdd); =20 #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 5a5fe3528bb4..366c3d30dba6 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -23,7 +23,7 @@ #include #include #include - +#include #include =20 #include @@ -2061,41 +2061,46 @@ static void sdhci_set_power_reg(struct sdhci_host *= host, unsigned char mode, sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); } =20 +unsigned short sdhci_get_vdd_value(unsigned short vdd) +{ + switch (1 << vdd) { + case MMC_VDD_165_195: + /* + * Without a regulator, SDHCI does not support 2.0v + * so we only get here if the driver deliberately + * added the 2.0v range to ocr_avail. Map it to 1.8v + * for the purpose of turning on the power. + */ + case MMC_VDD_20_21: + return SDHCI_POWER_180; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + return SDHCI_POWER_300; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + /* + * 3.4V ~ 3.6V are valid only for those platforms where it's + * known that the voltage range is supported by hardware. + */ + case MMC_VDD_34_35: + case MMC_VDD_35_36: + return SDHCI_POWER_330; + default: + return 0; + } +} +EXPORT_SYMBOL_GPL(sdhci_get_vdd_value); + void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, unsigned short vdd) { u8 pwr =3D 0; =20 if (mode !=3D MMC_POWER_OFF) { - switch (1 << vdd) { - case MMC_VDD_165_195: - /* - * Without a regulator, SDHCI does not support 2.0v - * so we only get here if the driver deliberately - * added the 2.0v range to ocr_avail. Map it to 1.8v - * for the purpose of turning on the power. - */ - case MMC_VDD_20_21: - pwr =3D SDHCI_POWER_180; - break; - case MMC_VDD_29_30: - case MMC_VDD_30_31: - pwr =3D SDHCI_POWER_300; - break; - case MMC_VDD_32_33: - case MMC_VDD_33_34: - /* - * 3.4 ~ 3.6V are valid only for those platforms where it's - * known that the voltage range is supported by hardware. - */ - case MMC_VDD_34_35: - case MMC_VDD_35_36: - pwr =3D SDHCI_POWER_330; - break; - default: + pwr =3D sdhci_get_vdd_value(vdd); + if (!pwr) { WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); - break; } } =20 diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 66ab90bd4017..0f78708d0c70 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -836,6 +836,7 @@ void sdhci_set_power(struct sdhci_host *host, unsigned = char mode, void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, unsigned char mode, unsigned short vdd); +unsigned short sdhci_get_vdd_value(unsigned short vdd); void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, unsigned short vdd); int sdhci_get_cd_nogpio(struct mmc_host *mmc); --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EC5F202F72; Fri, 18 Oct 2024 10:54:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248856; cv=none; b=AsA5jroraVkfxqdW8MdYT3dHo4IStJMgbTWD6LAHFAmpTfYcxAyY05XJ7VWFbBjV67Rv/ks0heBHPCtNFh2BaSXDVE/Oj/wzftTgcg41JkyM0hj5ql5k5srKDPehU93LMgJPRU9VjlWWACcy+9NNMh3DTusZ1QRvaybwm5V6/D0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248856; c=relaxed/simple; bh=VB5pAfZlY5yWHbxrV1VvySF25vuCBwsa2Yimme8Jx9w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aDkVxNHb0ALm6w0xCPjvN/qowHcAX3hSwKYIko6ceFmcAHnPW0VXSfOzzVsmvBFhlIeEJkdzRRmitP87GLixL40NyeYqdblQ3F/dxKL/6COSoreiy1hjQr2gUywP7uXzNS8IZtBxay8wZ5kC6gS3Al19EyebYfIqbqNFWxkpudU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=D0dQhcQM; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D0dQhcQM" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-20c693b68f5so21559835ad.1; Fri, 18 Oct 2024 03:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248854; x=1729853654; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hGS5FnAtxOoJb/6wOxS2ea2cNEevmIiG+LI1be0l3jU=; b=D0dQhcQMA6eKkLGL575yWpfECiBAtDFsx7VxVRvaV4PIs6uyUIoz387CKDPhPhH1wy 4EJ87rNhU7bKuKmHCJxn6e1NzgBw2FtsLaRu4bHXLpioOD3rXVbhWNFAJNvPg1mXia+q 2vLTjLciQh83TtJJzUNZV7KcHEuzj7kaExco4h9XvQFimbefmSZ35LxiFnpAOtPsccc5 SGYWrAOOhNgHNXu/ne6nA/i3c5ZpvHg+79aQSi23zfmxFsj6/Cp/LdNmKyvbr+IVs9D1 1O6XpGcJOkv6+fLhDIfdS3riKSpS2lYRI2H95bBvhE3jNIdYVQdjnXnXtuD4FME9JZqX RhWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248854; x=1729853654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hGS5FnAtxOoJb/6wOxS2ea2cNEevmIiG+LI1be0l3jU=; b=eFtYuxDEr/YkcLnaD9cUSNiIls1FizVjloUYBEj2bHtxXbj4DfLd9dKnzN5FuxEkzX 5fIzmtmuVGSG3A4y9t1lXbD/O7FDdcclV8v3ZmcgdAg+rXJ/z1TrvXR2ForJIRU7PdU3 3AxfhPZIJqh2auT9/IfFbdgJ37RbKbU+bzQsKS8Jj2IQpr3EaG+t7Mrx6WCXRGPNkjSW JmUX5hzBxcpFu0qzPhRbvWTX15MTmFk5pt2d+Vg9frS2D/vOBp8jvOMiCqkx9lI4KZqN 6KnBcTJil/yvVp/I6sDK1H1xjrYdI9OO/bp/CGv3VLBWhPwxd8QCi09WEGMLVp6LyWbg S7zg== X-Forwarded-Encrypted: i=1; AJvYcCVfhg0hx+9I8l5ufG7k3aABRsJoeJDnsb6NTheJ3pFnvfSEec6wSK1/JwX262FwCGRGZGOF59bn80EY5oM=@vger.kernel.org X-Gm-Message-State: AOJu0YyrkMkBvWt4fTmk9n1Bm7XOjMlJnDS3fpEn4j1pIPTA3kNNT8hS Yk+kglN9fVFFIxxgGB9UacyF7FrWJ6BixtwPyCUazsShh8x+iK5JV+q/3A== X-Google-Smtp-Source: AGHT+IGFIw4MCpwUYyysC9aeT84AnFkvJ4pEVcGeOW//2XwIrhsz/5/0eVfHmRpLlUCXUwnsecVyyQ== X-Received: by 2002:a17:903:32c2:b0:20c:b274:34d0 with SMTP id d9443c01a7336-20e5a913801mr23688565ad.46.1729248853826; Fri, 18 Oct 2024 03:54:13 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:13 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 07/16] mmc: sdhci-uhs2: add set_timeout() Date: Fri, 18 Oct 2024 18:53:24 +0800 Message-Id: <20241018105333.4569-8-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This is a UHS-II version of sdhci's set_timeout() operation. Use sdhci_uhs2_set_timeout() to set and calculate the timeout time. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V14: - Use mmc_card_uhs2() to stead sdhci_uhs2_mode() in the sdhci_uhs2_set_timeout(). Updates in V13: - Modify comment message. Updates in V8: - Initialization be combined with declaration and realigned in sdhci_calc_timeout_uhs2(). - Forward declare struct mmc_command in sdhci_uhs2.h. Updates in V6: - Use GENMASK() and FIELD_PREP() in some case. - Use sdhci_uhs2_mode() to simplify code. - Remove unnecessary functions. --- drivers/mmc/host/sdhci-uhs2.c | 72 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 + 2 files changed, 74 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 756e44d84b87..6b249eb8395a 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include "sdhci.h" #include "sdhci-uhs2.h" @@ -135,6 +136,77 @@ void sdhci_uhs2_set_power(struct sdhci_host *host, uns= igned char mode, unsigned } EXPORT_SYMBOL_GPL(sdhci_uhs2_set_power); =20 +static u8 sdhci_calc_timeout_uhs2(struct sdhci_host *host, u8 *cmd_res, u8= *dead_lock) +{ + /* timeout in us */ + unsigned int dead_lock_timeout =3D 1 * 1000 * 1000; + unsigned int cmd_res_timeout =3D 5 * 1000; + unsigned int current_timeout; + u8 count; + + /* + * Figure out needed cycles. + * We do this in steps in order to fit inside a 32 bit int. + * The first step is the minimum timeout, which will have a + * minimum resolution of 6 bits: + * (1) 2^13*1000 > 2^22, + * (2) host->timeout_clk < 2^16 + * =3D> + * (1) / (2) > 2^6 + */ + count =3D 0; + current_timeout =3D (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < cmd_res_timeout) { + count++; + current_timeout <<=3D 1; + if (count >=3D 0xF) + break; + } + + if (count >=3D 0xF) { + DBG("%s: Too large timeout 0x%x requested for CMD_RES!\n", + mmc_hostname(host->mmc), count); + count =3D 0xE; + } + *cmd_res =3D count; + + count =3D 0; + current_timeout =3D (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < dead_lock_timeout) { + count++; + current_timeout <<=3D 1; + if (count >=3D 0xF) + break; + } + + if (count >=3D 0xF) { + DBG("%s: Too large timeout 0x%x requested for DEADLOCK!\n", + mmc_hostname(host->mmc), count); + count =3D 0xE; + } + *dead_lock =3D count; + + return count; +} + +static void __sdhci_uhs2_set_timeout(struct sdhci_host *host) +{ + u8 cmd_res, dead_lock; + + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + cmd_res |=3D FIELD_PREP(SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK, dead_lock); + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); +} + +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *c= md) +{ + __sdhci_set_timeout(host, cmd); + + if (mmc_card_uhs2(host->mmc)) + __sdhci_uhs2_set_timeout(host); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_set_timeout); + /*************************************************************************= ****\ * = * * Driver init/exit = * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 3efa8dd690bf..9bd3f610cf8c 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -175,9 +175,11 @@ #define SDHCI_UHS2_VENDOR_PTR 0xE8 =20 struct sdhci_host; +struct mmc_command; =20 void sdhci_uhs2_dump_regs(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, uns= igned short vdd); +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *c= md); =20 #endif /* __SDHCI_UHS2_H */ --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8209520265D; Fri, 18 Oct 2024 10:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248862; cv=none; b=XLvB56OsAuT+BRc17Hu5wFX83k89D/2yR86En3d6GNEq2frU6sOaqPL9ic5jbX3U1f3IJ5k126LM4YxChIVyTXYMiH6UnmCm5e0p+vPcgcQBJpJqXyy9rqTDKWlVMZ8zTSYbIcHEMMz7HeBGGHV8lalOMsQ9muzFasiz8HEVYVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248862; c=relaxed/simple; bh=YFLqV890Z42BNuleGy/377WU3cFQMODtUvsZxEvUggE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JdeSq5ene7QX0oHM4KmKBByP8eiggBsEw68gFD1jaGl461oqaNb/WG5WDkEDFsvFa7rK/3Ua/eJ+x8Ibyyl4wPfxirhZFba29Z+jhAO4w5It5JqblPWrIdcXECAdwe0/i0mXSU1BN9V50+FQcPCqUmu2IFhHsvSXbgyG+NTMpMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Xv2pq2Ss; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Xv2pq2Ss" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-20e576dbc42so7708815ad.0; Fri, 18 Oct 2024 03:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248859; x=1729853659; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sA8jKHOlnNb5oztdOQ8CqUpGZDm97ramC29vExw2ghw=; b=Xv2pq2Ss6wZhAeJ+qabq95JTCZYZJFmPXyt72tyIJx4A1NpO5UQ4He/pvRctGCNgzE povO4klMpr+objfJFAQvyi084XtYPxAVGu+1WzuzwnZOUOhbI8zWU76hejMzgYCofLZn vEFpzCoAfj0KYZ+vRYozRXZhtAyFE2Sj5amX6qanVlwHeaCUcCXAus+Bc4EzSwqr7k4U 4JIRtItE92GvZewCKmoy53E9CaJBg4fs1XYVJXHEiFMzi0Hv9ozi4sAo/8OB2uweDK5w dN0l1iOap2v9Kib8YxQpuEbGtYfuPiigiEeqczZB9oOjKAyAO9KB94elrX29nyzURyGe dIRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248859; x=1729853659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sA8jKHOlnNb5oztdOQ8CqUpGZDm97ramC29vExw2ghw=; b=HiPsOox64EZWEGlWQa1znLxWGuvLjeMa5Sd22dmdbjZ6nQinCZfgA7xqcjQ7MGPAiv KRVAkP6Jm05WoAGfrCuT//3UASY3YPJN4sWdmU5Q+VE4i8EQiEWVwVc6KS1Cv8y8tcl5 OGxgjcxrBO/29fv8oa/P4qfQjxJ5SKkF8GuqRkI4quibewM6viek3YPv/0alIeynDOYp NQ3MbWvQbJMytECz2qTw3C+N6XcruDCvo1QedTAP14izV/3jqShGOW/WE3Q+PAWGXZtT L6G1LIHImCp/jtRwICeRyDLhUJOgBJyy/H5J93523DrwGPhy63L1pGViNDTBvQlEFYSS 8Jwg== X-Forwarded-Encrypted: i=1; AJvYcCWvwtK31QyBMUBKcLYe9Wr/CNsIlTSpTT+c+H1eOVCrBz6Sd3HYEMHLfvV71HNLOYEZP3xNw4uA2hKU9jg=@vger.kernel.org X-Gm-Message-State: AOJu0YxMRWno1Hq8S8sA8mnbSEqVVjuNEXvSXCJq9mEVEtPOiyIWlwuf S+BhxOZYfF49aelr4doWrC9bCu8cEl7OF1yW84xDYE7fLS60EM9D X-Google-Smtp-Source: AGHT+IERopjt8r9bhq/ChS9B6ZO65gD63rvt5VLmh9BZQ1cWJ0Oi8Id6UQpRYAiFzub1gjFxVzCiLQ== X-Received: by 2002:a17:902:c412:b0:20b:c287:202d with SMTP id d9443c01a7336-20e5a9b14e2mr21154235ad.55.1729248858701; Fri, 18 Oct 2024 03:54:18 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:18 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 08/16] mmc: sdhci-uhs2: add add_host() and others to set up the driver Date: Fri, 18 Oct 2024 18:53:25 +0800 Message-Id: <20241018105333.4569-9-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This is a UHS-II version of sdhci's add_host/remove_host operation. Any sdhci drivers which are capable of handling UHS-II cards must call those functions instead of the corresponding sdhci's. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V22: - Adjust the patch order from v21 patch#18 to v22 patch#14 and remove unnecessary code to avoid defined but not used warnings. Updates in V14: - Use mmc_card_uhs2() to stead sdhci_uhs2_mode() in the __sdhci_uhs2_remove_host(). Updates in V13: - Re-order function to avoid declaration. - Use vqmmc2 to stead vmmc2. Updates in V11: - Remove unused ocr_avail_uhs2. Updates in V10: - Move some definitions of PatchV9[05/23] to PatchV10[20/23]. Updates in V8: - Change return type to void for __sdhci_uhs2_add_host_v4(). - Remove unused variables in __sdhci_uhs2_add_host_v4(). Updates in V7: - __sdhci_add_host() to instead of __sdhci_uhs2_add_host() in sdhci_uhs2_add_host(). - Cancel export state of some functions. Updates in V6: - Add complete_work_fn/thread_irq_fn variables in struct sdhci_host. - Use complete_work_fn/thread_irq_fn variables in sdhci_alloc_host() and sdhci_uhs2_add_host(). - Use sdhci_uhs2_mode() to simplify code in __sdhci_uhs2_remove_host(). --- drivers/mmc/host/sdhci-uhs2.c | 91 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 + 2 files changed, 93 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 6b249eb8395a..d3af620c7b68 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include "sdhci.h" #include "sdhci-uhs2.h" @@ -224,6 +225,96 @@ static void __exit sdhci_uhs2_mod_exit(void) } module_exit(sdhci_uhs2_mod_exit); =20 +/*************************************************************************= ****\ + * + * Device allocation/registration = * + * = * +\*************************************************************************= ****/ + +static void __sdhci_uhs2_add_host_v4(struct sdhci_host *host, u32 caps1) +{ + struct mmc_host *mmc; + u32 max_current_caps2; + + mmc =3D host->mmc; + + /* Support UHS2 */ + if (caps1 & SDHCI_SUPPORT_UHS2) + mmc->caps2 |=3D MMC_CAP2_SD_UHS2; + + max_current_caps2 =3D sdhci_readl(host, SDHCI_MAX_CURRENT_1); + + if ((caps1 & SDHCI_CAN_VDD2_180) && + !max_current_caps2 && + !IS_ERR(mmc->supply.vqmmc2)) { + /* UHS2 - VDD2 */ + int curr =3D regulator_get_current_limit(mmc->supply.vqmmc2); + + if (curr > 0) { + /* convert to SDHCI_MAX_CURRENT format */ + curr =3D curr / 1000; /* convert to mA */ + curr =3D curr / SDHCI_MAX_CURRENT_MULTIPLIER; + curr =3D min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); + max_current_caps2 =3D curr; + } + } + + if (!(caps1 & SDHCI_CAN_VDD2_180)) + mmc->caps2 &=3D ~MMC_CAP2_SD_UHS2; +} + +static void __sdhci_uhs2_remove_host(struct sdhci_host *host, int dead) +{ + if (!mmc_card_uhs2(host->mmc)) + return; + + if (!dead) + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_FULL); +} + +int sdhci_uhs2_add_host(struct sdhci_host *host) +{ + struct mmc_host *mmc =3D host->mmc; + int ret; + + ret =3D sdhci_setup_host(host); + if (ret) + return ret; + + if (host->version >=3D SDHCI_SPEC_400) + __sdhci_uhs2_add_host_v4(host, host->caps1); + + if ((mmc->caps2 & MMC_CAP2_SD_UHS2) && !host->v4_mode) + /* host doesn't want to enable UHS2 support */ + mmc->caps2 &=3D ~MMC_CAP2_SD_UHS2; + + /* LED support not implemented for UHS2 */ + host->quirks |=3D SDHCI_QUIRK_NO_LED; + + ret =3D __sdhci_add_host(host); + if (ret) + goto cleanup; + + return 0; + +cleanup: + if (host->version >=3D SDHCI_SPEC_400) + __sdhci_uhs2_remove_host(host, 0); + + sdhci_cleanup_host(host); + + return ret; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_add_host); + +void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead) +{ + __sdhci_uhs2_remove_host(host, dead); + + sdhci_remove_host(host, dead); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_remove_host); + MODULE_AUTHOR("Intel, Genesys Logic, Linaro"); MODULE_DESCRIPTION("MMC UHS-II Support"); MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 9bd3f610cf8c..0e1866a6bdb6 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -181,5 +181,7 @@ void sdhci_uhs2_dump_regs(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, uns= igned short vdd); void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *c= md); +int sdhci_uhs2_add_host(struct sdhci_host *host); +void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead); =20 #endif /* __SDHCI_UHS2_H */ --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15F6820263D; Fri, 18 Oct 2024 10:54:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248865; cv=none; b=t+Uixbt9GkNs6fzB3nW6JtmMsQut1bPBwBP7HNQwNU8Nefij8K93yAE69Sb+qngTlZSJXGI/P99xnu+CU4jgELJkQfHc6Sw8UsultaivrJFjwrvxd1RATDR7gZaL7fksUFJuZ5vo0dbjvPn3LvjAllp4XJGbh3xjXKp/hu66B9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248865; c=relaxed/simple; bh=EJUupgG1XnQ584S2GhdGx1EZTFaSKXSl/i9dudKjyag=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PNfqRyhLQJJmJDqe+Q2eOsvsPeJJoW1Irg7+AkPHTrF4nAXEtX+EHImB6ffMUu4lz9wjeumr/WMB4eJ8CqHT4UUIQVCl1EWWqWPA2jkgjUlBfQM7Bb5Z0Sm9kLPaozIAV6tDxziAM3aF6Dw3/aHRjN338XyY+9PHb/6sZFkdViE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VS3ITPcK; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VS3ITPcK" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-20e576dbc42so7709415ad.0; Fri, 18 Oct 2024 03:54:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248863; x=1729853663; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ISHPEovLGmEkwcnJ/lpZjrn6I9Dt/a+/WsXG5HfNPq4=; b=VS3ITPcKeN6qpJzP3/eh7IvImTYESwqMUvKWvD/2s5CKGyBFkCB1+w0GCeYzNto02B PSMY/dCoNfnsIzy8fABKs9DvhBy2pbr5sQFHrBy6LiqqaUiMJXzM96OZOX/3+Ok7Aq5B GlmKQezC+Jwb4J69YDWvn+8jehWrZIbEXSGCNpempjEzKE0I1s3CWz0BJcGcWR2LFkmm C8CVL99SVuuZDMGbWhBzQAhpg1VYt+UyFiS2IzLq9GuPnieAeZBe5OPGkd/N+6QOpbUl HDu/DUSE5iDV5MXSMvBuwhieSFC/D1bQHBcSzfawnHsykJP9xuYVBrgVwlKLPmaW78P+ FCcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248863; x=1729853663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ISHPEovLGmEkwcnJ/lpZjrn6I9Dt/a+/WsXG5HfNPq4=; b=ebRViaR2fLhnZcsaH0U20Apk20BlLLsqnKtGTrvzLxMxxBaAXV0CNvFwCaJu2lFSOX pfNZ8PfVHe6NPbOnAAn+7c61L1joxzvMLC7fwgxmK1AtVZtQkzFuPFdreDPJkUBVdnmZ Tok2RY9nNNuOA6inkL6Wr6P1LfkpyZdzhJxglu3SOxYY8MqEpZnrxGYeytrLzwWhhqAP WneUkBda7eDHi+nnzvJ/KmD1qB7AEDIs5HDxlUUWww0BS9LjrybgKO51OjaSTlaGhWCr jztBV75E0MgKQuYKKPrGNA7SJH7MpfpxizuczOT1XKYeoWoLSF3NwF+BlsjgOkmHipnc yghg== X-Forwarded-Encrypted: i=1; AJvYcCWUrsgfR1Ricp7hU68os81IliyZqz0De4BXY2glbeEBD9gxuGLQsLdfGdeZhLSw9cuyb4EsylmKWPbR0mE=@vger.kernel.org X-Gm-Message-State: AOJu0YykEYjxvi8uOcanZeubix1jqPL9rUB7dYo7XPnyw88Nf313g7xz hwT+eYAVLO2bL+9X8/bJlNa7m/FkC2uO3KBPhVeTuARKKx88wRuX X-Google-Smtp-Source: AGHT+IHhT0JaUTsoQVhzk/VSIGQfPK+W4nKIYYb9SgDPF2lStYGuxeWlfMlHQo8f6Mj7p6vzMjCefQ== X-Received: by 2002:a17:903:990:b0:20c:9285:e941 with SMTP id d9443c01a7336-20e5a904f15mr25692075ad.27.1729248863437; Fri, 18 Oct 2024 03:54:23 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:23 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 09/16] mmc: sdhci-uhs2: add set_ios() Date: Fri, 18 Oct 2024 18:53:26 +0800 Message-Id: <20241018105333.4569-10-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This is a sdhci version of mmc's set_ios operation. This is used to handle basic IO bus setting. It covers both UHS-I and UHS-II. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V22: - Adjust the patch order from v21 patch#14 to v22 patch#15 and add necessary code to avoid defined but not used warnings. Updates in V14: - Use mmc_card_uhs2() to stead sdhci_uhs2_mode() in the sdhci_uhs2_set_ios(). Updates in V13: - Add judgment condition for power mode in the __sdhci_uhs2_set_ios(). - Modify comment message. Updates in V9: - Simplity the turning_on_clk in sdhci_set_ios(). Updates in V8: - Add the judgment formula for MMC_TIMING_SPEED_A_HD, MMC_TIMING_SPEED_B and MMC_TIMING_SPEED_B_HD in __sdhci_uhs2_set_ios(). - Add the switch case for MMC_TIMING_SPEED_A_HD, MMC_TIMING_SPEED_B and MMC_TIMING_SPEED_B_HD in sdhci_get_preset_value(). - mmc_opt_regulator_set_ocr() to instead of mmc_regulator_set_ocr() in sdhci_uhs2_set_ios(). Updates in V7: - Remove unnecessary functions. Updates in V6: - Modify return value in some functions. - Remove unnecessary functions. --- drivers/mmc/host/sdhci-uhs2.c | 128 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 1 + drivers/mmc/host/sdhci.c | 55 +++++++++------ drivers/mmc/host/sdhci.h | 2 + 4 files changed, 165 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index d3af620c7b68..ee46dac891e5 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -208,12 +208,136 @@ void sdhci_uhs2_set_timeout(struct sdhci_host *host,= struct mmc_command *cmd) } EXPORT_SYMBOL_GPL(sdhci_uhs2_set_timeout); =20 +/** + * sdhci_uhs2_clear_set_irqs - set Error Interrupt Status Enable register + * @host: SDHCI host + * @clear: bit-wise clear mask + * @set: bit-wise set mask + * + * Set/unset bits in UHS-II Error Interrupt Status Enable register + */ +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) +{ + u32 ier; + + ier =3D sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE); + ier &=3D ~clear; + ier |=3D set; + sdhci_writel(host, ier, SDHCI_UHS2_INT_STATUS_ENABLE); + sdhci_writel(host, ier, SDHCI_UHS2_INT_SIGNAL_ENABLE); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_clear_set_irqs); + +static void __sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + u8 cmd_res, dead_lock; + u16 ctrl_2; + + /* UHS2 Timeout Control */ + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + + /* change to use calculate value */ + cmd_res |=3D FIELD_PREP(SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK, dead_lock); + + sdhci_uhs2_clear_set_irqs(host, + SDHCI_UHS2_INT_CMD_TIMEOUT | + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT, + 0); + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); + sdhci_uhs2_clear_set_irqs(host, 0, + SDHCI_UHS2_INT_CMD_TIMEOUT | + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT); + + /* UHS2 timing. Note, UHS2 timing is disabled when powering off */ + ctrl_2 =3D sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ios->power_mode !=3D MMC_POWER_OFF && + (ios->timing =3D=3D MMC_TIMING_UHS2_SPEED_A || + ios->timing =3D=3D MMC_TIMING_UHS2_SPEED_A_HD || + ios->timing =3D=3D MMC_TIMING_UHS2_SPEED_B || + ios->timing =3D=3D MMC_TIMING_UHS2_SPEED_B_HD)) + ctrl_2 |=3D SDHCI_CTRL_UHS2 | SDHCI_CTRL_UHS2_ENABLE; + else + ctrl_2 &=3D ~(SDHCI_CTRL_UHS2 | SDHCI_CTRL_UHS2_ENABLE); + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + host->timing =3D ios->timing; + + if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) + sdhci_enable_preset_value(host, true); + + if (host->ops->set_power) + host->ops->set_power(host, ios->power_mode, ios->vdd); + else + sdhci_uhs2_set_power(host, ios->power_mode, ios->vdd); + + sdhci_set_clock(host, host->clock); +} + +static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + + pr_debug("%s: clock %uHz powermode %u Vdd %u timing %u\n", + mmc_hostname(mmc), ios->clock, ios->power_mode, ios->vdd, ios->timing); + + if (!mmc_card_uhs2(mmc)) { + sdhci_set_ios(mmc, ios); + return 0; + } + + if (ios->power_mode =3D=3D MMC_POWER_UNDEFINED) + return 0; + + if (host->flags & SDHCI_DEVICE_DEAD) { + if (ios->power_mode =3D=3D MMC_POWER_OFF) { + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + mmc_regulator_set_vqmmc2(mmc, ios); + } + return -1; + } + + sdhci_set_ios_common(mmc, ios); + + __sdhci_uhs2_set_ios(mmc, ios); + + return 0; +} + +static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation= op) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct mmc_ios *ios =3D &mmc->ios; + int err =3D 0; + + DBG("Begin uhs2 control, act %d.\n", op); + + switch (op) { + case UHS2_SET_IOS: + err =3D sdhci_uhs2_set_ios(mmc, ios); + break; + default: + pr_err("%s: input sd uhs2 operation %d is wrong!\n", + mmc_hostname(host->mmc), op); + err =3D -EIO; + break; + } + + return err; +} + /*************************************************************************= ****\ * = * * Driver init/exit = * * = * \*************************************************************************= ****/ =20 +static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) +{ + host->mmc_host_ops.uhs2_control =3D sdhci_uhs2_control; + + return 0; +} + static int __init sdhci_uhs2_mod_init(void) { return 0; @@ -288,6 +412,10 @@ int sdhci_uhs2_add_host(struct sdhci_host *host) /* host doesn't want to enable UHS2 support */ mmc->caps2 &=3D ~MMC_CAP2_SD_UHS2; =20 + /* overwrite ops */ + if (mmc->caps2 & MMC_CAP2_SD_UHS2) + sdhci_uhs2_host_ops_init(host); + /* LED support not implemented for UHS2 */ host->quirks |=3D SDHCI_QUIRK_NO_LED; =20 diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 0e1866a6bdb6..14713a31f8a5 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -183,5 +183,6 @@ void sdhci_uhs2_set_power(struct sdhci_host *host, unsi= gned char mode, unsigned void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *c= md); int sdhci_uhs2_add_host(struct sdhci_host *host); void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead); +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set= ); =20 #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 366c3d30dba6..63fa1714930a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -47,8 +47,6 @@ static unsigned int debug_quirks =3D 0; static unsigned int debug_quirks2; =20 -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable= ); - static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command= *cmd); =20 void sdhci_dumpregs(struct sdhci_host *host) @@ -1877,6 +1875,12 @@ static u16 sdhci_get_preset_value(struct sdhci_host = *host) case MMC_TIMING_MMC_HS400: preset =3D sdhci_readw(host, SDHCI_PRESET_FOR_HS400); break; + case MMC_TIMING_UHS2_SPEED_A: + case MMC_TIMING_UHS2_SPEED_A_HD: + case MMC_TIMING_UHS2_SPEED_B: + case MMC_TIMING_UHS2_SPEED_B_HD: + preset =3D sdhci_readw(host, SDHCI_PRESET_FOR_UHS2); + break; default: pr_warn("%s: Invalid UHS-I mode selected\n", mmc_hostname(host->mmc)); @@ -2323,24 +2327,9 @@ static bool sdhci_presetable_values_change(struct sd= hci_host *host, struct mmc_i (sdhci_preset_needed(host, ios->timing) || host->drv_type !=3D ios= ->drv_type); } =20 -void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios) { struct sdhci_host *host =3D mmc_priv(mmc); - bool reinit_uhs =3D host->reinit_uhs; - bool turning_on_clk =3D false; - u8 ctrl; - - host->reinit_uhs =3D false; - - if (ios->power_mode =3D=3D MMC_POWER_UNDEFINED) - return; - - if (host->flags & SDHCI_DEVICE_DEAD) { - if (!IS_ERR(mmc->supply.vmmc) && - ios->power_mode =3D=3D MMC_POWER_OFF) - mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); - return; - } =20 /* * Reset the chip on each power off. @@ -2357,8 +2346,6 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_i= os *ios) sdhci_enable_preset_value(host, false); =20 if (!ios->clock || ios->clock !=3D host->clock) { - turning_on_clk =3D ios->clock && !host->clock; - host->ops->set_clock(host, ios->clock); host->clock =3D ios->clock; =20 @@ -2374,6 +2361,31 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_= ios *ios) mmc->max_busy_timeout /=3D host->timeout_clk; } } +} +EXPORT_SYMBOL_GPL(sdhci_set_ios_common); + +void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + bool reinit_uhs =3D host->reinit_uhs; + bool turning_on_clk; + u8 ctrl; + + host->reinit_uhs =3D false; + + if (ios->power_mode =3D=3D MMC_POWER_UNDEFINED) + return; + + if (host->flags & SDHCI_DEVICE_DEAD) { + if (!IS_ERR(mmc->supply.vmmc) && + ios->power_mode =3D=3D MMC_POWER_OFF) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + return; + } + + turning_on_clk =3D ios->clock !=3D host->clock && ios->clock && !host->cl= ock; + + sdhci_set_ios_common(mmc, ios); =20 if (host->ops->set_power) host->ops->set_power(host, ios->power_mode, ios->vdd); @@ -2942,7 +2954,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 op= code) } EXPORT_SYMBOL_GPL(sdhci_execute_tuning); =20 -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) { /* Host Controller v3.00 defines preset value registers */ if (host->version < SDHCI_SPEC_300) @@ -2970,6 +2982,7 @@ static void sdhci_enable_preset_value(struct sdhci_ho= st *host, bool enable) host->preset_enabled =3D enable; } } +EXPORT_SYMBOL_GPL(sdhci_enable_preset_value); =20 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0f78708d0c70..5c66927210bd 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -848,6 +848,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode); +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); +void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios); void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); --=20 2.25.1 From nobody Tue Nov 26 11:53:54 2024 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84263205AA2; Fri, 18 Oct 2024 10:54:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248870; cv=none; b=cGO0+2D503eU9OKfOYfhbuShobiVp2KmYdTM/o1LY56mrENgCcbbNA4NNdjOBiWvVdlyRmKhG90Ecwff46gLUiRHr3OcYIxayJYzary7MORIrZFi4+hYr0MRzHCPJ7hzQ00dB7nSneOcLngYBovffbobiP02OXCoMnki7E6/DSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248870; c=relaxed/simple; bh=Yf9c/+P80QvztzSDSZc5+mOLmfL0EsrfDRKcNyiiles=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VF/dFVcTOnYwsRWHYJW/wiS1v9UClM+ctHlhPv932Rc2UrJmtUYScKznFRaD8e3OAZfHEXGv53aE6Y2yp25rGeMKWncdYwD2sdhQN+vHaVtGua/sIdUaSHMuMGQucnSRz+vBShl3fQ57KaviTfouNMwfHKp3ZhhjEYe5Crih9Rs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=O459pB3F; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O459pB3F" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-20e6981ca77so1974925ad.2; Fri, 18 Oct 2024 03:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248868; x=1729853668; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MRafvWR7zGbZF3TAjHo6lxtfuVouUGY2HW+1bCf77G0=; b=O459pB3FqM3iIwEastGUgn4tJ7cMhvO3LVbg3hB1ZcPJDEySavHH2dy8rynjr+j5p8 Zo/KSRvIJg4MaFvEST5TyqQ5rCQoX1dqRVhcpLQFEb4WLBemUU14Ti/GobPAWWdJpuY8 kglDOLXfRr/NQG364Td3hD9rE2Mdj43u5rfGCLtk2tq+A1rz76lfXWLaqDtoiZk9UZ8B QiWUBCHfR78EYx0/6tYunovb4jU/gt7fxomd9hf3HY57lhzC0wZqKPTVLZ3rGK1jsLAP 7QV7KMqvyI69pPzKfYM9UC0S3mfOcDvr+WNYRmY7ApNWU+QFTpafhuUB41uqWAMWC/AN hkkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248868; x=1729853668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MRafvWR7zGbZF3TAjHo6lxtfuVouUGY2HW+1bCf77G0=; b=j3QxGsrGk7gLhmEo0+bteziNPgaSkyZO1J67qYtSRrgXuDd5YxXIE15HdEdJW/tkMv UqawLI6LR7pPkp879DiyV/PHiPKJre680gEkeBI13valj2uwnslti6uzGZzUh2U4dltG FWk9C1cWJJPViA5gs45rXL1qVcxgZSY38Mpj4CDyjfDroL3llbNAj8wqaGS9e4c6E9hf vjak8F8hlWyUFwvVLpnuYSw4h70WbWBjhuOf7m5vSnNjvvdJeyuFb3wBqZR+kIGOPYhy L2KUkCvlO7O68Bi03tEHuZ8U2aW7c8wPdcvu8BmWPQFXm17/QFRLqTlFz/bsztKoLXs3 hx3Q== X-Forwarded-Encrypted: i=1; AJvYcCVPtsUfVIl3ooiP+NW0VdTlVtR5R/m34EKuu9qq4MIvS96OMA7wQZNRA8UhAP3MQQZoIIYNY6nLUfu3pl4=@vger.kernel.org X-Gm-Message-State: AOJu0Yyj9tPHf//kICoxVTteyXhI5yWfALqK3a3hSOm2u7Z/N6ojksyK 3L4DVGUWtwGMnQfJ/02or/XzKKVWAhIcx5AfKRAetaAAud8vJHEN X-Google-Smtp-Source: AGHT+IH0AefCC9lLf+G5P5wfzLATcrnRsow06e2zkBRImSQlBN5NMg1eLhUrvqgvFoUWxHU67joZug== X-Received: by 2002:a17:903:94f:b0:20c:ea04:a186 with SMTP id d9443c01a7336-20e5a914892mr27969905ad.48.1729248867734; Fri, 18 Oct 2024 03:54:27 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:27 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 10/16] mmc: sdhci-uhs2: add related functions to initialize the interface Date: Fri, 18 Oct 2024 18:53:27 +0800 Message-Id: <20241018105333.4569-11-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih UHS-II interface (related registers) will be initialized here. The operations include mmc's uhs2_set_reg operations, mmc's uhs2_detect_init operations, uhs2_[enable|disable]_clk operations. After detected the UHS-II interface, the host's UHS-II capabilities will be= set up here and interrupts will also be enabled. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V22: - Adjust the patch order from v21 patch#15 to v22 patch#16 and remove unnecessary code to avoid defined but not used warnings. - Modify commit message. Updates in V15: - Resolve merge conflicts and reduce unnecessary line breaks. Updates in V13: - Merge Patch#15, Patch#16 and Patch#17 of v12 version into Patch#15 in v1= 3 version. - Use definitions to simplify code. - Modify comment message. --- drivers/mmc/host/sdhci-uhs2.c | 204 ++++++++++++++++++++++++++++++++++ 1 file changed, 204 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index ee46dac891e5..94e041520a54 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -26,6 +26,9 @@ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) =20 #define UHS2_RESET_TIMEOUT_100MS 100000 +#define UHS2_CHECK_DORMANT_TIMEOUT_100MS 100000 +#define UHS2_INTERFACE_DETECT_TIMEOUT_100MS 100000 +#define UHS2_LANE_SYNC_TIMEOUT_150MS 150000 =20 void sdhci_uhs2_dump_regs(struct sdhci_host *host) { @@ -303,6 +306,186 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, s= truct mmc_ios *ios) return 0; } =20 +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) +{ + u32 val; + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), + 100, UHS2_INTERFACE_DETECT_TIMEOUT_100MS, true, + host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: not detect UHS2 interface in 100ms.\n", mmc_hostname(host->= mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + /* Enable UHS2 error interrupts */ + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_= MASK); + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), + 100, UHS2_LANE_SYNC_TIMEOUT_150MS, true, host, SDHCI_PRESENT_STAT= E)) { + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", + mmc_hostname(host->mmc)); + return 0; +} + +static int sdhci_uhs2_init(struct sdhci_host *host) +{ + u16 caps_ptr =3D 0; + u32 caps_gen =3D 0; + u32 caps_phy =3D 0; + u32 caps_tran[2] =3D {0, 0}; + struct mmc_host *mmc =3D host->mmc; + + caps_ptr =3D sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { + pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n", + mmc_hostname(mmc), caps_ptr); + return -ENODEV; + } + caps_gen =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); + caps_phy =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); + caps_tran[0] =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET= ); + caps_tran[1] =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFS= ET); + + /* General Caps */ + mmc->uhs2_caps.dap =3D caps_gen & SDHCI_UHS2_CAPS_DAP_MASK; + mmc->uhs2_caps.gap =3D FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen); + mmc->uhs2_caps.n_lanes =3D FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen); + mmc->uhs2_caps.addr64 =3D (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0; + mmc->uhs2_caps.card_type =3D FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, cap= s_gen); + + /* PHY Caps */ + mmc->uhs2_caps.phy_rev =3D caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK; + mmc->uhs2_caps.speed_range =3D FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, = caps_phy); + mmc->uhs2_caps.n_lss_sync =3D FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MAS= K, caps_phy); + mmc->uhs2_caps.n_lss_dir =3D FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK= , caps_phy); + if (mmc->uhs2_caps.n_lss_sync =3D=3D 0) + mmc->uhs2_caps.n_lss_sync =3D 16 << 2; + else + mmc->uhs2_caps.n_lss_sync <<=3D 2; + if (mmc->uhs2_caps.n_lss_dir =3D=3D 0) + mmc->uhs2_caps.n_lss_dir =3D 16 << 3; + else + mmc->uhs2_caps.n_lss_dir <<=3D 3; + + /* LINK/TRAN Caps */ + mmc->uhs2_caps.link_rev =3D caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_= MASK; + mmc->uhs2_caps.n_fcu =3D FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_= tran[0]); + if (mmc->uhs2_caps.n_fcu =3D=3D 0) + mmc->uhs2_caps.n_fcu =3D 256; + mmc->uhs2_caps.host_type =3D FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MAS= K, caps_tran[0]); + mmc->uhs2_caps.maxblk_len =3D FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK= , caps_tran[0]); + mmc->uhs2_caps.n_data_gap =3D caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DAT= A_GAP_MASK; + + return 0; +} + +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + + DBG("Begin do uhs2 detect init.\n"); + + if (sdhci_uhs2_interface_detect(host)) { + pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc)); + return -EIO; + } + + if (sdhci_uhs2_init(host)) { + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); + return -EIO; + } + + /* Init complete, do soft reset and enable UHS2 error irqs. */ + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_= MASK); + /* + * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared + * by SDHCI_UHS2_SW_RESET_SD + */ + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + + return 0; +} + +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + u16 clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk &=3D ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + return 0; +} + +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + u16 clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + int timeout_us =3D 20000; /* 20ms */ + u32 val; + + clk |=3D SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + if (read_poll_timeout(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)= ); + sdhci_dumpregs(host); + return -EIO; + } + return 0; +} + +static void sdhci_uhs2_set_config(struct sdhci_host *host) +{ + u32 value; + u16 sdhci_uhs2_set_ptr =3D sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR); + u16 sdhci_uhs2_gen_set_reg =3D sdhci_uhs2_set_ptr; + u16 sdhci_uhs2_phy_set_reg =3D sdhci_uhs2_set_ptr + 4; + u16 sdhci_uhs2_tran_set_reg =3D sdhci_uhs2_set_ptr + 8; + u16 sdhci_uhs2_tran_set_1_reg =3D sdhci_uhs2_set_ptr + 12; + + /* Set Gen Settings */ + value =3D FIELD_PREP(SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK, host->mmc->uhs= 2_caps.n_lanes_set); + sdhci_writel(host, value, sdhci_uhs2_gen_set_reg); + + /* Set PHY Settings */ + value =3D FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_DIR_MASK, host->mmc->uhs2_caps.= n_lss_dir_set) | + FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_SYN_MASK, host->mmc->uhs2_caps.n_lss_syn= c_set); + if (host->mmc->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_B || + host->mmc->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_B_HD) + value |=3D SDHCI_UHS2_PHY_SET_SPEED_B; + sdhci_writel(host, value, sdhci_uhs2_phy_set_reg); + + /* Set LINK-TRAN Settings */ + value =3D FIELD_PREP(SDHCI_UHS2_TRAN_RETRY_CNT_MASK, host->mmc->uhs2_caps= .max_retry_set) | + FIELD_PREP(SDHCI_UHS2_TRAN_N_FCU_MASK, host->mmc->uhs2_caps.n_fcu_set); + sdhci_writel(host, value, sdhci_uhs2_tran_set_reg); + sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, sdhci_uhs2_tran_s= et_1_reg); +} + +static int sdhci_uhs2_check_dormant(struct sdhci_host *host) +{ + u32 val; + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IN_DORMANT_STAT= E), + 100, UHS2_CHECK_DORMANT_TIMEOUT_100MS, true, host, + SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + return 0; +} + static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation= op) { struct sdhci_host *host =3D mmc_priv(mmc); @@ -312,6 +495,27 @@ static int sdhci_uhs2_control(struct mmc_host *mmc, en= um sd_uhs2_operation op) DBG("Begin uhs2 control, act %d.\n", op); =20 switch (op) { + case UHS2_PHY_INIT: + err =3D sdhci_uhs2_do_detect_init(mmc); + break; + case UHS2_SET_CONFIG: + sdhci_uhs2_set_config(host); + break; + case UHS2_ENABLE_INT: + sdhci_uhs2_clear_set_irqs(host, 0, SDHCI_INT_CARD_INT); + break; + case UHS2_DISABLE_INT: + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_CARD_INT, 0); + break; + case UHS2_CHECK_DORMANT: + err =3D sdhci_uhs2_check_dormant(host); + break; + case UHS2_DISABLE_CLK: + err =3D sdhci_uhs2_disable_clk(mmc); + break; + case UHS2_ENABLE_CLK: + err =3D sdhci_uhs2_enable_clk(mmc); + break; case UHS2_SET_IOS: err =3D sdhci_uhs2_set_ios(mmc, ios); break; --=20 2.25.1 From nobody Tue Nov 26 11:53:55 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C9C2036F1; Fri, 18 Oct 2024 10:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248875; cv=none; b=ZBYl2a1wliaQxC7pEgYOudjh+c5qITkSKFHdj8e2UteC+FohkxHGUUjeqq3GfPjo2A9uUriF2tllgQk8ZgEUvuZ7lMlk/VRax6U69GtWt9r3ccNEqfTIGwpI92LS85d017fn7KRSO11xiBXa+Qr0Mxj8A/eSgjpRERgvYIHNmNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248875; c=relaxed/simple; bh=B+Wa7oOAmDVkINnlgYIgH9NByleuifN/m1Jcx69l3vo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A17nx4UMQuncvhiugU/1QiWoZMRXZrn0xynkMZbieIovwqAR4eIS+14dOMZGOj0aHGAPc+DWFUF2t9/8HfBDlCu9GKjDBq19xn4/KBGu7DIuMSjAao4bOp96oygivA9Q9lNAijGSOqae0igj3X0cwYNUgNLdH9okW2AXJB2GoPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ctZ/HrrU; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ctZ/HrrU" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-20cb47387ceso16423905ad.1; Fri, 18 Oct 2024 03:54:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248872; x=1729853672; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2TktPzLzjI8Xc4Q60euNFMPr6whdPIGlEZYibsnuzdI=; b=ctZ/HrrUCjqPnuEBUGL1hh3DKaREE55VqWOZm4F9YJa3HAR1GEHf+xwlnJniLwH6rx 2SRreK8mvitgHlP68X+WVFqaLEIpTlEXJaz4ZnvENjLH7rmdoDUKY2H8OZeysXXLmF84 jGFghEM2vUpROHIPRrbY06VAGzgy5Mf6Ng45K2Udk2Ceh/tEXp13d2ECvsWo+7RjGRsJ 8a3EMFflou3II5JOCTKdKXZXp3tXZCVZ7OeBDyklYE/xCfy4snADVqTls2rdxuwWdkC/ KNJ0fuemkB9KF9owMNsJ4mJLcQx/G3qPGb6c9OTgNR/jsmukJqBsmJTfB6Zbwb7oGPik qwGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248872; x=1729853672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2TktPzLzjI8Xc4Q60euNFMPr6whdPIGlEZYibsnuzdI=; b=wdYFeqDP83Xmqq3QvjL5MqWXwE2p+ra4eAyn1Ozwa8lUwKoH12e/tWiAy92Vhj7Ie7 HtCAst1d7ZWhvtMuLCDva3UWQRw8zughvvPh7TjRZw+zIm9IBWbGYFevzrI0QxUT+slO JomE2cyq389mqtx0DySon+c/jg1jIii7ktxafqvvA3z2MTtVwSuJF9Jyoy+mTX1aWwVR J4BYWe4Sy5HAxAk3n59EsNuxtsya/PUDGGhyEC8Loj9/Cx8L7ub4k+1qU89CmEGQPk+f mCYVK6augWvu1c7BEy2YnTazzcug3K5ehemXKVBEzNko6V8e8iTtp0jqYymjB5jv/pHT zGag== X-Forwarded-Encrypted: i=1; AJvYcCVbfS8znZuHo/WVo58YA5YLGdi56FHeGaI0zxrgo+0J1BFt1dZpBt4Q+lx8g4lrcbsynju5S/c1lvdDtoE=@vger.kernel.org X-Gm-Message-State: AOJu0YyyxhwLcE+GyT8bpYbr3VNbNEA/wm77VOwkhsclGloGc1xzWkWj keEnTyqgBCsVHvIkgXC/Y0Q4cyBXpGLp7bIJNkc+gnweNVpzQbdA X-Google-Smtp-Source: AGHT+IFkiNZwxJXzQJJId0On8nTbY9suBA/o1/8Z3XzJuhSR6cqvoP3Mu2aQakeg/DfFjcsYU/jwzA== X-Received: by 2002:a17:903:2907:b0:20e:57c8:6ab3 with SMTP id d9443c01a7336-20e5a71b492mr23286425ad.4.1729248872184; Fri, 18 Oct 2024 03:54:32 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:31 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 11/16] mmc: sdhci-uhs2: add irq() and others Date: Fri, 18 Oct 2024 18:53:28 +0800 Message-Id: <20241018105333.4569-12-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This is a UHS-II version of sdhci's request() operation. It handles UHS-II related command interrupts and errors. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V22: - Remove unnecessary code to avoid defined but not used warnings. Updates in V19: - Corrected sdhci_uhs2_reset() parameter errors in the sdhci_uhs2_request_done(). Updates in V18: - Modify the judgment condition in the sdhci_uhs2_reset_cmd_data() and replace it from mmc_card_uhs2() to host->mmc->uhs2_sd_tran flag. Updates in V17: - Add sdhci_uhs2_reset_cmd_data() and sdhci_uhs2_needs_reset() to resolve the data error or cmd error. Updates in V14: - Use mmc_card_uhs2() to stead sdhci_uhs2_mode() in the sdhci_uhs2_complete_work(), sdhci_uhs2_irq() and sdhci_uhs2_thread_irq(). Updates in V13: - Re-order function to avoid declaration. - Remove unnecessary definitions. Updates in V9: - Cancel export state of sdhci_set_mrq_done() function. Updates in V8: - Forward declare struct mmc_request in sdhci_uhs2.h. - Remove forward declaration of sdhci_send_command(). - Use mmc_dev() to simplify code in sdhci_request_done_dma(). Updates in V7: - Remove unnecessary functions. - Use sdhci_uhs2_mode() to simplify code in sdhci_uhs2_irq(). - Modify descriptions in sdhci_uhs2_irq(). - Cancel export state of some functions. Updates in V6: - Remove unnecessary functions. - Add sdhci_uhs2_mode() in sdhci_uhs2_complete_work(). - Add sdhci_uhs2_mode() in sdhci_uhs2_thread_irq(). --- drivers/mmc/host/sdhci-uhs2.c | 227 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 + drivers/mmc/host/sdhci.c | 109 +++++++++------- drivers/mmc/host/sdhci.h | 8 ++ 4 files changed, 298 insertions(+), 48 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 94e041520a54..76f1af8b0486 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -98,6 +98,19 @@ void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) } EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); =20 +static void sdhci_uhs2_reset_cmd_data(struct sdhci_host *host) +{ + sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + + if (host->mmc->uhs2_sd_tran) { + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR= _MASK); + } +} + void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, uns= igned short vdd) { struct mmc_host *mmc =3D host->mmc; @@ -529,6 +542,217 @@ static int sdhci_uhs2_control(struct mmc_host *mmc, e= num sd_uhs2_operation op) return err; } =20 +/*************************************************************************= ****\ + * = * + * Request done = * + * = * +\*************************************************************************= ****/ + +static bool sdhci_uhs2_needs_reset(struct sdhci_host *host, struct mmc_req= uest *mrq) +{ + return sdhci_needs_reset(host, mrq) || + (!(host->flags & SDHCI_DEVICE_DEAD) && mrq->data && mrq->data->err= or); +} + +static bool sdhci_uhs2_request_done(struct sdhci_host *host) +{ + unsigned long flags; + struct mmc_request *mrq; + int i; + + spin_lock_irqsave(&host->lock, flags); + + for (i =3D 0; i < SDHCI_MAX_MRQS; i++) { + mrq =3D host->mrqs_done[i]; + if (mrq) + break; + } + + if (!mrq) { + spin_unlock_irqrestore(&host->lock, flags); + return true; + } + + /* + * Always unmap the data buffers if they were mapped by + * sdhci_prepare_data() whenever we finish with a request. + * This avoids leaking DMA mappings on error. + */ + if (host->flags & SDHCI_REQ_USE_DMA) + sdhci_request_done_dma(host, mrq); + + /* + * The controller needs a reset of internal state machines + * upon error conditions. + */ + if (sdhci_uhs2_needs_reset(host, mrq)) { + /* + * Do not finish until command and data lines are available for + * reset. Note there can only be one other mrq, so it cannot + * also be in mrqs_done, otherwise host->cmd and host->data_cmd + * would both be null. + */ + if (host->cmd || host->data_cmd) { + spin_unlock_irqrestore(&host->lock, flags); + return true; + } + + if (mrq->cmd->error || mrq->data->error) + sdhci_uhs2_reset_cmd_data(host); + else + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + host->pending_reset =3D false; + } + + host->mrqs_done[i] =3D NULL; + + spin_unlock_irqrestore(&host->lock, flags); + + if (host->ops->request_done) + host->ops->request_done(host, mrq); + else + mmc_request_done(host->mmc, mrq); + + return false; +} + +static void sdhci_uhs2_complete_work(struct work_struct *work) +{ + struct sdhci_host *host =3D container_of(work, struct sdhci_host, + complete_work); + + if (!mmc_card_uhs2(host->mmc)) { + sdhci_complete_work(work); + return; + } + + while (!sdhci_uhs2_request_done(host)) + ; +} + +/*************************************************************************= ****\ + * = * + * Interrupt handling = * + * = * +\*************************************************************************= ****/ + +static void __sdhci_uhs2_irq(struct sdhci_host *host, u32 uhs2mask) +{ + DBG("*** %s got UHS2 error interrupt: 0x%08x\n", + mmc_hostname(host->mmc), uhs2mask); + + if (uhs2mask & SDHCI_UHS2_INT_CMD_ERR_MASK) { + if (!host->cmd) { + pr_err("%s: Got cmd interrupt 0x%08x but no cmd.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + host->cmd->error =3D -EILSEQ; + if (uhs2mask & SDHCI_UHS2_INT_CMD_TIMEOUT) + host->cmd->error =3D -ETIMEDOUT; + } + + if (uhs2mask & SDHCI_UHS2_INT_DATA_ERR_MASK) { + if (!host->data) { + pr_err("%s: Got data interrupt 0x%08x but no data.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + + if (uhs2mask & SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) { + pr_err("%s: Got deadlock timeout interrupt 0x%08x\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + host->data->error =3D -ETIMEDOUT; + } else if (uhs2mask & SDHCI_UHS2_INT_ADMA_ERROR) { + pr_err("%s: ADMA error =3D 0x %x\n", + mmc_hostname(host->mmc), + sdhci_readb(host, SDHCI_ADMA_ERROR)); + host->data->error =3D -EIO; + } else { + host->data->error =3D -EILSEQ; + } + } +} + +u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask) +{ + u32 mask =3D intmask, uhs2mask; + + if (!mmc_card_uhs2(host->mmc)) + goto out; + + if (intmask & SDHCI_INT_ERROR) { + uhs2mask =3D sdhci_readl(host, SDHCI_UHS2_INT_STATUS); + if (!(uhs2mask & SDHCI_UHS2_INT_ERROR_MASK)) + goto cmd_irq; + + /* Clear error interrupts */ + sdhci_writel(host, uhs2mask & SDHCI_UHS2_INT_ERROR_MASK, + SDHCI_UHS2_INT_STATUS); + + /* Handle error interrupts */ + __sdhci_uhs2_irq(host, uhs2mask); + + /* Caller, sdhci_irq(), doesn't have to care about UHS-2 errors */ + intmask &=3D ~SDHCI_INT_ERROR; + mask &=3D SDHCI_INT_ERROR; + } + +cmd_irq: + if (intmask & SDHCI_INT_CMD_MASK) { + /* Clear command interrupt */ + sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); + + /* Caller, sdhci_irq(), doesn't have to care about UHS-2 commands */ + intmask &=3D ~SDHCI_INT_CMD_MASK; + mask &=3D SDHCI_INT_CMD_MASK; + } + + /* Clear already-handled interrupts. */ + sdhci_writel(host, mask, SDHCI_INT_STATUS); + +out: + return intmask; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_irq); + +static irqreturn_t sdhci_uhs2_thread_irq(int irq, void *dev_id) +{ + struct sdhci_host *host =3D dev_id; + struct mmc_command *cmd; + unsigned long flags; + u32 isr; + + if (!mmc_card_uhs2(host->mmc)) + return sdhci_thread_irq(irq, dev_id); + + while (!sdhci_uhs2_request_done(host)) + ; + + spin_lock_irqsave(&host->lock, flags); + + isr =3D host->thread_isr; + host->thread_isr =3D 0; + + cmd =3D host->deferred_cmd; + + spin_unlock_irqrestore(&host->lock, flags); + + if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + struct mmc_host *mmc =3D host->mmc; + + mmc->ops->card_event(mmc); + mmc_detect_change(mmc, msecs_to_jiffies(200)); + } + + return IRQ_HANDLED; +} + /*************************************************************************= ****\ * = * * Driver init/exit = * @@ -620,6 +844,9 @@ int sdhci_uhs2_add_host(struct sdhci_host *host) if (mmc->caps2 & MMC_CAP2_SD_UHS2) sdhci_uhs2_host_ops_init(host); =20 + host->complete_work_fn =3D sdhci_uhs2_complete_work; + host->thread_irq_fn =3D sdhci_uhs2_thread_irq; + /* LED support not implemented for UHS2 */ host->quirks |=3D SDHCI_QUIRK_NO_LED; =20 diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 14713a31f8a5..3205adaecfa4 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -176,6 +176,7 @@ =20 struct sdhci_host; struct mmc_command; +struct mmc_request; =20 void sdhci_uhs2_dump_regs(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); @@ -184,5 +185,6 @@ void sdhci_uhs2_set_timeout(struct sdhci_host *host, st= ruct mmc_command *cmd); int sdhci_uhs2_add_host(struct sdhci_host *host); void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead); void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set= ); +u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask); =20 #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 63fa1714930a..871b4fe2a1b2 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -234,7 +234,7 @@ void sdhci_reset(struct sdhci_host *host, u8 mask) } EXPORT_SYMBOL_GPL(sdhci_reset); =20 -static bool sdhci_do_reset(struct sdhci_host *host, u8 mask) +bool sdhci_do_reset(struct sdhci_host *host, u8 mask) { if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { struct mmc_host *mmc =3D host->mmc; @@ -247,6 +247,7 @@ static bool sdhci_do_reset(struct sdhci_host *host, u8 = mask) =20 return true; } +EXPORT_SYMBOL_GPL(sdhci_do_reset); =20 static void sdhci_reset_for_all(struct sdhci_host *host) { @@ -1489,7 +1490,7 @@ static void sdhci_set_transfer_mode(struct sdhci_host= *host, sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); } =20 -static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request = *mrq) +bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) { return (!(host->flags & SDHCI_DEVICE_DEAD) && ((mrq->cmd && mrq->cmd->error) || @@ -1497,6 +1498,7 @@ static bool sdhci_needs_reset(struct sdhci_host *host= , struct mmc_request *mrq) (mrq->data && mrq->data->stop && mrq->data->stop->error) || (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); } +EXPORT_SYMBOL_GPL(sdhci_needs_reset); =20 static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request= *mrq) { @@ -3076,6 +3078,53 @@ static const struct mmc_host_ops sdhci_ops =3D { * = * \*************************************************************************= ****/ =20 +void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *m= rq) +{ + struct mmc_data *data =3D mrq->data; + + if (data && data->host_cookie =3D=3D COOKIE_MAPPED) { + if (host->bounce_buffer) { + /* + * On reads, copy the bounced data into the + * sglist + */ + if (mmc_get_dma_dir(data) =3D=3D DMA_FROM_DEVICE) { + unsigned int length =3D data->bytes_xfered; + + if (length > host->bounce_buffer_size) { + pr_err("%s: bounce buffer is %u bytes but DMA claims to have transfer= red %u bytes\n", + mmc_hostname(host->mmc), + host->bounce_buffer_size, + data->bytes_xfered); + /* Cap it down and continue */ + length =3D host->bounce_buffer_size; + } + dma_sync_single_for_cpu(mmc_dev(host->mmc), + host->bounce_addr, + host->bounce_buffer_size, + DMA_FROM_DEVICE); + sg_copy_from_buffer(data->sg, + data->sg_len, + host->bounce_buffer, + length); + } else { + /* No copying, just switch ownership */ + dma_sync_single_for_cpu(mmc_dev(host->mmc), + host->bounce_addr, + host->bounce_buffer_size, + mmc_get_dma_dir(data)); + } + } else { + /* Unmap the raw data */ + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, + mmc_get_dma_dir(data)); + } + data->host_cookie =3D COOKIE_UNMAPPED; + } +} +EXPORT_SYMBOL_GPL(sdhci_request_done_dma); + static bool sdhci_request_done(struct sdhci_host *host) { unsigned long flags; @@ -3140,48 +3189,7 @@ static bool sdhci_request_done(struct sdhci_host *ho= st) sdhci_set_mrq_done(host, mrq); } =20 - if (data && data->host_cookie =3D=3D COOKIE_MAPPED) { - if (host->bounce_buffer) { - /* - * On reads, copy the bounced data into the - * sglist - */ - if (mmc_get_dma_dir(data) =3D=3D DMA_FROM_DEVICE) { - unsigned int length =3D data->bytes_xfered; - - if (length > host->bounce_buffer_size) { - pr_err("%s: bounce buffer is %u bytes but DMA claims to have transfe= rred %u bytes\n", - mmc_hostname(host->mmc), - host->bounce_buffer_size, - data->bytes_xfered); - /* Cap it down and continue */ - length =3D host->bounce_buffer_size; - } - dma_sync_single_for_cpu( - mmc_dev(host->mmc), - host->bounce_addr, - host->bounce_buffer_size, - DMA_FROM_DEVICE); - sg_copy_from_buffer(data->sg, - data->sg_len, - host->bounce_buffer, - length); - } else { - /* No copying, just switch ownership */ - dma_sync_single_for_cpu( - mmc_dev(host->mmc), - host->bounce_addr, - host->bounce_buffer_size, - mmc_get_dma_dir(data)); - } - } else { - /* Unmap the raw data */ - dma_unmap_sg(mmc_dev(host->mmc), data->sg, - data->sg_len, - mmc_get_dma_dir(data)); - } - data->host_cookie =3D COOKIE_UNMAPPED; - } + sdhci_request_done_dma(host, mrq); } =20 host->mrqs_done[i] =3D NULL; @@ -3196,7 +3204,7 @@ static bool sdhci_request_done(struct sdhci_host *hos= t) return false; } =20 -static void sdhci_complete_work(struct work_struct *work) +void sdhci_complete_work(struct work_struct *work) { struct sdhci_host *host =3D container_of(work, struct sdhci_host, complete_work); @@ -3204,6 +3212,7 @@ static void sdhci_complete_work(struct work_struct *w= ork) while (!sdhci_request_done(host)) ; } +EXPORT_SYMBOL_GPL(sdhci_complete_work); =20 static void sdhci_timeout_timer(struct timer_list *t) { @@ -3665,7 +3674,7 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) return result; } =20 -static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) +irqreturn_t sdhci_thread_irq(int irq, void *dev_id) { struct sdhci_host *host =3D dev_id; struct mmc_command *cmd; @@ -3695,6 +3704,7 @@ static irqreturn_t sdhci_thread_irq(int irq, void *de= v_id) =20 return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(sdhci_thread_irq); =20 /*************************************************************************= ****\ * = * @@ -4067,6 +4077,9 @@ struct sdhci_host *sdhci_alloc_host(struct device *de= v, =20 host->max_timeout_count =3D 0xE; =20 + host->complete_work_fn =3D sdhci_complete_work; + host->thread_irq_fn =3D sdhci_thread_irq; + return host; } =20 @@ -4831,7 +4844,7 @@ int __sdhci_add_host(struct sdhci_host *host) if (!host->complete_wq) return -ENOMEM; =20 - INIT_WORK(&host->complete_work, sdhci_complete_work); + INIT_WORK(&host->complete_work, host->complete_work_fn); =20 timer_setup(&host->timer, sdhci_timeout_timer, 0); timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); @@ -4840,7 +4853,7 @@ int __sdhci_add_host(struct sdhci_host *host) =20 sdhci_init(host, 0); =20 - ret =3D request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, + ret =3D request_threaded_irq(host->irq, sdhci_irq, host->thread_irq_fn, IRQF_SHARED, mmc_hostname(mmc), host); if (ret) { pr_err("%s: Failed to request IRQ %d: %d\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 5c66927210bd..5f416bc783bd 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -625,6 +625,9 @@ struct sdhci_host { struct timer_list timer; /* Timer for timeouts */ struct timer_list data_timer; /* Timer for data timeouts */ =20 + void (*complete_work_fn)(struct work_struct *work); + irqreturn_t (*thread_irq_fn)(int irq, void *dev_id); + #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) struct dma_chan *rx_chan; struct dma_chan *tx_chan; @@ -827,6 +830,7 @@ static inline void sdhci_read_caps(struct sdhci_host *h= ost) __sdhci_read_caps(host, NULL, NULL, NULL); } =20 +bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq); u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock); void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); @@ -845,6 +849,7 @@ void sdhci_request(struct mmc_host *mmc, struct mmc_req= uest *mrq); int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); void sdhci_set_bus_width(struct sdhci_host *host, int width); void sdhci_reset(struct sdhci_host *host, u8 mask); +bool sdhci_do_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode); @@ -854,6 +859,9 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios= *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); +void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *m= rq); +void sdhci_complete_work(struct work_struct *work); +irqreturn_t sdhci_thread_irq(int irq, void *dev_id); void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, unsigned int cmd); =20 --=20 2.25.1 From nobody Tue Nov 26 11:53:55 2024 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0225F203701; Fri, 18 Oct 2024 10:54:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248880; cv=none; b=UF7o7FVHCgIP7FD3Bf6IPk++2PdyEhs3lILiGWyH+FsL0Y76zXGEvTT5J22YaJ+unO80eUnUZFKw5gyl02B+OHsZfy87yLzWIWFGgsEWKybh1tkyiNuQlXINnGY1psfV3syhdBBLYyuBk0kCNIg4wxG1A0ya9gFu9b2YBYMfNwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248880; c=relaxed/simple; bh=CFzQ4Vv7dL/101A5xPHXt02EkDI0vj/zsYXvMDV0jEc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=exXabXOCB+BJzggYa3sHAbiR0tE3qplp7rAZzUoqRI+NEHStDTZaloZ0w/EzJCINTmRXdo6Wg7PJIJTqyrjZwfDl9e0eY0udNN5eWGpc09xfHCY3GkcDCqNw7VWvp/v6v/DBFy5tfglmvfk2A9P9INmWTLaRqmrm97zEZV980Qc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Y5l1jhYz; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y5l1jhYz" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-20c803787abso15437095ad.0; Fri, 18 Oct 2024 03:54:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248877; x=1729853677; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h7uSYeaZZwxXwIQD3LCDHDP91xIJh8wcjYWHXNSRfSs=; b=Y5l1jhYzoBRPVChf4yAQcF3FzSZcYF8Wm3PCj7T+AkRpPsM67pDbJyaHKhG522xrfZ XPR308H1t8RqgBNVwX4motnGDapgRMjCwzkDNkHUfhidKvdY47V6BSffs9fl/GXuvzrl OomzNjxILMEQjbcRyJkF+4ajLDWoquS+B6lAFBst0SMGBkesFwOJMf69XfJQ4kTAlb41 l+Qw2TOw/TSMSp3/e8EcYw0siZp3n92afzPd3YmKTMnKCfBIaYrvz5YDYc03+GqMVWQh JyDJELULE3kMKzZFPWdeUIrwpgRCb2sfgqHhSPgRKyL2M7y3ALQHLNpzDcXKJsSVN9aA dAkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248877; x=1729853677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h7uSYeaZZwxXwIQD3LCDHDP91xIJh8wcjYWHXNSRfSs=; b=KCnDJXFt9rQZvxWEWSvLUfmdqgxb5/5I8WE+jg0JtZDw1GYrv63zlBb3dn8wELqg28 bjs/qosQXsDXdXhMnBA9efF4ldilq3AJqZ1lWD0t8rQ7ckLcqWRauiKBnqnNFKJAntFf osep+SSm5BZSv+zay3Nuw31bBhto7dDUxVao6PWwaiVJvUTy4KMwvO7lPBguFVM4uWKQ wpk/E0CGLDtHYdU5cTpF5BXSwX3Aoe5Pgr4NX9CA+4zlXGYwN9rji1a71P4z3cQb2o16 856WV6MZOnwIUJ2xpZPtMHW9oa0yuWL2nJZMTyJMLIm7cBuAaFRXI3x02V4whX9Kx+D9 d6MA== X-Forwarded-Encrypted: i=1; AJvYcCVYYE1MpLEib+HxqoNn+EUVaytblZ8Rl1WF+NfQ5xWHxmQoB6EI6JbNP8nGml8pc98tGbJsHJKpwKClEgQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwiBwFvdm9euvKNIa+i/Kav6Pw4+VgjvpPNaHMXQU2Dq8Q99zLT cZmqPiH+RptptMc10QgsLUy55Zgij7oCLwEmkeiElZgz/DSMJm/m X-Google-Smtp-Source: AGHT+IHm4E9iB/HM8EmEClADUTdtAurvFuXYMZVgK760p4HpnqFnK7KNmCII6xQzx4MDNpop4VZh0w== X-Received: by 2002:a17:903:22c5:b0:20c:ad30:c891 with SMTP id d9443c01a7336-20d47414ea7mr90975365ad.10.1729248877114; Fri, 18 Oct 2024 03:54:37 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:36 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 12/16] mmc: sdhci-uhs2: add request() and others Date: Fri, 18 Oct 2024 18:53:29 +0800 Message-Id: <20241018105333.4569-13-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This is a sdhci version of mmc's request operation. It covers both UHS-I and UHS-II. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V22: - Adjust the patch order from v21 patch#16 to v22 patch#18 and add necessary code to avoid defined but not used warnings. Updates in V19: - cmd->uhs2_cmd->uhs2_resp is always true, remove it from safety check in the __sdhci_uhs2_finish_command(). Updates in V17: - Add new parameter to __sdhci_finish_data_common(). Updates in V16: - Remove irrelevant definition in the sdhci_calc_timeout_uhs2(). Updates in V15: - Adjust the parameters used in the __sdhci_uhs2_finish_command() to match changes in the Patch#7. Updates in V14: - Use mmc_card_uhs2() to stead sdhci_uhs2_mode() in the sdhci_uhs2_request(). Updates in V13: - Re-order function to avoid declaration. - Remove unnecessary function. Updates in V11: - Drop the check mmc_card_uhs2_hd_mode(host->mmc) in sdhci_uhs2_set_transfer_mode(). Updates in V10: - Use tmode_half_duplex to instead of uhs2_tmode0_flag in sdhci_uhs2_set_transfer_mode(). Updates in V9: - Modify the annotations in __sdhci_uhs2_send_command(). Updates in V8: - Adjust the position of matching brackets in sdhci_uhs2_send_command_retry(). - Modify CameCase definition in __sdhci_uhs2_finish_command(). - Modify error message in __sdhci_uhs2_finish_command(). - sdhci_uhs2_send_command_retry() to instead of sdhci_uhs2_send_command() in sdhci_uhs2_request(). - Use sdhci_uhs2_mode() to simplify code in sdhci_uhs2_request_atomic(). - Add forward declaration for sdhci_send_command(). Updates in V7: - Cancel export state of some functions. - Remove unnecessary whitespace changes. Updates in V6: - Add uhs2_dev_cmd() to simplify code. - Remove unnecessary functions. - Cancel export state of some functions. - Drop use CONFIG_MMC_DEBUG(). - Wrap at 100 columns in some functions. --- drivers/mmc/host/sdhci-uhs2.c | 392 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 53 +++-- drivers/mmc/host/sdhci.h | 8 + 3 files changed, 437 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 76f1af8b0486..d99ea05098cb 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include =20 #include "sdhci.h" #include "sdhci-uhs2.h" @@ -30,6 +32,8 @@ #define UHS2_INTERFACE_DETECT_TIMEOUT_100MS 100000 #define UHS2_LANE_SYNC_TIMEOUT_150MS 150000 =20 +#define UHS2_ARG_IOADR_MASK 0xfff + void sdhci_uhs2_dump_regs(struct sdhci_host *host) { if (!(mmc_card_uhs2(host->mmc))) @@ -64,6 +68,11 @@ EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); * = * \*************************************************************************= ****/ =20 +static inline u16 uhs2_dev_cmd(struct mmc_command *cmd) +{ + return be16_to_cpu((__be16)cmd->uhs2_cmd->arg) & UHS2_ARG_IOADR_MASK; +} + static inline int mmc_opt_regulator_set_ocr(struct mmc_host *mmc, struct regulator *supply, unsigned short vdd_bit) @@ -542,6 +551,374 @@ static int sdhci_uhs2_control(struct mmc_host *mmc, e= num sd_uhs2_operation op) return err; } =20 +/*************************************************************************= ****\ + * = * + * Core functions = * + * = * +\*************************************************************************= ****/ + +static void sdhci_uhs2_prepare_data(struct sdhci_host *host, struct mmc_co= mmand *cmd) +{ + struct mmc_data *data =3D cmd->data; + + sdhci_initialize_data(host, data); + + sdhci_prepare_dma(host, data); + + sdhci_writew(host, data->blksz, SDHCI_UHS2_BLOCK_SIZE); + sdhci_writew(host, data->blocks, SDHCI_UHS2_BLOCK_COUNT); +} + +static void sdhci_uhs2_finish_data(struct sdhci_host *host) +{ + struct mmc_data *data =3D host->data; + + __sdhci_finish_data_common(host, true); + + __sdhci_finish_mrq(host, data->mrq); +} + +static void sdhci_uhs2_set_transfer_mode(struct sdhci_host *host, struct m= mc_command *cmd) +{ + u16 mode; + struct mmc_data *data =3D cmd->data; + + if (!data) { + /* clear Auto CMD settings for no data CMDs */ + if (uhs2_dev_cmd(cmd) =3D=3D UHS2_DEV_CMD_TRANS_ABORT) { + mode =3D 0; + } else { + mode =3D sdhci_readw(host, SDHCI_UHS2_TRANS_MODE); + if (cmd->opcode =3D=3D MMC_STOP_TRANSMISSION || cmd->opcode =3D=3D MMC_= ERASE) + mode |=3D SDHCI_UHS2_TRNS_WAIT_EBSY; + else + /* send status mode */ + if (cmd->opcode =3D=3D MMC_SEND_STATUS) + mode =3D 0; + } + + DBG("UHS2 no data trans mode is 0x%x.\n", mode); + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + return; + } + + WARN_ON(!host->data); + + mode =3D SDHCI_UHS2_TRNS_BLK_CNT_EN | SDHCI_UHS2_TRNS_WAIT_EBSY; + if (data->flags & MMC_DATA_WRITE) + mode |=3D SDHCI_UHS2_TRNS_DATA_TRNS_WRT; + + if (data->blocks =3D=3D 1 && + data->blksz !=3D 512 && + cmd->opcode !=3D MMC_READ_SINGLE_BLOCK && + cmd->opcode !=3D MMC_WRITE_BLOCK) { + mode &=3D ~SDHCI_UHS2_TRNS_BLK_CNT_EN; + mode |=3D SDHCI_UHS2_TRNS_BLK_BYTE_MODE; + } + + if (host->flags & SDHCI_REQ_USE_DMA) + mode |=3D SDHCI_UHS2_TRNS_DMA; + + if (cmd->uhs2_cmd->tmode_half_duplex) + mode |=3D SDHCI_UHS2_TRNS_2L_HD; + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + + DBG("UHS2 trans mode is 0x%x.\n", mode); +} + +static void __sdhci_uhs2_send_command(struct sdhci_host *host, struct mmc_= command *cmd) +{ + int i, j; + int cmd_reg; + + i =3D 0; + sdhci_writel(host, + ((u32)cmd->uhs2_cmd->arg << 16) | + (u32)cmd->uhs2_cmd->header, + SDHCI_UHS2_CMD_PACKET + i); + i +=3D 4; + + /* + * Per spec, payload (config) should be MSB before sending out. + * But we don't need convert here because had set payload as + * MSB when preparing config read/write commands. + */ + for (j =3D 0; j < cmd->uhs2_cmd->payload_len / sizeof(u32); j++) { + sdhci_writel(host, *(cmd->uhs2_cmd->payload + j), SDHCI_UHS2_CMD_PACKET = + i); + i +=3D 4; + } + + for ( ; i < SDHCI_UHS2_CMD_PACK_MAX_LEN; i +=3D 4) + sdhci_writel(host, 0, SDHCI_UHS2_CMD_PACKET + i); + + DBG("UHS2 CMD packet_len =3D %d.\n", cmd->uhs2_cmd->packet_len); + for (i =3D 0; i < cmd->uhs2_cmd->packet_len; i++) + DBG("UHS2 CMD_PACKET[%d] =3D 0x%x.\n", i, + sdhci_readb(host, SDHCI_UHS2_CMD_PACKET + i)); + + cmd_reg =3D FIELD_PREP(SDHCI_UHS2_CMD_PACK_LEN_MASK, cmd->uhs2_cmd->packe= t_len); + if ((cmd->flags & MMC_CMD_MASK) =3D=3D MMC_CMD_ADTC) + cmd_reg |=3D SDHCI_UHS2_CMD_DATA; + if (cmd->opcode =3D=3D MMC_STOP_TRANSMISSION) + cmd_reg |=3D SDHCI_UHS2_CMD_CMD12; + + /* UHS2 Native ABORT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + (uhs2_dev_cmd(cmd) =3D=3D UHS2_DEV_CMD_TRANS_ABORT)) + cmd_reg |=3D SDHCI_UHS2_CMD_TRNS_ABORT; + + /* UHS2 Native DORMANT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + (uhs2_dev_cmd(cmd) =3D=3D UHS2_DEV_CMD_GO_DORMANT_STATE)) + cmd_reg |=3D SDHCI_UHS2_CMD_DORMANT; + + DBG("0x%x is set to UHS2 CMD register.\n", cmd_reg); + + sdhci_writew(host, cmd_reg, SDHCI_UHS2_CMD); +} + +static bool sdhci_uhs2_send_command(struct sdhci_host *host, struct mmc_co= mmand *cmd) +{ + int flags; + u32 mask; + unsigned long timeout; + + WARN_ON(host->cmd); + + /* Initially, a command has no error */ + cmd->error =3D 0; + + if (cmd->opcode =3D=3D MMC_STOP_TRANSMISSION) + cmd->flags |=3D MMC_RSP_BUSY; + + mask =3D SDHCI_CMD_INHIBIT; + + if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) + return false; + + host->cmd =3D cmd; + host->data_timeout =3D 0; + if (sdhci_data_line_cmd(cmd)) { + WARN_ON(host->data_cmd); + host->data_cmd =3D cmd; + __sdhci_uhs2_set_timeout(host); + } + + if (cmd->data) + sdhci_uhs2_prepare_data(host, cmd); + + sdhci_uhs2_set_transfer_mode(host, cmd); + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + WARN_ONCE(1, "Unsupported response type!\n"); + /* + * This does not happen in practice because 136-bit response + * commands never have busy waiting, so rather than complicate + * the error path, just remove busy waiting and continue. + */ + cmd->flags &=3D ~MMC_RSP_BUSY; + } + + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags =3D SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags =3D SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags =3D SDHCI_CMD_RESP_SHORT_BUSY; + else + flags =3D SDHCI_CMD_RESP_SHORT; + + if (cmd->flags & MMC_RSP_CRC) + flags |=3D SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |=3D SDHCI_CMD_INDEX; + + timeout =3D jiffies; + if (host->data_timeout) + timeout +=3D nsecs_to_jiffies(host->data_timeout); + else if (!cmd->data && cmd->busy_timeout > 9000) + timeout +=3D DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; + else + timeout +=3D 10 * HZ; + sdhci_mod_timer(host, cmd->mrq, timeout); + + __sdhci_uhs2_send_command(host, cmd); + + return true; +} + +static bool sdhci_uhs2_send_command_retry(struct sdhci_host *host, + struct mmc_command *cmd, + unsigned long flags) + __releases(host->lock) + __acquires(host->lock) +{ + struct mmc_command *deferred_cmd =3D host->deferred_cmd; + int timeout =3D 10; /* Approx. 10 ms */ + bool present; + + while (!sdhci_uhs2_send_command(host, cmd)) { + if (!timeout--) { + pr_err("%s: Controller never released inhibit bit(s).\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + cmd->error =3D -EIO; + return false; + } + + spin_unlock_irqrestore(&host->lock, flags); + + usleep_range(1000, 1250); + + present =3D host->mmc->ops->get_cd(host->mmc); + + spin_lock_irqsave(&host->lock, flags); + + /* A deferred command might disappear, handle that */ + if (cmd =3D=3D deferred_cmd && cmd !=3D host->deferred_cmd) + return true; + + if (sdhci_present_error(host, cmd, present)) + return false; + } + + if (cmd =3D=3D host->deferred_cmd) + host->deferred_cmd =3D NULL; + + return true; +} + +static void __sdhci_uhs2_finish_command(struct sdhci_host *host) +{ + struct mmc_command *cmd =3D host->cmd; + u8 resp; + u8 error_code; + bool breada0 =3D 0; + int i; + + if (host->mmc->uhs2_sd_tran) { + resp =3D sdhci_readb(host, SDHCI_UHS2_RESPONSE + 2); + if (resp & UHS2_RES_NACK_MASK) { + error_code =3D (resp >> UHS2_RES_ECODE_POS) & UHS2_RES_ECODE_MASK; + pr_err("%s: NACK response, ECODE=3D0x%x.\n", + mmc_hostname(host->mmc), error_code); + } + breada0 =3D 1; + } + + if (cmd->uhs2_cmd->uhs2_resp_len) { + int len =3D min_t(int, cmd->uhs2_cmd->uhs2_resp_len, UHS2_MAX_RESP_LEN); + + /* Get whole response of some native CCMD, like + * DEVICE_INIT, ENUMERATE. + */ + for (i =3D 0; i < len; i++) + cmd->uhs2_cmd->uhs2_resp[i] =3D sdhci_readb(host, SDHCI_UHS2_RESPONSE += i); + } else { + /* Get SD CMD response and Payload for some read + * CCMD, like INQUIRY_CFG. + */ + /* Per spec (p136), payload field is divided into + * a unit of DWORD and transmission order within + * a DWORD is big endian. + */ + if (!breada0) + sdhci_readl(host, SDHCI_UHS2_RESPONSE); + for (i =3D 4; i < 20; i +=3D 4) { + cmd->resp[i / 4 - 1] =3D + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i) << 24) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 1) + << 16) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 2) + << 8) | + sdhci_readb(host, SDHCI_UHS2_RESPONSE + i + 3); + } + } +} + +static void sdhci_uhs2_finish_command(struct sdhci_host *host) +{ + struct mmc_command *cmd =3D host->cmd; + + __sdhci_uhs2_finish_command(host); + + host->cmd =3D NULL; + + if (cmd->mrq->cap_cmd_during_tfr && cmd =3D=3D cmd->mrq->cmd) + mmc_command_done(host->mmc, cmd->mrq); + + /* + * The host can send and interrupt when the busy state has + * ended, allowing us to wait without wasting CPU cycles. + * The busy signal uses DAT0 so this is similar to waiting + * for data to complete. + * + * Note: The 1.0 specification is a bit ambiguous about this + * feature so there might be some problems with older + * controllers. + */ + if (cmd->flags & MMC_RSP_BUSY) { + if (cmd->data) { + DBG("Cannot wait for busy signal when also doing a data transfer"); + } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && + cmd =3D=3D host->data_cmd) { + /* Command complete before busy is ended */ + return; + } + } + + /* Processed actual command. */ + if (host->data && host->data_early) + sdhci_uhs2_finish_data(host); + + if (!cmd->data) + __sdhci_finish_mrq(host, cmd->mrq); +} + +static void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *m= rq) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct mmc_command *cmd; + unsigned long flags; + bool present; + + if (!(mmc_card_uhs2(mmc))) { + sdhci_request(mmc, mrq); + return; + } + + mrq->stop =3D NULL; + mrq->sbc =3D NULL; + if (mrq->data) + mrq->data->stop =3D NULL; + + /* Firstly check card presence */ + present =3D mmc->ops->get_cd(mmc); + + spin_lock_irqsave(&host->lock, flags); + + if (sdhci_present_error(host, mrq->cmd, present)) + goto out_finish; + + cmd =3D mrq->cmd; + + if (!sdhci_uhs2_send_command_retry(host, cmd, flags)) + goto out_finish; + + spin_unlock_irqrestore(&host->lock, flags); + + return; + +out_finish: + sdhci_finish_mrq(host, mrq); + spin_unlock_irqrestore(&host->lock, flags); +} + /*************************************************************************= ****\ * = * * Request done = * @@ -638,6 +1015,8 @@ static void sdhci_uhs2_complete_work(struct work_struc= t *work) =20 static void __sdhci_uhs2_irq(struct sdhci_host *host, u32 uhs2mask) { + struct mmc_command *cmd =3D host->cmd; + DBG("*** %s got UHS2 error interrupt: 0x%08x\n", mmc_hostname(host->mmc), uhs2mask); =20 @@ -677,6 +1056,12 @@ static void __sdhci_uhs2_irq(struct sdhci_host *host,= u32 uhs2mask) host->data->error =3D -EILSEQ; } } + + if (host->data && host->data->error) + sdhci_uhs2_finish_data(host); + else + sdhci_finish_mrq(host, cmd->mrq); + } =20 u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask) @@ -708,6 +1093,10 @@ u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intma= sk) /* Clear command interrupt */ sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); =20 + /* Handle command interrupt */ + if (intmask & SDHCI_INT_RESPONSE) + sdhci_uhs2_finish_command(host); + /* Caller, sdhci_irq(), doesn't have to care about UHS-2 commands */ intmask &=3D ~SDHCI_INT_CMD_MASK; mask &=3D SDHCI_INT_CMD_MASK; @@ -740,6 +1129,8 @@ static irqreturn_t sdhci_uhs2_thread_irq(int irq, void= *dev_id) host->thread_isr =3D 0; =20 cmd =3D host->deferred_cmd; + if (cmd && !sdhci_uhs2_send_command_retry(host, cmd, flags)) + sdhci_finish_mrq(host, cmd->mrq); =20 spin_unlock_irqrestore(&host->lock, flags); =20 @@ -762,6 +1153,7 @@ static irqreturn_t sdhci_uhs2_thread_irq(int irq, void= *dev_id) static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { host->mmc_host_ops.uhs2_control =3D sdhci_uhs2_control; + host->mmc_host_ops.request =3D sdhci_uhs2_request; =20 return 0; } diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 871b4fe2a1b2..f4a7733a8ad2 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -147,10 +147,11 @@ void sdhci_enable_v4_mode(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); =20 -static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) +bool sdhci_data_line_cmd(struct mmc_command *cmd) { return cmd->data || cmd->flags & MMC_RSP_BUSY; } +EXPORT_SYMBOL_GPL(sdhci_data_line_cmd); =20 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) { @@ -503,14 +504,15 @@ static inline void sdhci_led_deactivate(struct sdhci_= host *host) =20 #endif =20 -static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *m= rq, - unsigned long timeout) +void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, + unsigned long timeout) { if (sdhci_data_line_cmd(mrq->cmd)) mod_timer(&host->data_timer, timeout); else mod_timer(&host->timer, timeout); } +EXPORT_SYMBOL_GPL(sdhci_mod_timer); =20 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *m= rq) { @@ -1077,8 +1079,7 @@ static void sdhci_set_timeout(struct sdhci_host *host= , struct mmc_command *cmd) __sdhci_set_timeout(host, cmd); } =20 -static void sdhci_initialize_data(struct sdhci_host *host, - struct mmc_data *data) +void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data) { WARN_ON(host->data); =20 @@ -1091,6 +1092,7 @@ static void sdhci_initialize_data(struct sdhci_host *= host, host->data_early =3D 0; host->data->bytes_xfered =3D 0; } +EXPORT_SYMBOL_GPL(sdhci_initialize_data); =20 static inline void sdhci_set_block_info(struct sdhci_host *host, struct mmc_data *data) @@ -1113,12 +1115,8 @@ static inline void sdhci_set_block_info(struct sdhci= _host *host, } } =20 -static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command= *cmd) +void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data) { - struct mmc_data *data =3D cmd->data; - - sdhci_initialize_data(host, data); - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { struct scatterlist *sg; unsigned int length_mask, offset_mask; @@ -1203,6 +1201,16 @@ static void sdhci_prepare_data(struct sdhci_host *ho= st, struct mmc_command *cmd) } =20 sdhci_set_transfer_irqs(host); +} +EXPORT_SYMBOL_GPL(sdhci_prepare_dma); + +static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command= *cmd) +{ + struct mmc_data *data =3D cmd->data; + + sdhci_initialize_data(host, data); + + sdhci_prepare_dma(host, data); =20 sdhci_set_block_info(host, data); } @@ -1521,7 +1529,7 @@ static void sdhci_set_mrq_done(struct sdhci_host *hos= t, struct mmc_request *mrq) WARN_ON(i >=3D SDHCI_MAX_MRQS); } =20 -static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request= *mrq) +void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { if (host->cmd && host->cmd->mrq =3D=3D mrq) host->cmd =3D NULL; @@ -1545,15 +1553,17 @@ static void __sdhci_finish_mrq(struct sdhci_host *h= ost, struct mmc_request *mrq) if (!sdhci_has_requests(host)) sdhci_led_deactivate(host); } +EXPORT_SYMBOL_GPL(__sdhci_finish_mrq); =20 -static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *= mrq) +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { __sdhci_finish_mrq(host, mrq); =20 queue_work(host->complete_wq, &host->complete_work); } +EXPORT_SYMBOL_GPL(sdhci_finish_mrq); =20 -static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_time= out) +void __sdhci_finish_data_common(struct sdhci_host *host, bool defer_reset) { struct mmc_command *data_cmd =3D host->data_cmd; struct mmc_data *data =3D host->data; @@ -1566,7 +1576,9 @@ static void __sdhci_finish_data(struct sdhci_host *ho= st, bool sw_data_timeout) * conditions. */ if (data->error) { - if (!host->cmd || host->cmd =3D=3D data_cmd) + if (defer_reset) + host->pending_reset =3D true; + else if (!host->cmd || host->cmd =3D=3D data_cmd) sdhci_reset_for(host, REQUEST_ERROR); else sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY); @@ -1587,6 +1599,14 @@ static void __sdhci_finish_data(struct sdhci_host *h= ost, bool sw_data_timeout) data->bytes_xfered =3D 0; else data->bytes_xfered =3D data->blksz * data->blocks; +} +EXPORT_SYMBOL_GPL(__sdhci_finish_data_common); + +static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_time= out) +{ + struct mmc_data *data =3D host->data; + + __sdhci_finish_data_common(host, false); =20 /* * Need to send CMD12 if - @@ -1721,8 +1741,8 @@ static bool sdhci_send_command(struct sdhci_host *hos= t, struct mmc_command *cmd) return true; } =20 -static bool sdhci_present_error(struct sdhci_host *host, - struct mmc_command *cmd, bool present) +bool sdhci_present_error(struct sdhci_host *host, + struct mmc_command *cmd, bool present) { if (!present || host->flags & SDHCI_DEVICE_DEAD) { cmd->error =3D -ENOMEDIUM; @@ -1731,6 +1751,7 @@ static bool sdhci_present_error(struct sdhci_host *ho= st, =20 return false; } +EXPORT_SYMBOL_GPL(sdhci_present_error); =20 static bool sdhci_send_command_retry(struct sdhci_host *host, struct mmc_command *cmd, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 5f416bc783bd..c636808139d5 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -831,6 +831,14 @@ static inline void sdhci_read_caps(struct sdhci_host *= host) } =20 bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq); +bool sdhci_data_line_cmd(struct mmc_command *cmd); +void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, uns= igned long timeout); +void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data); +void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data); +void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); +void __sdhci_finish_data_common(struct sdhci_host *host, bool defer_reset); +bool sdhci_present_error(struct sdhci_host *host, struct mmc_command *cmd,= bool present); u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock); void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); --=20 2.25.1 From nobody Tue Nov 26 11:53:55 2024 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1DCA20371E; Fri, 18 Oct 2024 10:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248883; cv=none; b=O943AeW0BLkDmZiFwT6693m8I7A8fjVLH2zTg4+t5uANGp8z+S+WJ0o4zJrV+cL5mzs31gJ6tkF2XuJVX3JY7eP06ke09o9+cuoYGQM3pFSj1ev+1FSvSvkkh3ZghWZ3CUahTiiZL5rMgdKBTBMxC8+16AM2t1x/xx8oavuKXgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248883; c=relaxed/simple; bh=v4MM9bGqXsTwGu4en4i1RloVtI86bYOecflv6HHdnis=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JCVPTGkTb0+nnxNl+yrur77yzL/me1eyPZfduusMH/i024LK+2AgozieoWVEiUabl/sYF4oNr1O1HlLD7MZEYFlibKdVLnVQiDORA1oLU7B9X5cS1fej+q/OpiGwE6yWQpYThDI/Dr+92YRm6hQj1wXHDgG65n0W356lLvUT8sk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=P8DE3BpF; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P8DE3BpF" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-20ca1b6a80aso17761365ad.2; Fri, 18 Oct 2024 03:54:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248881; x=1729853681; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pefaTk8qKKbtSAgriHJ425KtY2+eFqYfJpkB9h3wzgM=; b=P8DE3BpFV+CXo89ysAfU+p2K9aWpNQK+i9xmIUeHkDsNiBHvuU/SOobGcKEMWp1jEj zYL6Zo6j6goUYC/5Fe+vOecNuCVDpUaCkRNqXfHGc3puKNVuktC/uBIqWGadFxreWFyi eqjX7NjSKbzIpQsL3KhFoY6/vZLUbQJimGhILmQ3McSLnkklEOqFIFmThAdO5rh/iGKx B3OQu911usAWYdTYVwSlBomZZNlJO1ZsEoTjSTOMOjZdc6WH35XmxkNSb4QTCK3mLr0r zUxZhgXAyuMvgAQLwX7hR0u3b7B4uCOmLOPV3GD1dTRExZNBoAq48JvI3fkpS/0wCMM0 AjCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248881; x=1729853681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pefaTk8qKKbtSAgriHJ425KtY2+eFqYfJpkB9h3wzgM=; b=SHYnbams3v8TA3SVU46Q0oRsaiK0HvFuRiD1tjQxF74rwERF9X/ZVklwIhkAWpl1u/ W/vR/ZM5EgwghaPWYsum3zg6iQxyMtTEellMCvDDfIwWaZQQU7Cs4PBMLLoqS/GrmHWF md2N5KI+TmYN19hIchgwfSJNMprt3RqJMk8Mml4/bcSZI2flPMPAErEHGifXqcOwFRy1 D3rmumNDZ37mLNtjNN3+xjptso/cebxqZK3oYMXShjmNltqRZnkruDbzGaCzyW+0POUY /GpAFIyYQCEkqv/jbooOZA1TXknX8wFhHxGkHwQWbUUxuLpf/RxMpvSZrNdKlN0oDaya UHnw== X-Forwarded-Encrypted: i=1; AJvYcCXZ3IhwvJTPQ2QLRC49PX6BaTInQnJtmaWLewpBt0laOweohiAEcwKyXBE5EyTDS1MAdS6XwVZ+7XEb6kA=@vger.kernel.org X-Gm-Message-State: AOJu0YwViiGTM+jzKdXEKvFqgCDWDArKSvlhnLgRErZyZwCPjEZH+MDo FwyF1Ra/utf+2ge1n4uEdARZ1kozNk8PyT4Bgcx8Oky2zSosfff9 X-Google-Smtp-Source: AGHT+IFukLFvY6uQ1WJOZS66U/6VdVB1klGJ4tHMml5jWOCqbh3LIRPfiDswVCt7lDEjRuujg2GpcQ== X-Received: by 2002:a17:903:192:b0:20b:9c8c:e9f3 with SMTP id d9443c01a7336-20e5a7663c2mr18394105ad.14.1729248881202; Fri, 18 Oct 2024 03:54:41 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:40 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro Subject: [PATCH V23 13/16] mmc: sdhci-uhs2: add pre-detect_init hook Date: Fri, 18 Oct 2024 18:53:30 +0800 Message-Id: <20241018105333.4569-14-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ben Chuang This "pre" hook for detect_init(), uhs2_pre_detect_init, will be required to enable UHS-II support, at least, on GL9755. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-uhs2.c | 3 +++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index d99ea05098cb..c488c6d56015 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -413,6 +413,9 @@ static int sdhci_uhs2_do_detect_init(struct mmc_host *m= mc) =20 DBG("Begin do uhs2 detect init.\n"); =20 + if (host->ops && host->ops->uhs2_pre_detect_init) + host->ops->uhs2_pre_detect_init(host); + if (sdhci_uhs2_interface_detect(host)) { pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc)); return -EIO; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c636808139d5..cd0e35a80542 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -723,6 +723,7 @@ struct sdhci_ops { struct mmc_request *mrq); void (*dump_vendor_regs)(struct sdhci_host *host); void (*dump_uhs2_regs)(struct sdhci_host *host); + void (*uhs2_pre_detect_init)(struct sdhci_host *host); }; =20 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS --=20 2.25.1 From nobody Tue Nov 26 11:53:55 2024 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA8C9206962; Fri, 18 Oct 2024 10:54:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248888; cv=none; b=fIT7kYBcHn1xTfoAp8Gz8agm+DYmzEJG1gkv9pv8UCpCzFnTab6ApeDPYOSNHvgjI8A2c1TjQ449tz2zl/zpfgBUNW+yGCcDZhxaNFoReqrfRTAXr5UYob65atRuaicMlt0Axrhp4VvbXi63XgHRD+0rwYvl4LW9EfzOGMcVtXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248888; c=relaxed/simple; bh=kx+4OyfPkgdDsZx2EqLrYQ2HGDcBIftS9eZE7hBiy/g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IGlZrZNRLdho4Bn3+VAuh+1AaKLbGePkJDkKIwjOmIgqZSBI3RbqyHMV4uafYs994ZrRM4n2J0HU/ItgWZKC+PLpqXoudh5BdErA8dll1Q0MUBmT7KEqPGehAB/7iU1IKX7dD/FUJ/79/L6gnvW9T8pzfM4fTy3ejT9Cg1/90bA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EeW6WGhD; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EeW6WGhD" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-20c805a0753so16794815ad.0; Fri, 18 Oct 2024 03:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248886; x=1729853686; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WEAeEioysszMV4Bk2sIJDxmaz1U5aF7RkBrmONafTZ8=; b=EeW6WGhDpqk82cuXsYYdWHi4hIP2IvKkWNzGeSVMCLeZI4erwmNqJZ7q7Hd8eJyQQE DGdFI1qcdBlli46rXkRkb98Oqqye1YyXzl+j7yBtsV7YH+6ohfWMBIMUNiX8NwbvdIQP M5QlcdNiPJAukktJZALZpNv2tuxpg9KFfprVgOoUgKHXDKTzut3haDfmo/wAKszwXhS9 g5EOECirfu/RNYAyEo9Sq/MAadTKC9Lnx86EtR9UFN3WCRTCFSZ+xjDQtudbSXC9mltX DGSoVPj0fLKrfWBtYzoMHDiCSQJKd0hh85+/8rOJ9u3gFx0SI0r4IsqI0r3ZKtXqhvX1 o6xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248886; x=1729853686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WEAeEioysszMV4Bk2sIJDxmaz1U5aF7RkBrmONafTZ8=; b=g+GDL7BbJLvDNHIAjHn0IHDL0mcorESGaeSkDtFFKnM2TmVIlVohzg0D2j8bJ9ssUy Ec2SjHIvrQ08J2ixkiCxVqto4XDVgTWDGh2ujw15VxR+0jPJTWmAPlP5CyFBxwDrVpqJ t4FS5eK4C42tDDc9XYM4FZ+EolGrkM6qbMJU6Bq18wSOW+ul11EQskExlkAdx1Sys6gj RSCY11sahJaFMImjYOdG7e2TK7vCr1eRIQvahIq4kmvN1CjLlDTn0U5QSMDxayEy1f35 zKbO3YzJ8f7a5n0+DhRPMztDYWPDuLvuj0hJZmZmp0F55M+ME+cLZkXLQFpmB9nuK1WS Dtlw== X-Forwarded-Encrypted: i=1; AJvYcCWn95SDmXt2i1BH067RihjrpzRXTV/zJXmXZWsfl1aar6XgN6MvYCcjnBt/dMZz4ELSdnzoM0RLqOpbMaQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzInY2AAhIa1leCuaKao+xX7Nm1oN759wp5VzuuC7C7jAxwdXkk P1DnLETGfUKlCBruQFeO9NiwU9OzEq5xh+KwA8iZAZAp5RTXKNh6 X-Google-Smtp-Source: AGHT+IFotUVUQtMDO8R7mVjD7kkaM+4IzA45gO52edlUiYEQWeiLtjGsy1XnBqZ4pfzqFm07jRItuQ== X-Received: by 2002:a17:903:2307:b0:20c:94f6:3e03 with SMTP id d9443c01a7336-20e5a8fb2e9mr26100835ad.47.1729248886046; Fri, 18 Oct 2024 03:54:46 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:45 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih Subject: [PATCH V23 14/16] mmc: sdhci-pci: add UHS-II support framework Date: Fri, 18 Oct 2024 18:53:31 +0800 Message-Id: <20241018105333.4569-15-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih This patch prepares for adding UHS-II support at a specific UHS-II capable sdhci-pci controller, GL9755 for now. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V8: - Add config select MMC_SDHCI_UHS2 in Kconfig. --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-pci-core.c | 16 +++++++++++++++- drivers/mmc/host/sdhci-pci.h | 3 +++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 45df8ddb8918..fec470225584 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -111,6 +111,7 @@ config MMC_SDHCI_PCI tristate "SDHCI support on PCI bus" depends on MMC_SDHCI && PCI select MMC_CQHCI + select MMC_SDHCI_UHS2 select IOSF_MBI if X86 select MMC_SDHCI_IO_ACCESSORS help diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci= -core.c index ed45ed0bdafd..2b300bc4a701 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -40,6 +40,7 @@ #include "sdhci.h" #include "sdhci-cqhci.h" #include "sdhci-pci.h" +#include "sdhci-uhs2.h" =20 static void sdhci_pci_hw_reset(struct sdhci_host *host); =20 @@ -2181,7 +2182,10 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_s= lot *slot) if (scratch =3D=3D (u32)-1) dead =3D 1; =20 - sdhci_remove_host(slot->host, dead); + if (slot->chip->fixes && slot->chip->fixes->remove_host) + slot->chip->fixes->remove_host(slot, dead); + else + sdhci_remove_host(slot->host, dead); =20 if (slot->chip->fixes && slot->chip->fixes->remove_slot) slot->chip->fixes->remove_slot(slot, dead); @@ -2189,6 +2193,16 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_s= lot *slot) sdhci_free_host(slot->host); } =20 +int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot) +{ + return sdhci_uhs2_add_host(slot->host); +} + +void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead) +{ + sdhci_uhs2_remove_host(slot->host, dead); +} + static void sdhci_pci_runtime_pm_allow(struct device *dev) { pm_suspend_ignore_children(dev, 1); diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index 153704f812ed..e807c039a8b1 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -145,6 +145,7 @@ struct sdhci_pci_fixes { int (*probe_slot) (struct sdhci_pci_slot *); int (*add_host) (struct sdhci_pci_slot *); void (*remove_slot) (struct sdhci_pci_slot *, int); + void (*remove_host) (struct sdhci_pci_slot *, int); =20 #ifdef CONFIG_PM_SLEEP int (*suspend) (struct sdhci_pci_chip *); @@ -189,6 +190,8 @@ static inline void *sdhci_pci_priv(struct sdhci_pci_slo= t *slot) return (void *)slot->private; } =20 +int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot); +void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead); #ifdef CONFIG_PM_SLEEP int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); #endif --=20 2.25.1 From nobody Tue Nov 26 11:53:55 2024 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E8992038B6; Fri, 18 Oct 2024 10:54:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248893; cv=none; b=bpyPNylRx9lP+CSMiTyoQIwdrFd6fP+QBzkqWQXSrIz/LmLZohmk86/SKexuCYPPSBGc7Ltql6UX4aLRj+IMy+yYFLCX+gD025I7KBuxBc/19gw0n6p4X+xswNi536vcPP67g6v3DCjDOOExR+Jojrluf3ec+VIvPHV1h78h+Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248893; c=relaxed/simple; bh=yBPWMM+UcxmD8WxaMTZD9fPg9PqlDCKf90o5THqyUNM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lUn0+CjVKyBPr+xBWRJXrGHPDXQWBmRpnobiMhs3GzMxGeYsXWXroEZYcs9J5nzAtukR8k4brVv4fJ/TgHDIlBoHbH6UPU4s2NWQ8b0g17+xGZBHw4Zzw/bBwBPMPI42CDXeC9nn4Io/ZUv4cnC4mKcyireenznYVjhm25kQAYw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=d1vP1vQz; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="d1vP1vQz" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-20cbb1cf324so16550295ad.0; Fri, 18 Oct 2024 03:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248891; x=1729853691; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ec3ffwGVG4T3zOAIwR5JyB4bVTuiuJxx1Z4oCNcuYcM=; b=d1vP1vQz5dwScLDYpS1U2+GVHDpdmoe9OEu3r2FqVCzskFN8ID0n1G3j+0Q5XuiWgX bYw10ek3tvA/Rr0vqQCe4oS/lgqZ4W5zmIgl7PTvZZWjREnpqAzeTIpatizhgAmenMU1 kLkrCMOc00Ipq78OYr30BWDOR3DD45Ae6kKd3hKMu4c7cnvFcW/IupQ5s15okVB5UH25 qzZdn5kPZaCvFk8yERuL+HeR6Cvf3dmvjS/+otpknaHLY3xrbxLScewWSCCXBmLAELym 51OviNJ+TNy5Lr93Nq66LIsB66rPPdv4eOfxYpNv0cyKenBerRhefDLWtiW3NrHEJUz5 W+UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248891; x=1729853691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ec3ffwGVG4T3zOAIwR5JyB4bVTuiuJxx1Z4oCNcuYcM=; b=FyjKAqupvmGKEFavkEvVaETUszFuFv15UUHd8Zicq9QkJWa2S5/jrlhCt3BNmsfTnt 210fhpn6DQirrEwaabIgtQzgoOT3rXvUuOrpEypqobelgNpdqe5fBAQ1MpEIbwuJ3kxt kRA6q4bNJooDgF+e+wjXmyCCknS0Jf+J2a8swBTjfuo2aTIg0z2EI55Z01vAXyzqPVZ9 kkHgT9KjWK9+3MJYo9lDyCwoOXuqIhhB98M0Haq6TIdw7Kf+M7hYcc1NQaIlUrklLg3U rf7rrnNhL6qBprrcm2yE1K+Jiu34O2Q/Wv5f+1Qt6vqgAc5Q4EVVbpZ6xuCiYvhe3yd6 N7rQ== X-Forwarded-Encrypted: i=1; AJvYcCWtpG0k6SdvmZZnZWbA289M3t6DRAgl09L0jtXlT5BpwK1S+108XNp/59MiuaRq6G2J6eNr1fPi2sC5OyA=@vger.kernel.org X-Gm-Message-State: AOJu0YyNgjqUi4dBJ+vO2y40EcY1Ro9JMxXYqZBao6lcfO/S2ygiUREK BmoAcPC7Z/7fxbXSxgrponebiYTFsn3S6jIHoU6VN8J2k8Rrj2qm X-Google-Smtp-Source: AGHT+IEWCC4hpoyQQVJAuUqw2ESqRolwckpXTH1hyDS1mEzDwU6iKL6pvTFIVlCY/xkQNJSs4AteQQ== X-Received: by 2002:a17:902:e552:b0:20c:5cdd:a9e with SMTP id d9443c01a7336-20e5a7968e8mr26784785ad.28.1729248891385; Fri, 18 Oct 2024 03:54:51 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:51 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , AKASHI Takahiro , Victor Shih , Lucas Lai Subject: [PATCH V23 15/16] mmc: sdhci-pci-gli: enable UHS-II mode for GL9755 Date: Fri, 18 Oct 2024 18:53:32 +0800 Message-Id: <20241018105333.4569-16-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih Changes are: * Disable GL9755 overcurrent interrupt when power on/off on UHS-II. * Enable the internal clock when do reset on UHS-II mode. * Increase timeout value before detecting UHS-II interface. * Add vendor settings fro UHS-II mode. * Remove sdhci_gli_enable_internal_clock functon unused clk_ctrl variable. * Make a function sdhci_gli_wait_software_reset_done() for gl9755 reset. * Remove unnecessary code from sdhci_gl9755_reset(). Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Signed-off-by: Lucas Lai Acked-by: Adrian Hunter --- Updates in V21: - Remove unnecessary code from sdhci_gl9755_reset(). Updates in V20: - Remove sdhci_gli_enable_internal_clock functon unused clk_ctrl variable. - Make a function sdhci_gli_wait_software_reset_done() for gl9755 reset. Updates in V19: - Add sdhci_gli_enable_internal_clock() to simplify the code in the sdhci_gl9755_reset(). Updates in V17: - Rname gl9755_overcurrent_event_enable() to sdhci_gli_overcurrent_event_enable(). Updates in V15: - Adjust gl9755_vendor_init() to the correct function. Updates in V13: - Ues uhs2_sd_tran to stead MMC_UHS2_SD_TRAN. Updates in V9: - Rename gl9755_pre_detect_init() to sdhci_gli_pre_detect_init(). - Rename gl9755_uhs2_reset_sd_tran() to sdhci_gli_uhs2_reset_sd_tran(). Updates in V8: - Use sdhci_get_vdd_value() to simplify code in gl9755_set_power(). - Use read_poll_timeout_atomic() to simplify code in sdhci_wait_clock_stable(). - Use read_poll_timeout_atomic() to simplify code in sdhci_gl9755_reset(). Updates in V7: - Drop using gl9755_post_attach_sd(). --- drivers/mmc/host/sdhci-pci-gli.c | 235 ++++++++++++++++++++++++++++++- 1 file changed, 234 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-= gli.c index 0f81586a19df..708138eecaa7 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -18,6 +18,7 @@ #include "sdhci-cqhci.h" #include "sdhci-pci.h" #include "cqhci.h" +#include "sdhci-uhs2.h" =20 /* Genesys Logic extra registers */ #define SDHCI_GLI_9750_WT 0x800 @@ -139,9 +140,36 @@ =20 #define PCI_GLI_9755_PLLSSC 0x68 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) +#define PCI_GLI_9755_PLLSSC_RTL BIT(24) +#define GLI_9755_PLLSSC_RTL_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) +#define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) +#define GLI_9755_PLLSSC_RECV_VALUE 0x0 +#define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) +#define GLI_9755_PLLSSC_TRAN_VALUE 0x3 + +#define PCI_GLI_9755_UHS2_PLL 0x6C +#define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) +#define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 +#define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) +#define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 +#define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) +#define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 =20 #define PCI_GLI_9755_SerDes 0x70 +#define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) +#define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 +#define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) +#define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 +#define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) +#define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB +#define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 #define PCI_GLI_9755_SCP_DIS BIT(19) +#define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) +#define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC +#define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) +#define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF =20 #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) @@ -779,6 +807,203 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *= slot) gl9755_wt_off(pdev); } =20 +static void gl9755_vendor_init(struct sdhci_host *host) +{ + struct sdhci_pci_slot *slot =3D sdhci_priv(host); + struct pci_dev *pdev =3D slot->chip->pdev; + u32 serdes; + u32 pllssc; + u32 uhs2_pll; + + gl9755_wt_on(pdev); + + pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_TRAN; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, + GLI_9755_UHS2_SERDES_TRAN_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_RECV; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, + GLI_9755_UHS2_SERDES_RECV_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_INTR; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, + GLI_9755_UHS2_SERDES_INTR_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_ZC1; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, + GLI_9755_UHS2_SERDES_ZC1_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_ZC2; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, + GLI_9755_UHS2_SERDES_ZC2_DEFAULT); + pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); + + pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); + uhs2_pll &=3D ~PCI_GLI_9755_UHS2_PLL_SSC; + uhs2_pll |=3D FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, + GLI_9755_UHS2_PLL_SSC_VALUE); + uhs2_pll &=3D ~PCI_GLI_9755_UHS2_PLL_DELAY; + uhs2_pll |=3D FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, + GLI_9755_UHS2_PLL_DELAY_VALUE); + uhs2_pll &=3D ~PCI_GLI_9755_UHS2_PLL_PDRST; + uhs2_pll |=3D FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, + GLI_9755_UHS2_PLL_PDRST_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); + + pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_RTL; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, + GLI_9755_PLLSSC_RTL_VALUE); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_TRANS_PASS; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, + GLI_9755_PLLSSC_TRANS_PASS_VALUE); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_RECV; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, + GLI_9755_PLLSSC_RECV_VALUE); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_TRAN; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, + GLI_9755_PLLSSC_TRAN_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); + + gl9755_wt_off(pdev); +} + +static void sdhci_gli_pre_detect_init(struct sdhci_host *host) +{ + /* Need more time on UHS2 detect flow */ + sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); +} + +static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bo= ol enable) +{ + u32 mask; + + mask =3D sdhci_readl(host, SDHCI_SIGNAL_ENABLE); + if (enable) + mask |=3D SDHCI_INT_BUS_POWER; + else + mask &=3D ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); + + mask =3D sdhci_readl(host, SDHCI_INT_ENABLE); + if (enable) + mask |=3D SDHCI_INT_BUS_POWER; + else + mask &=3D ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_INT_ENABLE); +} + +static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + u8 pwr =3D 0; + + if (mode !=3D MMC_POWER_OFF) { + pwr =3D sdhci_get_vdd_value(vdd); + if (!pwr) + WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); + pwr |=3D SDHCI_VDD2_POWER_180; + } + + if (host->pwr =3D=3D pwr) + return; + + host->pwr =3D pwr; + + if (pwr =3D=3D 0) { + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + } else { + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + pwr |=3D (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); + + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + sdhci_gli_overcurrent_event_enable(host, true); + } +} + +static bool sdhci_wait_clock_stable(struct sdhci_host *host) +{ + u16 clk =3D 0; + + if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STA= BLE), + 10, 20000, false, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)= ); + sdhci_dumpregs(host); + return false; + } + return true; +} + +static void sdhci_gli_enable_internal_clock(struct sdhci_host *host) +{ + u16 ctrl2; + + ctrl2 =3D sdhci_readw(host, SDHCI_HOST_CONTROL2); + + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); + + if (!((ctrl2 & SDHCI_CTRL_V4_MODE) && + (ctrl2 & SDHCI_CTRL_UHS2_ENABLE))) { + sdhci_wait_clock_stable(host); + sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); + } +} + +static int sdhci_gli_wait_software_reset_done(struct sdhci_host *host, u8 = mask) +{ + u8 rst; + + /* hw clears the bit when it's done */ + if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask), + 10, 100000, false, host, SDHCI_SOFTWARE_RESET)) { + pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (in= t)mask); + sdhci_dumpregs(host); + /* manual clear */ + sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); + return -ETIMEDOUT; + } + + return 0; +} + +static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) +{ + /* do this on UHS2 mode */ + if (host->mmc->uhs2_sd_tran) { + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + sdhci_uhs2_clear_set_irqs(host, + SDHCI_INT_ALL_MASK, + SDHCI_UHS2_INT_ERROR_MASK); + } +} + +static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) +{ + /* need internal clock */ + if (mask & SDHCI_RESET_ALL) + sdhci_gli_enable_internal_clock(host); + + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + + /* reset sd-tran on UHS2 mode if need to reset cmd/data */ + if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) + sdhci_gli_uhs2_reset_sd_tran(host); + + if (mask & SDHCI_RESET_ALL) + host->clock =3D 0; + + sdhci_gli_wait_software_reset_done(host, mask); +} + static inline void gl9767_vhs_read(struct pci_dev *pdev) { u32 vhs_enable; @@ -1086,6 +1311,7 @@ static int gli_probe_slot_gl9755(struct sdhci_pci_slo= t *slot) gli_pcie_enable_msi(slot); slot->host->mmc->caps2 |=3D MMC_CAP2_NO_SDIO; sdhci_enable_v4_mode(host); + gl9755_vendor_init(host); =20 return 0; } @@ -1524,17 +1750,24 @@ static const struct sdhci_ops sdhci_gl9755_ops =3D { .read_w =3D sdhci_gli_readw, .read_b =3D sdhci_gli_readb, .set_clock =3D sdhci_gl9755_set_clock, + .set_power =3D gl9755_set_power, .enable_dma =3D sdhci_pci_enable_dma, .set_bus_width =3D sdhci_set_bus_width, - .reset =3D sdhci_reset, + .reset =3D sdhci_gl9755_reset, .set_uhs_signaling =3D sdhci_set_uhs_signaling, .voltage_switch =3D sdhci_gli_voltage_switch, + .dump_uhs2_regs =3D sdhci_uhs2_dump_regs, + .set_timeout =3D sdhci_uhs2_set_timeout, + .irq =3D sdhci_uhs2_irq, + .uhs2_pre_detect_init =3D sdhci_gli_pre_detect_init, }; =20 const struct sdhci_pci_fixes sdhci_gl9755 =3D { .quirks =3D SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 =3D SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot =3D gli_probe_slot_gl9755, + .add_host =3D sdhci_pci_uhs2_add_host, + .remove_host =3D sdhci_pci_uhs2_remove_host, .ops =3D &sdhci_gl9755_ops, #ifdef CONFIG_PM_SLEEP .resume =3D sdhci_pci_gli_resume, --=20 2.25.1 From nobody Tue Nov 26 11:53:55 2024 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C06D2076A5; Fri, 18 Oct 2024 10:54:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248898; cv=none; b=PGYljJVF5oIsmL0/p9A7yIa/5iwrkVZ0gyiYCBQQ9q7dEl1JN/l4ciWH8JRcGw9F+wmI23n07nvhYJnNKNICAQeUViR2V6RmKgOjlxSCbq85jL/npMYzS0xSrp72YnIGrIcy1rfx9zG9sVzygo3jp7Ajdo5nBvv4Z2aa/c+TlNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729248898; c=relaxed/simple; bh=qmf9WfIviTtJwSgU5Q0mUQTSQ+PhALIXkUuHCsZsb04=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lWatHwIZsFuUeBrLtrRUcqWi2SdUJ1gFpfgqBLX1yUmEgUbMFl4AEJ4DyYH+uvO7+RjcHBWlPLqU4wJ1M6SrRqPLNYdkNzwo/wSsOyN5c3+5iop4qpVbZAF2lBWtztKQwxDg+fc4Ka9WjodMl8NJVp+U+aQsRdEUBBGOolP7WAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DyoCebT0; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DyoCebT0" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-20c693b68f5so21566425ad.1; Fri, 18 Oct 2024 03:54:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729248896; x=1729853696; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gbe7qhvT8ntO58X7PAXaQ3B+VwyPxi6oPgIOkOOFc4A=; b=DyoCebT0qhdsaQoYcj36G2CTx/ueX0SImtsaFYGbPHPpN4zRhGpqWto3/Y0cNGYYnm xia8ZXgzxWlAckLmrQS6Ujt2o7jJrc3eeGt1WYA0sw4NYznbhAhV91LiVGKnimklag4q CvMhWNmiOCopow3UQH8dw+heO4eXupxPZiM3Q88OFT4bMlQrMMeYMmpWjgk3sjRciLe1 1mY/1J7JG4lIAmuDpfAKifLycnJtnAoTmUldKCQNi3bSwUiNte5y5nk5C4sQJ+j902h6 M+wZXSixSAyT3/dZF58WifcrXsBfxZMAKGywCpV2viN0IkLVzQyyRhGhrdYrL1bZhpHv Xjsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729248896; x=1729853696; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gbe7qhvT8ntO58X7PAXaQ3B+VwyPxi6oPgIOkOOFc4A=; b=CHHprBemU+V9nplmUcMi6tFXabmmrS/Flz+L4MaJC547kx6ou49NdNGElpgbTxoCC2 E3yEadYvJar+UH+8t2pYJG6gmTDrLFtLlcVt+n1u49TMtJvXMJLRkfk52zuEbRtQRb0H utCRQbNKH+atuASOsFlPPuV08WJsbss0UeqRD/zfLic0PETVJekW2VUQ4js9GKDyKo3e PkqbkShEL5KCQERBMefP3Mi+hxSvUEY3eaol9Xop2NC/1KQCkbIsSoul8435HLzgNqpX 5v6sZ7+GV4lVuASHuJkOn+I3HsjT7FkUEWadDenpIjyOx2wRFgrpUb8f1+xC9doS8Kdt O91A== X-Forwarded-Encrypted: i=1; AJvYcCUmz8m+SRoMX/ytQYTV2WYCzfJua+JRKm3T4YKANzZ+Y6xmcWBMC1N8JUclP56SBJ41qjNdzi6XYHEYMZQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxlmuAf44mqQv0Mmkt55VnDPgKZGHzUZwNVIUx+aPaidnPswKJA nMCWRIBJcbzYmLtnS5okVhrcds9IwX8/E3MRnLSyElrfjQuGpxU6 X-Google-Smtp-Source: AGHT+IFgvOo4jI1IkmyMPwudwrlZSTUtS0Cp+rO5DDOEKe6bcfUVkFDpC5zoHRcT1p1Vt/zjNsaMdA== X-Received: by 2002:a17:902:f68f:b0:20c:ce1f:13bd with SMTP id d9443c01a7336-20e5a75a5b9mr22736325ad.18.1729248896001; Fri, 18 Oct 2024 03:54:56 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:47a:11ee:3789:3bcf:d64f:bc9a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e5a8fa20esm10237455ad.234.2024.10.18.03.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 03:54:55 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, Lucas.Lai@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih , Lucas Lai Subject: [PATCH V23 16/16] mmc: sdhci-pci-gli: enable UHS-II mode for GL9767 Date: Fri, 18 Oct 2024 18:53:33 +0800 Message-Id: <20241018105333.4569-17-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241018105333.4569-1-victorshihgli@gmail.com> References: <20241018105333.4569-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih Changes are: * Enable the internal clock when do reset on UHS-II mode. * Increase timeout value before detecting UHS-II interface. * Add vendor settings for UHS-II mode. * Use the function sdhci_gli_wait_software_reset_done() for gl9767 reset. * Remove unnecessary code from sdhci_gl9767_reset(). Signed-off-by: Ben Chuang Signed-off-by: Victor Shih Signed-off-by: Lucas Lai -- Updates in V21: - Remove unnecessary code from sdhci_gl9767_reset(). Updates in V20: - Use the function sdhci_gli_wait_software_reset_done() for gl9767 reset. Updates in V19: - Use sdhci_gli_enable_internal_clock() to simplify the code in the sdhci_gl9767_reset(). - Directly reading the SDHCI_PRESENT_STATE register to replace the get_cd() avoids the possibility of the get_cd() sleeping in the sdhci_gl9767_set_card_detect_debounce_time(). - Refine the position of gli_set_9767() in the sdhci_gl9767_reset(). Updates in V18: - Add new register settings for gl9767. - Add card_event in the sdhci_ops for gl9767. - Add sdhci_gl9767_set_card_detect_debounce_time() to configure the gl9767. - Adjust the sdhci_gl9767_reset() process for gl9767. Updates in V17: - Use mmc_card_uhs2() to simplify the code in the sdhci_gl9767_reset(). - Use mmc_card_uhs2() to simplify the code in the sdhci_gl9767_set_power(). - Add sdhci_gli_overcurrent_event_enable() to sdhci_gl9767_set_power(). Updates in V15: - Add gl9767 to support uhs2 function. Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-pci-gli.c | 202 ++++++++++++++++++++++++++++++- 1 file changed, 201 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-= gli.c index 708138eecaa7..cf2486ec7b9a 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -174,6 +174,15 @@ #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) =20 +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL 0x508 +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK BIT(0) +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE GENMASK(21, 16) +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE 0x= 05 +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE 0= x3F +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE GENMASK(2= 3, 22) +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS 0x2 +#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS 0x3 + #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) =20 @@ -210,6 +219,13 @@ #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) =20 +#define PCIE_GLI_9767_RESET_REG 0x8E4 +#define PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET BIT(0) + +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1 0x90C +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR GENMASK(31, 29) +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE 0x3 + #define PCIE_GLI_9767_SDHC_CAP 0x91C #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) =20 @@ -228,9 +244,15 @@ #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) =20 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL BIT(8) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 =20 +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2 0x948 +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING GENMASK(22, 2= 1) +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE 0x0 + #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) =20 @@ -240,6 +262,28 @@ #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL= _EN BIT(0) =20 +#define PCIE_GLI_9767_UHS2_CTL1 0x95C +#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS BIT(5) +#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE 0x1 +#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL BIT(6) +#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE 0x1 +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN GENMASK(10, 7) +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE 0x3 +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV GENMASK(14, 11) +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE 0xf +#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS GENMASK(16, 15) +#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE 0x0 +#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV GENMASK(18, 17) +#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE 0x0 +#define PCIE_GLI_9767_UHS2_CTL1_PDRST BIT(25) +#define PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE 0x1 + +#define PCIE_GLI_9767_UHS2_CTL2 0x964 +#define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0) +#define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb +#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6) +#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1 + #define GLI_MAX_TUNING_LOOP 40 =20 /* Genesys Logic chipset */ @@ -1155,6 +1199,31 @@ static void sdhci_gl9767_set_clock(struct sdhci_host= *host, unsigned int clock) gl9767_vhs_read(pdev); } =20 +static void sdhci_gl9767_set_card_detect_debounce_time(struct sdhci_host *= host) +{ + u32 value; + + value =3D sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); + value &=3D ~(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE | + SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE); + if (sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) + value |=3D FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, + SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE) | + FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, + SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS); + else + value |=3D FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, + SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE) | + FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, + SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS); + sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); +} + +static void sdhci_gl9767_card_event(struct sdhci_host *host) +{ + sdhci_gl9767_set_card_detect_debounce_time(host); +} + static void gli_set_9767(struct sdhci_host *host) { u32 value; @@ -1162,6 +1231,12 @@ static void gli_set_9767(struct sdhci_host *host) value =3D sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE); value &=3D ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE); + + value =3D sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); + value &=3D ~SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK; + sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); + + sdhci_gl9767_set_card_detect_debounce_time(host); } =20 static void gl9767_hw_setting(struct sdhci_pci_slot *slot) @@ -1200,7 +1275,43 @@ static void gl9767_hw_setting(struct sdhci_pci_slot = *slot) =20 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) { - sdhci_reset(host, mask); + struct sdhci_pci_slot *slot =3D sdhci_priv(host); + struct pci_dev *pdev =3D slot->chip->pdev; + u32 value; + + /* need internal clock */ + if (mask & SDHCI_RESET_ALL) { + sdhci_gli_enable_internal_clock(host); + + gl9767_vhs_write(pdev); + + pci_read_config_dword(pdev, PCIE_GLI_9767_RESET_REG, &value); + value &=3D ~PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET; + pci_write_config_dword(pdev, PCIE_GLI_9767_RESET_REG, value); + + if (read_poll_timeout_atomic(pci_read_config_dword, value, + !(value & PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET), + 1, 5, true, pdev, PCIE_GLI_9767_RESET_REG, &value)) { + pr_warn("%s: %s: Reset SDHC AHB and TL-AMBA failure.\n", + __func__, mmc_hostname(host->mmc)); + gl9767_vhs_read(pdev); + return; + } + gl9767_vhs_read(pdev); + } + + if (mmc_card_uhs2(host->mmc)) { + if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) { + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + sdhci_gli_uhs2_reset_sd_tran(host); + sdhci_gli_wait_software_reset_done(host, mask); + } else { + sdhci_uhs2_reset(host, mask); + } + } else { + sdhci_reset(host, mask); + } + gli_set_9767(host); } =20 @@ -1291,6 +1402,86 @@ static int gl9767_init_sd_express(struct mmc_host *m= mc, struct mmc_ios *ios) return 0; } =20 +static void gl9767_vendor_init(struct sdhci_host *host) +{ + struct sdhci_pci_slot *slot =3D sdhci_priv(host); + struct pci_dev *pdev =3D slot->chip->pdev; + u32 value; + + gl9767_vhs_write(pdev); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, &value); + value |=3D FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR, + PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, value); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value); + value |=3D FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING, + PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, value); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, &value); + value |=3D FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS, + PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL, + PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN, + PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV, + PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS, + PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV, + PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRST, + PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, value); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); + value |=3D FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC, + PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL, + PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); + + gl9767_vhs_read(pdev); +} + +static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char = mode, unsigned short vdd) +{ + struct sdhci_pci_slot *slot =3D sdhci_priv(host); + struct pci_dev *pdev =3D slot->chip->pdev; + u32 value; + + if (mmc_card_uhs2(host->mmc)) { + gl9767_vhs_write(pdev); + + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); + value |=3D PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | + PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL; + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); + + gl9767_vhs_read(pdev); + + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_uhs2_set_power(host, mode, vdd); + sdhci_gli_overcurrent_event_enable(host, true); + } else { + gl9767_vhs_write(pdev); + + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); + value &=3D ~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | + PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL); + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); + + gl9767_vhs_read(pdev); + + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_set_power(host, mode, vdd); + sdhci_gli_overcurrent_event_enable(host, true); + } +} + static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) { struct sdhci_host *host =3D slot->host; @@ -1327,6 +1518,7 @@ static int gli_probe_slot_gl9767(struct sdhci_pci_slo= t *slot) host->mmc->caps2 |=3D MMC_CAP2_SD_EXP; host->mmc_host_ops.init_sd_express =3D gl9767_init_sd_express; sdhci_enable_v4_mode(host); + gl9767_vendor_init(host); =20 return 0; } @@ -1830,12 +2022,20 @@ static const struct sdhci_ops sdhci_gl9767_ops =3D { .reset =3D sdhci_gl9767_reset, .set_uhs_signaling =3D sdhci_set_uhs_signaling, .voltage_switch =3D sdhci_gl9767_voltage_switch, + .dump_uhs2_regs =3D sdhci_uhs2_dump_regs, + .set_timeout =3D sdhci_uhs2_set_timeout, + .irq =3D sdhci_uhs2_irq, + .set_power =3D sdhci_gl9767_set_power, + .uhs2_pre_detect_init =3D sdhci_gli_pre_detect_init, + .card_event =3D sdhci_gl9767_card_event, }; =20 const struct sdhci_pci_fixes sdhci_gl9767 =3D { .quirks =3D SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 =3D SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot =3D gli_probe_slot_gl9767, + .add_host =3D sdhci_pci_uhs2_add_host, + .remove_host =3D sdhci_pci_uhs2_remove_host, .ops =3D &sdhci_gl9767_ops, #ifdef CONFIG_PM_SLEEP .resume =3D sdhci_pci_gli_resume, --=20 2.25.1