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charset="utf-8" For cases when the mux shares reset line with other chips we cannot use it always when channel selection or deselection times out, because it could break them without proper init/probe. The property is necessary, because reset lines are board-specific. Signed-off-by: Wojciech Siudy --- Changelog: v5: * Declare dependency of a new property --- .../devicetree/bindings/i2c/i2c-mux-pca954x.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml b/D= ocumentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml index 9aa0585200c9..37882a5a8c87 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml @@ -63,6 +63,11 @@ properties: necessary for example, if there are several multiplexers on the bus = and the devices behind them use same I2C addresses. =20 + i2c-mux-timeout-reset: + type: boolean + description: Sends reset pulse if channel selection or deselection tim= es + out. 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charset="utf-8" If the channel selection or deselection times out, it indicates a failure in the mux's I2C subsystem. Without sending a reset pulse, a power-on-reset of the entire device would be required to restore communication. The datasheet specifies a minimum hold time of 4 ns for the reset pulse, but due to the path's capacitance and themux having its own clock, it is recommended to extend this to approximately 1 us. This option can be enabled using the i2c-mux-timeout-reset property in the device tree and should only be used if the reset line is not shared with other devices. Signed-off-by: Wojciech Siudy --- Changelog: v2: * Removed mail header from the commit log * Decreased reset pulse hold time from 10 to 1 ms v3: * Make this functionality enabled by appropriate property in devicetree v4: * Fix missing condition check from devicetree --- drivers/i2c/muxes/i2c-mux-pca954x.c | 51 ++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mu= x-pca954x.c index 6f84018258c4..316048b0011d 100644 --- a/drivers/i2c/muxes/i2c-mux-pca954x.c +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c @@ -110,6 +110,7 @@ struct pca954x { u8 last_chan; /* last register value */ /* MUX_IDLE_AS_IS, MUX_IDLE_DISCONNECT or >=3D 0 for channel */ s32 idle_state; + u8 timeout_reset; =20 struct i2c_client *client; =20 @@ -316,6 +317,30 @@ static u8 pca954x_regval(struct pca954x *data, u8 chan) return 1 << chan; } =20 +static void pca954x_reset_deassert(struct pca954x *data) +{ + if (data->reset_cont) + reset_control_deassert(data->reset_cont); + else + gpiod_set_value_cansleep(data->reset_gpio, 0); +} + +static void pca954x_reset_assert(struct pca954x *data) +{ + if (data->reset_cont) + reset_control_assert(data->reset_cont); + else + gpiod_set_value_cansleep(data->reset_gpio, 1); +} + +static void pca954x_reset_mux(struct pca954x *data) +{ + dev_warn(&data->client->dev, "resetting the device\n"); + pca954x_reset_assert(data); + udelay(1); + pca954x_reset_deassert(data); +} + static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan) { struct pca954x *data =3D i2c_mux_priv(muxc); @@ -329,6 +354,9 @@ static int pca954x_select_chan(struct i2c_mux_core *mux= c, u32 chan) ret =3D pca954x_reg_write(muxc->parent, client, regval); data->last_chan =3D ret < 0 ? 0 : regval; } + if (ret =3D=3D -ETIMEDOUT && (data->reset_cont || data->reset_gpio) && + data->timeout_reset) + pca954x_reset_mux(data); =20 return ret; } @@ -338,6 +366,7 @@ static int pca954x_deselect_mux(struct i2c_mux_core *mu= xc, u32 chan) struct pca954x *data =3D i2c_mux_priv(muxc); struct i2c_client *client =3D data->client; s32 idle_state; + int ret =3D 0; =20 idle_state =3D READ_ONCE(data->idle_state); if (idle_state >=3D 0) @@ -347,13 +376,16 @@ static int pca954x_deselect_mux(struct i2c_mux_core *= muxc, u32 chan) if (idle_state =3D=3D MUX_IDLE_DISCONNECT) { /* Deselect active channel */ data->last_chan =3D 0; - return pca954x_reg_write(muxc->parent, client, - data->last_chan); + ret =3D pca954x_reg_write(muxc->parent, client, data->last_chan); + if (ret =3D=3D -ETIMEDOUT && + (data->reset_cont || data->reset_gpio) && + data->timeout_reset) + pca954x_reset_mux(data); } =20 /* otherwise leave as-is */ =20 - return 0; + return ret; } =20 static ssize_t idle_state_show(struct device *dev, @@ -543,14 +575,6 @@ static int pca954x_get_reset(struct device *dev, struc= t pca954x *data) return 0; } =20 -static void pca954x_reset_deassert(struct pca954x *data) -{ - if (data->reset_cont) - reset_control_deassert(data->reset_cont); - else - gpiod_set_value_cansleep(data->reset_gpio, 0); -} - /* * I2C init/probing/exit functions */ @@ -625,6 +649,11 @@ static int pca954x_probe(struct i2c_client *client) data->idle_state =3D MUX_IDLE_DISCONNECT; } =20 + if (device_property_read_bool(dev, "i2c-mux-timeout-reset")) + data->timeout_reset =3D 1; + else + data->timeout_reset =3D 0; + /* * Write the mux register at addr to verify * that the mux is in fact present. This also --=20 2.34.1