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Fri, 18 Oct 2024 01:11:56 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , jason-ch chen , Chen Zhong , Flora Fu , Alexandre Mergnat Cc: Yassine Oudjana , Yassine Oudjana , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 5/6] regulator: Add driver for MediaTek MT6328 PMIC regulators Date: Fri, 18 Oct 2024 11:10:47 +0300 Message-ID: <20241018081050.23592-6-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241018081050.23592-1-y.oudjana@protonmail.com> References: <20241018081050.23592-1-y.oudjana@protonmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a driver for the regulators on the MT6328 PMIC. Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6328-regulator.c | 479 +++++++++++++++++++++ include/linux/regulator/mt6328-regulator.h | 49 +++ 4 files changed, 538 insertions(+) create mode 100644 drivers/regulator/mt6328-regulator.c create mode 100644 include/linux/regulator/mt6328-regulator.h diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 249933d6388dd..e9b9faff67f3a 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -862,6 +862,15 @@ config REGULATOR_MT6323 This driver supports the control of different power rails of device through regulator interface. =20 +config REGULATOR_MT6328 + tristate "MediaTek MT6328 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6328 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6331 tristate "MediaTek MT6331 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 9b69546fb3f65..c1a5a44413198 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_REGULATOR_MPQ7920) +=3D mpq7920.o obj-$(CONFIG_REGULATOR_MT6311) +=3D mt6311-regulator.o obj-$(CONFIG_REGULATOR_MT6315) +=3D mt6315-regulator.o obj-$(CONFIG_REGULATOR_MT6323) +=3D mt6323-regulator.o +obj-$(CONFIG_REGULATOR_MT6328) +=3D mt6328-regulator.o obj-$(CONFIG_REGULATOR_MT6331) +=3D mt6331-regulator.o obj-$(CONFIG_REGULATOR_MT6332) +=3D mt6332-regulator.o obj-$(CONFIG_REGULATOR_MT6357) +=3D mt6357-regulator.o diff --git a/drivers/regulator/mt6328-regulator.c b/drivers/regulator/mt632= 8-regulator.c new file mode 100644 index 0000000000000..e15a64404f494 --- /dev/null +++ b/drivers/regulator/mt6328-regulator.c @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT6328 regulator driver + * Based on MT6323 driver. + * + * Copyright (c) 2016 MediaTek Inc. + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT6328_LDO_TABLE_MODE_NORMAL 0 +#define MT6328_LDO_TABLE_MODE_LP 1 + +/* + * MT6328 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +struct mt6328_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +#define MT6328_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + }, \ + .qi =3D BIT(13), \ + .vselon_reg =3D voselon, \ + .vselctrl_reg =3D vosel_ctrl, \ + .vselctrl_mask =3D BIT(1), \ +} + +#define MT6328_LDO_RANGE(match, vreg, min, max, step, volt_ranges, \ + enreg, enbit, vosel, vosel_mask, _modeset_reg, \ + _modeset_mask) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6328_LDO_TABLE(match, vreg, ldo_volt_table, enreg, enbit, \ + vosel, vosel_mask, _modeset_reg, _modeset_mask)\ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6328_REG_FIXED(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +static const struct linear_range buck_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000) +}; + +static const struct linear_range buck_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(600000, 0, 0x7f, 6250) +}; + +static const struct linear_range buck_volt_range3[] =3D { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 6250) +}; + +static const unsigned int ldo_volt_table1[] =3D { + 1500000, 1800000, 2500000, 2800000 +}; + +static const unsigned int ldo_volt_table2[] =3D { + 3300000, 3400000, 3500000, 3600000 +}; + +static const unsigned int ldo_volt_table3[] =3D { + 0, 0, 0, 1800000, 1900000, 2000000, 2100000, 2200000 +}; + +static const unsigned int ldo_volt_table4[] =3D { + 1700000, 1800000, 1860000, 2760000, 3000000, 3100000 +}; + +static const unsigned int ldo_volt_table5[] =3D { + 1800000, 2900000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table6[] =3D { + 2900000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table7[] =3D { + 2500000, 2900000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table8[] =3D { + 1300000, 1800000, 2900000, 3300000 +}; + +static const unsigned int ldo_volt_table9[] =3D { + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table10[] =3D { + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table11[] =3D { + 900000, 1000000, 1100000, 1200000, 1300000, 1500000 +}; + +static const unsigned int ldo_volt_table12[] =3D { + 1200000, 1300000, 1500000, 1800000, 1825000 +}; + +static const unsigned int ldo_volt_table13[] =3D { + 1200000, 1300000, 1500000, 1800000 +}; + +static const unsigned int ldo_volt_table14[] =3D { + 1240000, 1390000, 1540000 +}; + +static const struct linear_range ldo_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250) +}; + +static int mt6328_get_status(struct regulator_dev *rdev) +{ + int ret; + u32 regval; + struct mt6328_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->desc.enable_reg, ®val); + if (ret !=3D 0) { + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); + return ret; + } + + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; +} + +static int mt6328_ldo_table_set_mode(struct regulator_dev *rdev, unsigned = int mode) +{ + int ret, val =3D 0; + struct mt6328_regulator_info *info =3D rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n", + info->desc.name); + return -EINVAL; + } + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val =3D MT6328_LDO_TABLE_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6328_LDO_TABLE_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6328_ldo_table_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6328_regulator_info *info =3D rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n", + info->desc.name); + return -EINVAL; + } + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_STANDBY; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6328_volt_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6328_get_status, +}; + +static const struct regulator_ops mt6328_volt_table_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6328_get_status, + .set_mode =3D mt6328_ldo_table_set_mode, + .get_mode =3D mt6328_ldo_table_get_mode, +}; + +static const struct regulator_ops mt6328_volt_fixed_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6328_get_status, + .set_mode =3D mt6328_ldo_table_set_mode, + .get_mode =3D mt6328_ldo_table_get_mode, +}; + +/* The array is indexed by id(MT6328_ID_XXX) */ +static struct mt6328_regulator_info mt6328_regulators[] =3D { + MT6328_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, + buck_volt_range1, MT6328_VPA_CON9, MT6328_VPA_CON11, 0x3f, + MT6328_VPA_CON12, MT6328_VPA_CON7), + MT6328_BUCK("buck_vproc", VPROC, 600000, 1393750, 6250, + buck_volt_range2, MT6328_VPROC_CON9, MT6328_VPA_CON11, 0x7f, + MT6328_VPROC_CON12, MT6328_VPROC_CON7), + MT6328_BUCK("buck_vcore1", VCORE1, 600000, 1393750, 6250, + buck_volt_range2, MT6328_VCORE1_CON9, MT6328_VCORE1_CON11, 0x7f, + MT6328_VCORE1_CON12, MT6328_VCORE1_CON7), + MT6328_BUCK("buck_vsys22", VSYS22, 1200000, 1993750, 6250, + buck_volt_range3, MT6328_VSYS22_CON9, MT6328_VSYS22_CON11, 0x7f, + MT6328_VSYS22_CON12, MT6328_VSYS22_CON7), + MT6328_BUCK("buck_vlte", VLTE, 600000, 1393750, 6250, + buck_volt_range2, MT6328_VLTE_CON9, MT6328_VLTE_CON11, 0x7f, + MT6328_VLTE_CON12, MT6328_VLTE_CON7), + MT6328_REG_FIXED("ldo_vaux18", VAUX18, MT6328_VAUX18_CON0, 1, 1800000, + MT6328_VAUX18_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vtcxo_0", VTCXO_0, MT6328_VTCXO_0_CON0, 1, 2800000, + MT6328_VTCXO_0_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vtcxo_1", VTCXO_1, MT6328_VTCXO_1_CON0, 1, 2800000, + MT6328_VTCXO_1_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vaud28", VAUD28, MT6328_VAUD28_CON0, 1, 2800000, + MT6328_VAUD28_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vcn28", VCN28, MT6328_VCN28_CON0, 1, 2800000, + MT6328_VCN28_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcama", VCAMA, ldo_volt_table1, + MT6328_VCAMA_CON0, 1, MT6328_ADLDO_ANA_CON5, 0x30, + 0, 0), + MT6328_LDO_TABLE("ldo_vcn33_bt", VCN33_BT, ldo_volt_table2, + MT6328_VCN33_CON2, 1, MT6328_ADLDO_ANA_CON6, 0x70, + MT6328_VCN33_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcn33_wifi", VCN33_WIFI, ldo_volt_table2, + MT6328_VCN33_CON1, 1, MT6328_ADLDO_ANA_CON6, 0x70, + MT6328_VCN33_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vusb33", VUSB33, MT6328_VUSB33_CON0, 1, 3300000, + MT6328_VUSB33_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vefuse", VEFUSE, ldo_volt_table3, + MT6328_VEFUSE_CON0, 1, MT6328_ADLDO_ANA_CON8, 0x70, + MT6328_VEFUSE_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vsim1", VSIM1, ldo_volt_table4, + MT6328_VSIM1_CON0, 1, MT6328_ADLDO_ANA_CON9, 0x70, + MT6328_VSIM1_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vsim2", VSIM2, ldo_volt_table4, + MT6328_VSIM2_CON0, 1, MT6328_ADLDO_ANA_CON10, 0x70, + MT6328_VSIM2_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vemc_3v3", VEMC_3V3, ldo_volt_table5, + MT6328_VEMC_3V3_CON0, 1, MT6328_ADLDO_ANA_CON11, 0x30, + MT6328_VEMC_3V3_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vmch", VMCH, ldo_volt_table6, + MT6328_VMCH_CON0, 1, MT6328_ADLDO_ANA_CON12, 0x30, + MT6328_VMCH_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vtref", VTREF, MT6328_VTREF_CON0, 1, 1800000, + 0, 0), + MT6328_LDO_TABLE("ldo_vmc", VMC, ldo_volt_table5, + MT6328_VMC_CON0, 1, MT6328_DLDO_ANA_CON0, 0x30, + MT6328_VMC_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcamaf", VCAMAF, ldo_volt_table9, + MT6328_VCAMAF_CON0, 1, MT6328_DLDO_ANA_CON1, 0x70, + MT6328_VCAMAF_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vibr", VIBR, ldo_volt_table9, + MT6328_VIBR_CON0, 1, MT6328_DLDO_ANA_CON2, 0x70, + MT6328_VIBR_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vio28", VIO28, MT6328_VIO28_CON0, 1, 2800000, + MT6328_VIO28_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vgp1", VGP1, ldo_volt_table10, + MT6328_VGP1_CON0, 1, MT6328_DLDO_ANA_CON4, 0x70, + MT6328_VGP1_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcamd", VCAMD, ldo_volt_table11, + MT6328_VCAM_CON0, 1, MT6328_SLDO_ANA_CON2, 0x70, + MT6328_VCAM_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vrf18_0", VRF18_0, MT6328_VRF18_0_CON0, 1, 1825000, + MT6328_VRF18_0_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vrf18_1", VRF18_1, ldo_volt_table12, + MT6328_VRF18_1_CON0, 1, MT6328_SLDO_ANA_CON4, 0x30, + MT6328_VRF18_1_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vio18", VIO18, MT6328_VIO18_CON0, 1, 1800000, + MT6328_VIO18_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vcn18", VCN18, MT6328_VCN18_CON0, 1, 1800000, + MT6328_VCN18_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcamio", VCAMIO, ldo_volt_table13, + MT6328_VCAMIO_CON0, 1, MT6328_SLDO_ANA_CON7, 0x30, + MT6328_VCAMIO_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcamio", VCAMIO, ldo_volt_table13, + MT6328_VCAMIO_CON0, 1, MT6328_SLDO_ANA_CON7, 0x30, + MT6328_VCAMIO_CON0, BIT(0)), + MT6328_LDO_RANGE("ldo_vsram", VSRAM, 700000, 1493750, 6250, + ldo_volt_range1, MT6328_VSRAM_CON9, 1, MT6328_SLDO_ANA_CON9, + 0x7f, MT6328_LDO_VSRAM_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vm", VM, ldo_volt_table14, + MT6328_VM_CON0, 1, MT6328_SLDO_ANA_CON0, 0x3, + MT6328_VM_CON0, BIT(0)), +}; + +static int mt6328_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6328 =3D dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i =3D 0; i < MT6328_MAX_REGULATOR; i++) { + if (mt6328_regulators[i].vselctrl_reg) { + if (regmap_read(mt6328->regmap, + mt6328_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6328_regulators[i].vselctrl_mask) { + mt6328_regulators[i].desc.vsel_reg =3D + mt6328_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6328_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6328 =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_config config =3D {}; + struct regulator_dev *rdev; + int i; + + /* Query buck controller to select activated voltage register part */ + if (mt6328_set_buck_vosel_reg(pdev)) + return -EIO; + + for (i =3D 0; i < MT6328_MAX_REGULATOR; i++) { + config.dev =3D &pdev->dev; + config.driver_data =3D &mt6328_regulators[i]; + config.regmap =3D mt6328->regmap; + rdev =3D devm_regulator_register(&pdev->dev, + &mt6328_regulators[i].desc, &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6328_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + return 0; +} + +static const struct platform_device_id mt6328_platform_ids[] =3D { + { "mt6328-regulator" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6328_platform_ids); + +static struct platform_driver mt6328_regulator_driver =3D { + .driver =3D { + .name =3D "mt6328-regulator", + }, + .probe =3D mt6328_regulator_probe, + .id_table =3D mt6328_platform_ids, +}; + +module_platform_driver(mt6328_regulator_driver); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6328 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6328-regulator.h b/include/linux/reg= ulator/mt6328-regulator.h new file mode 100644 index 0000000000000..0f82aa88493b0 --- /dev/null +++ b/include/linux/regulator/mt6328-regulator.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016 MediaTek Inc. + * Copyright (c) 2022 Yassine Oudjana + */ + +#ifndef __LINUX_REGULATOR_MT6328_H +#define __LINUX_REGULATOR_MT6328_H + +enum { + MT6328_ID_VPA =3D 0, + MT6328_ID_VPROC, + MT6328_ID_VCORE1, + MT6328_ID_VSYS22, + MT6328_ID_VLTE, + MT6328_ID_VAUX18, + MT6328_ID_VTCXO_0, + MT6328_ID_VTCXO_1, + MT6328_ID_VAUD28, + MT6328_ID_VCN28, + MT6328_ID_VCAMA, + MT6328_ID_VCN33_BT, + MT6328_ID_VCN33_WIFI, + MT6328_ID_VUSB33, + MT6328_ID_VEFUSE, + MT6328_ID_VSIM1, + MT6328_ID_VSIM2, + MT6328_ID_VEMC_3V3, + MT6328_ID_VMCH, + MT6328_ID_VTREF, + MT6328_ID_VMC, + MT6328_ID_VCAMAF, + MT6328_ID_VIBR, + MT6328_ID_VIO28, + MT6328_ID_VGP1, + MT6328_ID_VCAMD, + MT6328_ID_VRF18_0, + MT6328_ID_VRF18_1, + MT6328_ID_VIO18, + MT6328_ID_VCN18, + MT6328_ID_VCAMIO, + MT6328_ID_VSRAM, + MT6328_ID_VM, + MT6328_ID_RG_MAX, +}; + +#define MT6328_MAX_REGULATOR MT6328_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6328_H */ --=20 2.47.0