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Fri, 18 Oct 2024 07:07:14 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 49I779rg019791; Fri, 18 Oct 2024 07:07:09 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 427j6mpjan-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 18 Oct 2024 07:07:09 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49I779Me019765; Fri, 18 Oct 2024 07:07:09 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 49I778MO019762; Fri, 18 Oct 2024 07:07:09 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id EA2B45299CC; Fri, 18 Oct 2024 12:37:07 +0530 (+0530) From: Soutrik Mukhopadhyay To: vkoul@kernel.org, kishon@kernel.org, konradybcio@kernel.org, andersson@kernel.org, simona@ffwll.ch, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_khsieh@quicinc.com, konrad.dybcio@linaro.org, quic_parellan@quicinc.com, quic_bjorande@quicinc.com Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH v5 2/5] phy: qcom: edp: Introduce aux_cfg array for version specific aux settings Date: Fri, 18 Oct 2024 12:37:03 +0530 Message-Id: <20241018070706.28980-3-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241018070706.28980-1-quic_mukhopad@quicinc.com> References: <20241018070706.28980-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r38blCsEIVEjFxZqkTzWI5r4V1rsskfj X-Proofpoint-ORIG-GUID: r38blCsEIVEjFxZqkTzWI5r4V1rsskfj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410180043 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In order to support different HW versions, introduce aux_cfg array to move v4 specific aux configuration settings. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay --- v2: Fixed review comments from Bjorn and Dmitry - Made aux_cfg array as const. v3: Fixed review comments from Dmitry - Used a for loop to write the dp_phy_aux_cfg registers. - Pre-defined the aux_cfg size to prevent any magic numbers. v4: No change v5: No change --- drivers/phy/qualcomm/phy-qcom-edp.c | 41 ++++++++++++----------------- 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index da2b32fb5b45..2ecff164ec44 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -32,16 +32,8 @@ #define DP_PHY_PD_CTL 0x001c #define DP_PHY_MODE 0x0020 =20 -#define DP_PHY_AUX_CFG0 0x0024 -#define DP_PHY_AUX_CFG1 0x0028 -#define DP_PHY_AUX_CFG2 0x002C -#define DP_PHY_AUX_CFG3 0x0030 -#define DP_PHY_AUX_CFG4 0x0034 -#define DP_PHY_AUX_CFG5 0x0038 -#define DP_PHY_AUX_CFG6 0x003C -#define DP_PHY_AUX_CFG7 0x0040 -#define DP_PHY_AUX_CFG8 0x0044 -#define DP_PHY_AUX_CFG9 0x0048 +#define DP_AUX_CFG_SIZE 10 +#define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) =20 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 =20 @@ -90,6 +82,7 @@ struct phy_ver_ops { =20 struct qcom_edp_phy_cfg { bool is_edp; + const u8 *aux_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; @@ -186,11 +179,15 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_p= hy_swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 +static const u8 edp_phy_aux_cfg_v4[10] =3D { + 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); + u8 aux_cfg[DP_AUX_CFG_SIZE]; int ret; - u8 cfg8; =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); if (ret) @@ -200,6 +197,8 @@ static int qcom_edp_phy_init(struct phy *phy) if (ret) goto out_disable_supplies; =20 + memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); @@ -222,22 +221,12 @@ static int qcom_edp_phy_init(struct phy *phy) * even needed. */ if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) - cfg8 =3D 0xb7; - else - cfg8 =3D 0x37; + aux_cfg[8] =3D 0xb7; =20 writel(0xfc, edp->edp + DP_PHY_MODE); =20 - writel(0x00, edp->edp + DP_PHY_AUX_CFG0); - writel(0x13, edp->edp + DP_PHY_AUX_CFG1); - writel(0x24, edp->edp + DP_PHY_AUX_CFG2); - writel(0x00, edp->edp + DP_PHY_AUX_CFG3); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); - writel(0x26, edp->edp + DP_PHY_AUX_CFG5); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); - writel(0x03, edp->edp + DP_PHY_AUX_CFG7); - writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); - writel(0x03, edp->edp + DP_PHY_AUX_CFG9); + for (int i =3D 0; i < DP_AUX_CFG_SIZE; i++) + writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); =20 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | @@ -519,16 +508,19 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = =3D { }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { .is_edp =3D true, + .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; @@ -707,6 +699,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D= { }; =20 static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, }; --=20 2.17.1