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charset="utf-8" Add compatible string for the supported eDP PHY on sa8775p platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Soutrik Mukhopadhyay --- v2: No change v3: No change v4: No change v5: No change --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 4e15d90d08b0..293fb6a9b1c3 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,sa8775p-edp-phy - qcom,sc7280-edp-phy - qcom,sc8180x-edp-phy - qcom,sc8280xp-dp-phy --=20 2.17.1 From nobody Tue Nov 26 10:31:56 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73E84188003; Fri, 18 Oct 2024 07:07:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" In order to support different HW versions, introduce aux_cfg array to move v4 specific aux configuration settings. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay --- v2: Fixed review comments from Bjorn and Dmitry - Made aux_cfg array as const. v3: Fixed review comments from Dmitry - Used a for loop to write the dp_phy_aux_cfg registers. - Pre-defined the aux_cfg size to prevent any magic numbers. v4: No change v5: No change --- drivers/phy/qualcomm/phy-qcom-edp.c | 41 ++++++++++++----------------- 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index da2b32fb5b45..2ecff164ec44 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -32,16 +32,8 @@ #define DP_PHY_PD_CTL 0x001c #define DP_PHY_MODE 0x0020 =20 -#define DP_PHY_AUX_CFG0 0x0024 -#define DP_PHY_AUX_CFG1 0x0028 -#define DP_PHY_AUX_CFG2 0x002C -#define DP_PHY_AUX_CFG3 0x0030 -#define DP_PHY_AUX_CFG4 0x0034 -#define DP_PHY_AUX_CFG5 0x0038 -#define DP_PHY_AUX_CFG6 0x003C -#define DP_PHY_AUX_CFG7 0x0040 -#define DP_PHY_AUX_CFG8 0x0044 -#define DP_PHY_AUX_CFG9 0x0048 +#define DP_AUX_CFG_SIZE 10 +#define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) =20 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 =20 @@ -90,6 +82,7 @@ struct phy_ver_ops { =20 struct qcom_edp_phy_cfg { bool is_edp; + const u8 *aux_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; @@ -186,11 +179,15 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_p= hy_swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 +static const u8 edp_phy_aux_cfg_v4[10] =3D { + 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); + u8 aux_cfg[DP_AUX_CFG_SIZE]; int ret; - u8 cfg8; =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); if (ret) @@ -200,6 +197,8 @@ static int qcom_edp_phy_init(struct phy *phy) if (ret) goto out_disable_supplies; =20 + memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); @@ -222,22 +221,12 @@ static int qcom_edp_phy_init(struct phy *phy) * even needed. */ if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) - cfg8 =3D 0xb7; - else - cfg8 =3D 0x37; + aux_cfg[8] =3D 0xb7; =20 writel(0xfc, edp->edp + DP_PHY_MODE); =20 - writel(0x00, edp->edp + DP_PHY_AUX_CFG0); - writel(0x13, edp->edp + DP_PHY_AUX_CFG1); - writel(0x24, edp->edp + DP_PHY_AUX_CFG2); - writel(0x00, edp->edp + DP_PHY_AUX_CFG3); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); - writel(0x26, edp->edp + DP_PHY_AUX_CFG5); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); - writel(0x03, edp->edp + DP_PHY_AUX_CFG7); - writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); - writel(0x03, edp->edp + DP_PHY_AUX_CFG9); + for (int i =3D 0; i < DP_AUX_CFG_SIZE; i++) + writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); =20 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | @@ -519,16 +508,19 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = =3D { }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; 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charset="utf-8" Add support for eDP PHY v5 found on the Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay --- v2: Fixed review comments from Dmitry - Reused edp_swing_hbr_rbr and edp_swing_hbr2_hbr3 for v5. v3: No change v4: No change v5: No change --- drivers/phy/qualcomm/phy-qcom-edp.c | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 2ecff164ec44..f1b51018683d 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -183,6 +183,31 @@ static const u8 edp_phy_aux_cfg_v4[10] =3D { 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 }; =20 +static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { + { 0x05, 0x11, 0x17, 0x1d }, + { 0x05, 0x11, 0x18, 0xff }, + { 0x06, 0x11, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] =3D { + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x0b, 0x15, 0x19, 0xff }, + { 0x0e, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v5 =3D { + .swing_hbr_rbr =3D &edp_swing_hbr_rbr, + .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr_v5, + .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v5, +}; + +static const u8 edp_phy_aux_cfg_v5[10] =3D { + 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -507,6 +532,13 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = =3D { .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, }; =20 +static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg =3D { + .is_edp =3D false, + .aux_cfg =3D edp_phy_aux_cfg_v5, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; + static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, @@ -1101,6 +1133,7 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) } =20 static const struct of_device_id qcom_edp_phy_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-edp-phy", .data =3D &sa8775p_dp_phy_cfg, = }, { .compatible =3D "qcom,sc7280-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &sc8280xp_dp_phy_cfg,= }, --=20 2.17.1 From nobody Tue Nov 26 10:31:56 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A1B816EB4C; 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charset="utf-8" Add compatible string for the DisplayPort controller found on the Qualcomm SA8775P platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Soutrik Mukhopadhyay --- v2: No change v3: No change v4: No change v5: No change --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 97993feda193..a212f335d5ff 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,sa8775p-dp - qcom,sc7180-dp - qcom,sc7280-dp - qcom,sc7280-edp --=20 2.17.1 From nobody Tue Nov 26 10:31:56 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 157F7185B56; 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charset="utf-8" The Qualcomm SA8775P platform comes with 2 DisplayPort controllers for each mdss, having different base offsets than the previous SoCs. The support for all 4 DPTX have been added here, and validation of only MDSS0 DPTX0 and DPTX1 have been conducted. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay --- v2: No change v3: Fixed review comments from Konrad and Bjorn -Added all the necessary DPTX controllers for this platform. v4: Updated commit message to mention specifically about the validation of MDSS0 DPTX0 and DPTX1. v5: Aligned the register starting address for display port as part of device description with respect to other targets. --- drivers/gpu/drm/msm/dp/dp_display.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e1228fb093ee..c34362bc16ba 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -118,6 +118,14 @@ struct msm_dp_desc { bool wide_bus_supported; }; =20 +static const struct msm_dp_desc sa8775p_dp_descs[] =3D { + { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x22154000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x2215c000, .id =3D MSM_DP_CONTROLLER_3, .wide_bus_suppor= ted =3D true }, + {} +}; + static const struct msm_dp_desc sc7180_dp_descs[] =3D { { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, {} @@ -162,6 +170,7 @@ static const struct msm_dp_desc x1e80100_dp_descs[] =3D= { }; =20 static const struct of_device_id dp_dt_match[] =3D { + { .compatible =3D "qcom,sa8775p-dp", .data =3D &sa8775p_dp_descs }, { .compatible =3D "qcom,sc7180-dp", .data =3D &sc7180_dp_descs }, { .compatible =3D "qcom,sc7280-dp", .data =3D &sc7280_dp_descs }, { .compatible =3D "qcom,sc7280-edp", .data =3D &sc7280_dp_descs }, --=20 2.17.1