From nobody Tue Nov 26 11:36:00 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EDF620E31C; Fri, 18 Oct 2024 04:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729224035; cv=none; b=XQazbPZvO1zBBte4l0p269VNk8loRgt5knN3Q8I3X7+tdGDdlujl6zLAUdfRP+9cUmVYsBYeyNL5wGH4dcb1Vqjrk6Fb+PYXP1H3EKNQjdMF23VQdNY9wj7igFLkVifiNbDOWTfP2vGJmlmoq0L98ToeFlOxMPaclZ0mODfYI4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729224035; c=relaxed/simple; bh=NGz6KlkJSWDi/bWhwwnxcjNUC/FuKAov70R8NlezG6A=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Soj7c8k54QCy2ryUe+qw93rMPWZB3GzOp6pLWaA2nPIjaXltDIi19baLX7q8u7O1W8qjU6sr5vKbbq0Spza9sDYOiZQYOh1FYtZbq5R+MXeumSFRQHm3xcZ1KefPVs1jSqZzPA1TCZb1TeJ43SfheH3N8hFbM0L23nDbIqRT6dc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CE04C4CEC3; Fri, 18 Oct 2024 04:00:31 +0000 (UTC) From: Huacai Chen To: Huacai Chen Cc: loongarch@lists.linux.dev, Xuefeng Li , Guo Ren , Xuerui Wang , Jiaxun Yang , linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn, Huacai Chen , stable@vger.kernel.org, Kanglong Wang Subject: [PATCH] LoongArch: Make KASAN usable for variable cpu_vabits Date: Fri, 18 Oct 2024 12:00:24 +0800 Message-ID: <20241018040024.1060903-1-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.43.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, KASAN on LoongArch assume the CPU VA bits is 48, which is true for Loongson-3 series, but not for Loongson-2 series (only 40 or lower), this patch fix that issue and make KASAN usable for variable cpu_vabits. 1. Define XRANGE_SHADOW_SHIFT which means valid address length from VA_BITS to min(cpu_vabits, VA_BITS). 2. In kasan_mem_to_shadow() let DMW addresses which exceed XRANGE_SIZE to return kasan_early_shadow_page. Cc: stable@vger.kernel.org Signed-off-by: Kanglong Wang Signed-off-by: Huacai Chen --- arch/loongarch/include/asm/kasan.h | 2 +- arch/loongarch/mm/kasan_init.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/kasan.h b/arch/loongarch/include/as= m/kasan.h index cd6084f4e153..c6bce5fbff57 100644 --- a/arch/loongarch/include/asm/kasan.h +++ b/arch/loongarch/include/asm/kasan.h @@ -16,7 +16,7 @@ #define XRANGE_SHIFT (48) =20 /* Valid address length */ -#define XRANGE_SHADOW_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) +#define XRANGE_SHADOW_SHIFT min(cpu_vabits, VA_BITS) /* Used for taking out the valid address */ #define XRANGE_SHADOW_MASK GENMASK_ULL(XRANGE_SHADOW_SHIFT - 1, 0) /* One segment whole address space size */ diff --git a/arch/loongarch/mm/kasan_init.c b/arch/loongarch/mm/kasan_init.c index 427d6b1aec09..e5ecc8c12034 100644 --- a/arch/loongarch/mm/kasan_init.c +++ b/arch/loongarch/mm/kasan_init.c @@ -48,6 +48,10 @@ void *kasan_mem_to_shadow(const void *addr) return (void *)(kasan_early_shadow_page); =20 maddr &=3D XRANGE_SHADOW_MASK; + + if (maddr >=3D XRANGE_SIZE) + return (void *)(kasan_early_shadow_page); + switch (xrange) { case XKPRANGE_CC_SEG: offset =3D XKPRANGE_CC_SHADOW_OFFSET; --=20 2.43.5