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charset="utf-8" Add handling of clock related to secondary MI2S_RX in sm8250_snd_startup(). Cc: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Signed-off-by: Alexey Klimov --- sound/soc/qcom/sm8250.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/soc/qcom/sm8250.c b/sound/soc/qcom/sm8250.c index 91e9bba192c0..45e0c33fc3f3 100644 --- a/sound/soc/qcom/sm8250.c +++ b/sound/soc/qcom/sm8250.c @@ -63,6 +63,14 @@ static int sm8250_snd_startup(struct snd_pcm_substream *= substream) snd_soc_dai_set_fmt(cpu_dai, fmt); snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt); break; + case SECONDARY_MI2S_RX: + codec_dai_fmt |=3D SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S; + snd_soc_dai_set_sysclk(cpu_dai, + Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, + MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK); + snd_soc_dai_set_fmt(cpu_dai, fmt); + snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt); + break; case TERTIARY_MI2S_RX: codec_dai_fmt |=3D SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S; snd_soc_dai_set_sysclk(cpu_dai, --=20 2.45.2 From nobody Tue Nov 26 12:39:00 2024 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2F5513AA3F for ; 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Thu, 17 Oct 2024 19:54:58 -0700 (PDT) Received: from localhost.localdomain ([2.125.184.148]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0ed599sm596135f8f.69.2024.10.17.19.54.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 19:54:57 -0700 (PDT) From: Alexey Klimov To: linux-sound@vger.kernel.org, srinivas.kandagatla@linaro.org, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, perex@perex.cz, tiwai@suse.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, krzysztof.kozlowski@linaro.org, caleb.connolly@linaro.org, linux-kernel@vger.kernel.org, a39.skl@gmail.com Subject: [PATCH v3 2/5] arm64: dts: qcom: sm6115: add apr and its services Date: Fri, 18 Oct 2024 03:54:48 +0100 Message-ID: <20241018025452.1362293-3-alexey.klimov@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241018025452.1362293-1-alexey.klimov@linaro.org> References: <20241018025452.1362293-1-alexey.klimov@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add apr (asynchronous packet router) node and its associated services required to enable audio on QRB4210 RB2 platform. Cc: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexey Klimov --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 72 ++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index 41216cc319d6..b211a49982d6 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include =20 / { @@ -2701,6 +2703,76 @@ glink-edge { qcom,remote-pid =3D <2>; mboxes =3D <&apcs_glb 8>; =20 + apr { + compatible =3D "qcom,apr-v2"; + qcom,glink-channels =3D "apr_audio_svc"; + qcom,domain =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + + service@3 { + reg =3D ; + compatible =3D "qcom,q6core"; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible =3D "qcom,q6afe"; + reg =3D ; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + q6afedai: dais { + compatible =3D "qcom,q6afe-dais"; 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charset="utf-8" Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. Cc: Srinivas Kandagatla Signed-off-by: Alexey Klimov --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index b211a49982d6..4fc6978d105b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include =20 / { @@ -810,6 +811,20 @@ data-pins { }; }; =20 + lpass_tlmm: pinctrl@a7c0000 { + compatible =3D "qcom,sm6115-lpass-lpi-pinctrl"; + reg =3D <0x0 0x0a7c0000 0x0 0x20000>, + <0x0 0x0a950000 0x0 0x10000>; + + clocks =3D <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO= >; + clock-names =3D "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 19>; + + }; + gcc: clock-controller@1400000 { compatible =3D "qcom,gcc-sm6115"; reg =3D <0x0 0x01400000 0x0 0x1f0000>; --=20 2.45.2 From nobody Tue Nov 26 12:39:00 2024 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6633F1714A5 for ; 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charset="utf-8" Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. QRB4210 is based on sm4250 which has a slightly different lpass pin controller comparing to sm6115. While at this, also add description of lpi_i2s2 pins (active state) required for audio playback via HDMI. Cc: Srinivas Kandagatla Signed-off-by: Alexey Klimov Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 39 ++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qco= m/sm4250.dtsi index c5add8f44fc0..ed5eb5818d5f 100644 --- a/arch/arm64/boot/dts/qcom/sm4250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -36,3 +36,42 @@ &CPU6 { &CPU7 { compatible =3D "qcom,kryo240"; }; + +&lpass_tlmm { + compatible =3D "qcom,sm4250-lpass-lpi-pinctrl"; + gpio-ranges =3D <&lpass_tlmm 0 0 26>; + + lpi_i2s2_active: lpi-i2s2-active-state { + sck-pins { + pins =3D "gpio10"; + function =3D "i2s2_clk"; + bias-disable; + drive-strength =3D <8>; + output-high; + }; + + ws-pins { + pins =3D "gpio11"; + function =3D "i2s2_ws"; + bias-disable; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio12"; + function =3D "i2s2_data"; + bias-disable; + drive-strength =3D <8>; + output-high; + }; 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charset="utf-8" Add sound node and dsp-related piece to enable HDMI audio playback support on Qualcomm QRB4210 RB2 board. That is the only sound output supported for now. The audio playback is verified using the following commands: amixer -c0 cset iface=3DMIXER,name=3D'SEC_MI2S_RX Audio Mixer MultiMedia1' 1 aplay -D hw:0,0 /usr/share/sounds/alsa/Front_Center.wav Cc: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Signed-off-by: Alexey Klimov --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 55 ++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts= /qcom/qrb4210-rb2.dts index 1888d99d398b..5f671b9c8fb9 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -6,6 +6,8 @@ /dts-v1/; =20 #include +#include +#include #include #include "sm4250.dtsi" #include "pm6125.dtsi" @@ -103,6 +105,51 @@ led-wlan { }; }; =20 + sound { + compatible =3D "qcom,qrb4210-rb2-sndcard"; + pinctrl-0 =3D <&lpi_i2s2_active>; + pinctrl-names =3D "default"; + model =3D "Qualcomm-RB2-WSA8815-Speakers-DMIC0"; + audio-routing =3D "MM_DL1", "MultiMedia1 Playback", + "MM_DL2", "MultiMedia2 Playback"; + + mm1-dai-link { + link-name =3D "MultiMedia1"; + cpu { + sound-dai =3D <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name =3D "MultiMedia2"; + cpu { + sound-dai =3D <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name =3D "MultiMedia3"; + cpu { + sound-dai =3D <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + hdmi-dai-link { + link-name =3D "HDMI Playback"; + cpu { + sound-dai =3D <&q6afedai SECONDARY_MI2S_RX>; + }; + + platform { + sound-dai =3D <&q6routing>; + }; + + codec { + sound-dai =3D <<9611_codec 0>; + }; + }; + }; + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { compatible =3D "regulator-fixed"; regulator-name =3D "VREG_HDMI_OUT_1P2"; @@ -318,6 +365,14 @@ &pon_resin { status =3D "okay"; }; =20 +/* SECONDARY I2S uses 1 I2S SD Line for audio on LT9611UXC HDMI Bridge */ +&q6afedai { + dai@20 { + reg =3D ; + qcom,sd-lines =3D <0>; + }; +}; + &qupv3_id_0 { status =3D "okay"; }; --=20 2.45.2