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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Document two supplies that are used by this model and the optional xo-clk signal. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/regulator/qcom,qca6390-pmu.yaml | 12 ++++++++= ++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.y= aml b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml index 11ed04c95542..ca401a209cca 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml @@ -33,6 +33,12 @@ properties: vddpmu-supply: description: VDD_PMU supply regulator handle =20 + vddpmumx-supply: + description: VDD_PMU_MX supply regulator handle + + vddpmucx-supply: + description: VDD_PMU_CX supply regulator handle + vddio1p2-supply: description: VDD_IO_1P2 supply regulator handle =20 @@ -72,6 +78,10 @@ properties: maxItems: 1 description: GPIO line indicating the state of the clock supply to the= BT module =20 + xo-clk-gpios: + maxItems: 1 + description: GPIO line allowing to select the XO clock configuration f= or the module + clocks: maxItems: 1 description: Reference clock handle @@ -119,6 +129,8 @@ allOf: - vddio-supply - vddaon-supply - vddpmu-supply + - vddpmumx-supply + - vddpmucx-supply - vddrfa0p95-supply - vddrfa1p3-supply - vddrfa1p9-supply --=20 2.43.0 From nobody Tue Nov 26 11:57:17 2024 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D3E918CBF1 for ; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski WCN6855 (also known as QCA6490) is similar to the already supported QCA6390 but takes in two more supplies so add a new vregs list for it. On sm8450-hdk it also requires a short assert of the xo-clk pin so add handling for it in a dedicated unit. As we now have a separate set of targets for this variant, store the pointer to the targets struct associated with a model in the device match data. Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov --- drivers/power/sequencing/pwrseq-qcom-wcn.c | 101 +++++++++++++++++++++++++= +++- 1 file changed, 98 insertions(+), 3 deletions(-) diff --git a/drivers/power/sequencing/pwrseq-qcom-wcn.c b/drivers/power/seq= uencing/pwrseq-qcom-wcn.c index 4fa129877d7e..682a9beac69e 100644 --- a/drivers/power/sequencing/pwrseq-qcom-wcn.c +++ b/drivers/power/sequencing/pwrseq-qcom-wcn.c @@ -22,6 +22,7 @@ struct pwrseq_qcom_wcn_pdata { size_t num_vregs; unsigned int pwup_delay_ms; unsigned int gpio_enable_delay_ms; + const struct pwrseq_target_data **targets; }; =20 struct pwrseq_qcom_wcn_ctx { @@ -31,6 +32,7 @@ struct pwrseq_qcom_wcn_ctx { struct regulator_bulk_data *regs; struct gpio_desc *bt_gpio; struct gpio_desc *wlan_gpio; + struct gpio_desc *xo_clk_gpio; struct clk *clk; unsigned long last_gpio_enable_jf; }; @@ -98,6 +100,33 @@ static const struct pwrseq_unit_data *pwrseq_qcom_wcn_u= nit_deps[] =3D { NULL }; =20 +static int pwrseq_qcom_wcn6855_clk_assert(struct pwrseq_device *pwrseq) +{ + struct pwrseq_qcom_wcn_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + if (!ctx->xo_clk_gpio) + return 0; + + msleep(1); + + gpiod_set_value_cansleep(ctx->xo_clk_gpio, 1); + usleep_range(100, 200); + + return 0; +} + +static const struct pwrseq_unit_data pwrseq_qcom_wcn6855_xo_clk_assert =3D= { + .name =3D "xo-clk-assert", + .enable =3D pwrseq_qcom_wcn6855_clk_assert, +}; + +static const struct pwrseq_unit_data *pwrseq_qcom_wcn6855_unit_deps[] =3D { + &pwrseq_qcom_wcn_vregs_unit_data, + &pwrseq_qcom_wcn_clk_unit_data, + &pwrseq_qcom_wcn6855_xo_clk_assert, + NULL +}; + static int pwrseq_qcom_wcn_bt_enable(struct pwrseq_device *pwrseq) { struct pwrseq_qcom_wcn_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); @@ -125,6 +154,13 @@ static const struct pwrseq_unit_data pwrseq_qcom_wcn_b= t_unit_data =3D { .disable =3D pwrseq_qcom_wcn_bt_disable, }; =20 +static const struct pwrseq_unit_data pwrseq_qcom_wcn6855_bt_unit_data =3D { + .name =3D "wlan-enable", + .deps =3D pwrseq_qcom_wcn6855_unit_deps, + .enable =3D pwrseq_qcom_wcn_bt_enable, + .disable =3D pwrseq_qcom_wcn_bt_disable, +}; + static int pwrseq_qcom_wcn_wlan_enable(struct pwrseq_device *pwrseq) { struct pwrseq_qcom_wcn_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); @@ -152,6 +188,13 @@ static const struct pwrseq_unit_data pwrseq_qcom_wcn_w= lan_unit_data =3D { .disable =3D pwrseq_qcom_wcn_wlan_disable, }; =20 +static const struct pwrseq_unit_data pwrseq_qcom_wcn6855_wlan_unit_data = =3D { + .name =3D "wlan-enable", + .deps =3D pwrseq_qcom_wcn6855_unit_deps, + .enable =3D pwrseq_qcom_wcn_wlan_enable, + .disable =3D pwrseq_qcom_wcn_wlan_disable, +}; + static int pwrseq_qcom_wcn_pwup_delay(struct pwrseq_device *pwrseq) { struct pwrseq_qcom_wcn_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); @@ -162,6 +205,18 @@ static int pwrseq_qcom_wcn_pwup_delay(struct pwrseq_de= vice *pwrseq) return 0; } =20 +static int pwrseq_qcom_wcn6855_xo_clk_deassert(struct pwrseq_device *pwrse= q) +{ + struct pwrseq_qcom_wcn_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + if (ctx->xo_clk_gpio) { + usleep_range(2000, 5000); + gpiod_set_value_cansleep(ctx->xo_clk_gpio, 0); + } + + return pwrseq_qcom_wcn_pwup_delay(pwrseq); +} + static const struct pwrseq_target_data pwrseq_qcom_wcn_bt_target_data =3D { .name =3D "bluetooth", .unit =3D &pwrseq_qcom_wcn_bt_unit_data, @@ -174,12 +229,30 @@ static const struct pwrseq_target_data pwrseq_qcom_wc= n_wlan_target_data =3D { .post_enable =3D pwrseq_qcom_wcn_pwup_delay, }; =20 +static const struct pwrseq_target_data pwrseq_qcom_wcn6855_bt_target_data = =3D { + .name =3D "bluetooth", + .unit =3D &pwrseq_qcom_wcn6855_bt_unit_data, + .post_enable =3D pwrseq_qcom_wcn6855_xo_clk_deassert, +}; + +static const struct pwrseq_target_data pwrseq_qcom_wcn6855_wlan_target_dat= a =3D { + .name =3D "wlan", + .unit =3D &pwrseq_qcom_wcn6855_wlan_unit_data, + .post_enable =3D pwrseq_qcom_wcn6855_xo_clk_deassert, +}; + static const struct pwrseq_target_data *pwrseq_qcom_wcn_targets[] =3D { &pwrseq_qcom_wcn_bt_target_data, &pwrseq_qcom_wcn_wlan_target_data, NULL }; =20 +static const struct pwrseq_target_data *pwrseq_qcom_wcn6855_targets[] =3D { + &pwrseq_qcom_wcn6855_bt_target_data, + &pwrseq_qcom_wcn6855_wlan_target_data, + NULL +}; + static const char *const pwrseq_qca6390_vregs[] =3D { "vddio", "vddaon", @@ -196,13 +269,28 @@ static const struct pwrseq_qcom_wcn_pdata pwrseq_qca6= 390_of_data =3D { .num_vregs =3D ARRAY_SIZE(pwrseq_qca6390_vregs), .pwup_delay_ms =3D 60, .gpio_enable_delay_ms =3D 100, + .targets =3D pwrseq_qcom_wcn_targets, +}; + +static const char *const pwrseq_wcn6855_vregs[] =3D { + "vddio", + "vddaon", + "vddpmu", + "vddpmumx", + "vddpmucx", + "vddrfa0p95", + "vddrfa1p3", + "vddrfa1p9", + "vddpcie1p3", + "vddpcie1p9", }; =20 static const struct pwrseq_qcom_wcn_pdata pwrseq_wcn6855_of_data =3D { - .vregs =3D pwrseq_qca6390_vregs, - .num_vregs =3D ARRAY_SIZE(pwrseq_qca6390_vregs), + .vregs =3D pwrseq_wcn6855_vregs, + .num_vregs =3D ARRAY_SIZE(pwrseq_wcn6855_vregs), .pwup_delay_ms =3D 50, .gpio_enable_delay_ms =3D 5, + .targets =3D pwrseq_qcom_wcn6855_targets, }; =20 static const char *const pwrseq_wcn7850_vregs[] =3D { @@ -219,6 +307,7 @@ static const struct pwrseq_qcom_wcn_pdata pwrseq_wcn785= 0_of_data =3D { .vregs =3D pwrseq_wcn7850_vregs, .num_vregs =3D ARRAY_SIZE(pwrseq_wcn7850_vregs), .pwup_delay_ms =3D 50, + .targets =3D pwrseq_qcom_wcn_targets, }; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Add nodes for the WCN6855 PMU, the WLAN module and relevant regulators and pin functions to fully describe how the wifi is actually wired on this platform. Reviewed-by: Dmitry Baryshkov Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 112 ++++++++++++++++++++++++++= ++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index 6020582b0a59..a02d8029ac2d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -260,6 +260,69 @@ usb1_sbu_mux: endpoint { }; }; }; + + wcn6855-pmu { + compatible =3D "qcom,wcn6855-pmu"; + + pinctrl-0 =3D <&wlan_en>; + pinctrl-names =3D "default"; + + wlan-enable-gpios =3D <&tlmm 134 GPIO_ACTIVE_HIGH>; + swctrl-gpios =3D <&tlmm 132 GPIO_ACTIVE_HIGH>; + + vddio-supply =3D <&vreg_s10b>; + vddaon-supply =3D <&vreg_s12b>; + vddpmu-supply =3D <&vreg_s12b>; + vddpmumx-supply =3D <&vreg_s12b>; + vddpmucx-supply =3D <&vreg_s12b>; + vddrfa0p95-supply =3D <&vreg_s12b>; + vddrfa1p3-supply =3D <&vreg_s11b>; + vddrfa1p9-supply =3D <&vreg_s1c>; + vddpcie1p3-supply =3D <&vreg_s11b>; + vddpcie1p9-supply =3D <&vreg_s1c>; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name =3D "vreg_pmu_rfa_1p7"; + }; + }; + }; }; =20 &apps_rsc { @@ -269,6 +332,15 @@ regulators-0 { =20 vdd-l3-l5-supply =3D <&vreg_s11b>; =20 + vreg_s10b: smps10 { + regulator-name =3D "vreg_s10b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + regulator-boot-on; + }; + vreg_s11b: smps11 { regulator-name =3D "vreg_s11b"; regulator-min-microvolt =3D <1272000>; @@ -276,6 +348,13 @@ vreg_s11b: smps11 { regulator-initial-mode =3D ; }; =20 + vreg_s12b: smps12 { + regulator-name =3D "vreg_s12b"; + regulator-min-microvolt =3D <984000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + vreg_l3b: ldo3 { regulator-name =3D "vreg_l3b"; regulator-min-microvolt =3D <1200000>; @@ -304,6 +383,13 @@ regulators-1 { compatible =3D "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id =3D "c"; =20 + vreg_s1c: smps1 { + regulator-name =3D "vreg_s1c"; + regulator-min-microvolt =3D <1888000>; + regulator-max-microvolt =3D <1888000>; + regulator-initial-mode =3D ; + }; + vreg_l1c: ldo1 { regulator-name =3D "vreg_l1c"; regulator-min-microvolt =3D <1800000>; @@ -583,6 +669,25 @@ &pcie4_phy { status =3D "okay"; }; =20 +&pcie4_port0 { + wifi@0 { + compatible =3D "pci17cb,1103"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply =3D <&vreg_pmu_aon_0p8>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p8>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; + + qcom,ath11k-calibration-variant =3D "QC_8280XP_CRD"; + }; +}; + &pmc8280c_lpg { status =3D "okay"; }; @@ -1030,4 +1135,11 @@ mode-pins { output-high; }; }; + + wlan_en: wlan-en-state { + pins =3D "gpio134"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; }; --=20 2.43.0 From nobody Tue Nov 26 11:57:17 2024 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4BD418E37A for ; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Add the bluetooth node for sc8280xp-crd and make it consume the outputs from the PMU as per the new DT bindings contract. Reviewed-by: Dmitry Baryshkov Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 59 +++++++++++++++++++++++++++= +++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index a02d8029ac2d..75adaa19d1c3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -20,6 +20,7 @@ aliases { i2c4 =3D &i2c4; i2c21 =3D &i2c21; serial0 =3D &uart17; + serial1 =3D &uart2; }; =20 backlight: backlight { @@ -264,10 +265,11 @@ usb1_sbu_mux: endpoint { wcn6855-pmu { compatible =3D "qcom,wcn6855-pmu"; =20 - pinctrl-0 =3D <&wlan_en>; + pinctrl-0 =3D <&bt_en>, <&wlan_en>; pinctrl-names =3D "default"; =20 wlan-enable-gpios =3D <&tlmm 134 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 133 GPIO_ACTIVE_HIGH>; swctrl-gpios =3D <&tlmm 132 GPIO_ACTIVE_HIGH>; =20 vddio-supply =3D <&vreg_s10b>; @@ -748,6 +750,26 @@ &sdc2 { status =3D "okay"; }; =20 +&uart2 { + pinctrl-0 =3D <&uart2_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn6855-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply =3D <&vreg_pmu_aon_0p8>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p8>; + vddbtcmx-supply =3D <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; + }; +}; + &uart17 { compatible =3D "qcom,geni-debug-uart"; =20 @@ -893,6 +915,13 @@ hastings_reg_en: hastings-reg-en-state { &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 + bt_en: bt-en-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins =3D "gpio25"; function =3D "gpio"; @@ -1086,6 +1115,34 @@ reset-n-pins { }; }; =20 + uart2_default: uart2-default-state { + cts-pins { + pins =3D "gpio121"; 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Fri, 18 Oct 2024 05:49:43 -0700 (PDT) From: Bartosz Golaszewski Date: Fri, 18 Oct 2024 14:49:15 +0200 Subject: [PATCH v6 5/6] arm64: dts: qcom: sc8280xp-x13s: model the PMU of the on-board wcn6855 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241018-sc8280xp-pwrseq-v6-5-8da8310d9564@linaro.org> References: <20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org> In-Reply-To: <20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Bjorn Andersson , Konrad Dybcio , Johan Hovold , Kalle Valo , Dmitry Baryshkov , Abel Vesa , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Bartosz Golaszewski , Steev Klimaszewski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Add a node for the PMU of the WCN6855 and rework the inputs of the wifi and bluetooth nodes to consume the PMU's outputs. With this we can drop the regulator-always-on properties from vreg_s11b and vreg_s12b as they will now be enabled by the power sequencing driver. Tested-by: Steev Klimaszewski # Thinkpad X13s Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 103 +++++++++++++++++= +--- 1 file changed, 89 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 6a28cab97189..ce1898c085de 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -400,6 +400,70 @@ usb1_sbu_mux: endpoint { }; }; }; + + wcn6855-pmu { + compatible =3D "qcom,wcn6855-pmu"; + + pinctrl-0 =3D <&bt_default>, <&wlan_en>; + pinctrl-names =3D "default"; + + wlan-enable-gpios =3D <&tlmm 134 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 133 GPIO_ACTIVE_HIGH>; + swctrl-gpios =3D <&tlmm 132 GPIO_ACTIVE_HIGH>; + + vddio-supply =3D <&vreg_s10b>; + vddaon-supply =3D <&vreg_s12b>; + vddpmu-supply =3D <&vreg_s12b>; + vddpmumx-supply =3D <&vreg_s12b>; + vddpmucx-supply =3D <&vreg_s12b>; + vddrfa0p95-supply =3D <&vreg_s12b>; + vddrfa1p3-supply =3D <&vreg_s11b>; + vddrfa1p9-supply =3D <&vreg_s1c>; + vddpcie1p3-supply =3D <&vreg_s11b>; + vddpcie1p9-supply =3D <&vreg_s1c>; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name =3D "vreg_pmu_rfa_1p7"; + }; + }; + }; }; =20 &apps_rsc { @@ -426,7 +490,6 @@ vreg_s11b: smps11 { regulator-min-microvolt =3D <1272000>; regulator-max-microvolt =3D <1272000>; regulator-initial-mode =3D ; - regulator-always-on; }; =20 vreg_s12b: smps12 { @@ -434,7 +497,6 @@ vreg_s12b: smps12 { regulator-min-microvolt =3D <984000>; regulator-max-microvolt =3D <984000>; regulator-initial-mode =3D ; - regulator-always-on; }; =20 vreg_l1b: ldo1 { @@ -927,6 +989,16 @@ wifi@0 { compatible =3D "pci17cb,1103"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; =20 + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply =3D <&vreg_pmu_aon_0p8>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p8>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; + qcom,ath11k-calibration-variant =3D "LE_X13S"; }; }; @@ -1258,20 +1330,16 @@ &uart2 { bluetooth { compatible =3D "qcom,wcn6855-bt"; =20 - vddio-supply =3D <&vreg_s10b>; - vddbtcxmx-supply =3D <&vreg_s12b>; - vddrfacmn-supply =3D <&vreg_s12b>; - vddrfa0p8-supply =3D <&vreg_s12b>; - vddrfa1p2-supply =3D <&vreg_s11b>; - vddrfa1p7-supply =3D <&vreg_s1c>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply =3D <&vreg_pmu_aon_0p8>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p8>; + vddbtcmx-supply =3D <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; =20 max-speed =3D <3200000>; - - enable-gpios =3D <&tlmm 133 GPIO_ACTIVE_HIGH>; - swctrl-gpios =3D <&tlmm 132 GPIO_ACTIVE_HIGH>; - - pinctrl-0 =3D <&bt_default>; - pinctrl-names =3D "default"; }; }; =20 @@ -1761,4 +1829,11 @@ reset-pins { bias-disable; }; }; + + wlan_en: wlan-en-state { + pins =3D "gpio134"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; }; --=20 2.43.0 From nobody Tue Nov 26 11:57:17 2024 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8DD71EE007 for ; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Add nodes for the WCN6855 PMU, the WLAN and BT modules and relevant regulators and pin functions to fully describe how the wifi is actually wired on this platform. Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 157 ++++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 2 files changed, 158 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8450-hdk.dts index 67443822653d..2ff40a120aad 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -26,6 +26,7 @@ / { =20 aliases { serial0 =3D &uart7; + serial1 =3D &uart20; }; =20 wcd938x: audio-codec { @@ -247,6 +248,71 @@ active-config0 { }; }; =20 + wcn6855-pmu { + compatible =3D "qcom,wcn6855-pmu"; + + pinctrl-0 =3D <&bt_en>, <&wlan_en>, <&xo_clk_default>; + pinctrl-names =3D "default"; + + wlan-enable-gpios =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; + swctrl-gpios =3D <&tlmm 82 GPIO_ACTIVE_HIGH>; + xo-clk-gpios =3D <&tlmm 204 GPIO_ACTIVE_HIGH>; + + vddio-supply =3D <&vreg_s10b_1p8>; + vddaon-supply =3D <&vreg_s11b_0p95>; + vddpmu-supply =3D <&vreg_s12b_1p25>; + vddpmumx-supply =3D <&vreg_s2e_0p85>; + vddpmucx-supply =3D <&vreg_s11b_0p95>; + vddrfa0p95-supply =3D <&vreg_s11b_0p95>; + vddrfa1p3-supply =3D <&vreg_s12b_1p25>; + vddrfa1p9-supply =3D <&vreg_s1c_1p86>; + vddpcie1p3-supply =3D <&vreg_s12b_1p25>; + vddpcie1p9-supply =3D <&vreg_s1c_1p86>; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name =3D "vreg_pmu_rfa_1p7"; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vph_pwr"; @@ -685,6 +751,23 @@ &pcie0_phy { vdda-pll-supply =3D <&vreg_l6b_1p2>; }; =20 +&pcieport0 { + wifi@0 { + compatible =3D "pci17cb,1103"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply =3D <&vreg_pmu_aon_0p8>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p8>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; + }; +}; + &pcie1 { status =3D "okay"; }; @@ -892,6 +975,10 @@ &qupv3_id_1 { status =3D "okay"; }; =20 +&qupv3_id_2 { + status =3D "okay"; +}; + &sdhc_2 { cd-gpios =3D <&tlmm 92 GPIO_ACTIVE_HIGH>; pinctrl-names =3D "default", "sleep"; @@ -1069,6 +1156,26 @@ &uart7 { status =3D "okay"; }; =20 +&uart20 { + pinctrl-0 =3D <&uart20_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn6855-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply =3D <&vreg_pmu_aon_0p8>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p8>; + vddbtcmx-supply =3D <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; + }; +}; + &ufs_mem_hc { status =3D "okay"; =20 @@ -1130,6 +1237,14 @@ &vamacro { }; =20 &tlmm { + bt_en: bt-en-state { + pins =3D "gpio81"; + function =3D "gpio"; + drive-strength =3D <16>; + output-low; + bias-pull-down; + }; + spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins =3D "gpio1"; function =3D "gpio"; @@ -1153,4 +1268,46 @@ wcd_default: wcd-reset-n-active-state { bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <16>; + output-low; + bias-pull-down; + }; + + uart20_default: uart20-default-state { + cts-pins { + pins =3D "gpio76"; + function =3D "qup20"; + bias-disable; + }; + + rts-pins { + pins =3D "gpio77"; + function =3D "qup20"; + bias-disable; + }; + + rx-pins { + pins =3D "gpio78"; + function =3D "qup20"; + bias-disable; + }; + + tx-pins { + pins =3D "gpio79"; + function =3D "qup20"; + bias-disable; + }; + }; + + xo_clk_default: xo-clk-state { + pins =3D "gpio204"; + function =3D "gpio"; + drive-strength =3D <16>; + output-low; + bias-pull-down; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 1b5dc5b8cecb..be876a919455 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1880,7 +1880,7 @@ opp-8000000 { }; }; =20 - pcie@0 { + pcieport0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; --=20 2.43.0