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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a151b0098sm160702e87.22.2024.10.18.01.42.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 01:42:42 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 18 Oct 2024 11:42:39 +0300 Subject: [PATCH v2 1/2] dt-bindings: pinctrl : qcom: document SAR2130P TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241018-sar2130p-tlmm-v2-1-11a1d09a6e5f@linaro.org> References: <20241018-sar2130p-tlmm-v2-0-11a1d09a6e5f@linaro.org> In-Reply-To: <20241018-sar2130p-tlmm-v2-0-11a1d09a6e5f@linaro.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5501; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=jlAblsvCAzmnPMfPaWDHZ1zD+dL0UCw2w1NNWlWDCHE=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnEh+A4s/ZJsjEmaEAiMaj2vHXZ5zW4SHla/y/T 25X8wRZcdCJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxIfgAAKCRAU23LtvoBl uPDPD/9VxrKg/rkUeAsZ0OjOobv5eXI/rb0vh1YXHOqrQ1Q9zyOeMJmyDXf/Gy6vI92xwJ3zGuN wIHKKaKulkpNX/a55U2E/lCD2PjHqP8jbT/LmEmsjYppzNzjEKKfI0Cup2D/EBXDLYgkXV4jxKH 0N3VGuU4kaRmfGclD4HqURYJyz4oMgkvvUy7lEHCgujb2TCNaRE2wEcakEVLsCcReO4jkbt6e7U 3qUp6nwJFb/gr3yS/8Wjy0bBV21nr474DEeU0TMNd0cemdoM8KIpENw3MTzB+ARFu3j0Zktsg2D jU3+b050/ueXU/CZHdaYhxQ3ADbD4oNIPrq+yRWhonl/55Basge+d+/AAz5lfa1cxu3YpFHci11 s0xwtXEltqT/tj+EdC87bMbr+8pUPZiHNk4as1G2gnG+BT10c0ydDb754d4pXszhJvbj/AAGqkJ Vj8Oq3dj9BW4oyIpQdfwATcJqecqtvUttnD6VahTE5gLiETkuC3VGjkpK/CzJui80d2zY+cjTZx qFKMtJpJMJcLnR5gymE1kYTgEqm587oMaQDI55/WKllrUq+oofAqpcVv2KhtYAB+8JWvpzo4ht+ 1Bt3MkxLb0V2QJDGnb1OV86BfTA0GMGOSC200UEblduQguDznfOsJPhENEhgrS+MvnmNPn8CeC5 iYQRd9vFTRa8Efg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add bindings for the pin controller (TLMM) present on the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sar2130p-tlmm.yaml | 138 +++++++++++++++++= ++++ 1 file changed, 138 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.y= aml b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b388380b1ce02e21283e2200bce= 241bba6100024 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SAR2130P TLMM block + +maintainers: + - Dmitry Baryshkov + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sar2130p-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 78 + + gpio-line-names: + maxItems: 156 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sar2130p-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sar2130p-tlmm-state" + additionalProperties: false + +$defs: + qcom-sar2130p-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ aoss_cti, atest_char, atest_char0, atest_char1, atest_char= 2, + atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_u= sb02, + atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi= 0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp0_hot, ext_mclk0, ext_mclk= 1, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, host2wlan_sol, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_v= sync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, pcie0_clkr= eqn, + pcie1_clkreqn, phase_flag0, phase_flag1, phase_flag10, + phase_flag11, phase_flag12, phase_flag13, phase_flag14, + phase_flag15, phase_flag16, phase_flag17, phase_flag18, + phase_flag19, phase_flag2, phase_flag20, phase_flag21, + phase_flag22, phase_flag23, phase_flag24, phase_flag25, + phase_flag26, phase_flag27, phase_flag28, phase_flag29, + phase_flag3, phase_flag30, phase_flag31, phase_flag4, + phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gp= io13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpi= o4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs0, qspi_cs1, = qup0, + qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup1= 0, + qup11, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, usb0_phy, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible =3D "qcom,sar2130p-tlmm"; + reg =3D <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 156>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + gpio-wo-state { + pins =3D "gpio1"; + function =3D "gpio"; + }; + + uart-w-state { + rx-pins { + pins =3D "gpio26"; + function =3D "qup7"; + bias-pull-up; + }; + + tx-pins { + pins =3D "gpio27"; + function =3D "qup7"; + bias-disable; + }; + }; + }; +... --=20 2.39.5