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Fri, 18 Oct 2024 11:13:18 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49IBDHom014060 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Oct 2024 11:13:17 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 18 Oct 2024 04:13:13 -0700 From: Imran Shaik Date: Fri, 18 Oct 2024 16:42:34 +0530 Subject: [PATCH 6/6] clk: qcom: Add support for Video Clock Controller on QCS8300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241018-qcs8300-mm-patches-v1-6-859095e0776c@quicinc.com> References: <20241018-qcs8300-mm-patches-v1-0-859095e0776c@quicinc.com> In-Reply-To: <20241018-qcs8300-mm-patches-v1-0-859095e0776c@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7Y7TQFIXw3gcoQqYhrAgM78wKi3vHRGY X-Proofpoint-ORIG-GUID: 7Y7TQFIXw3gcoQqYhrAgM78wKi3vHRGY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 clxscore=1015 phishscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410180071 Add support to the QCS8300 Video clock controller by extending the SA8775P Video clock controller, which is mostly identical but QCS8300 has minor difference. Signed-off-by: Imran Shaik --- drivers/clk/qcom/videocc-sa8775p.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/videocc-sa8775p.c b/drivers/clk/qcom/videocc-= sa8775p.c index bf5de411fd5d..d0494ba81f5f 100644 --- a/drivers/clk/qcom/videocc-sa8775p.c +++ b/drivers/clk/qcom/videocc-sa8775p.c @@ -524,6 +524,7 @@ static struct qcom_cc_desc video_cc_sa8775p_desc =3D { =20 static const struct of_device_id video_cc_sa8775p_match_table[] =3D { { .compatible =3D "qcom,sa8775p-videocc" }, + { .compatible =3D "qcom,qcs8300-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sa8775p_match_table); @@ -550,6 +551,9 @@ static int video_cc_sa8775p_probe(struct platform_devic= e *pdev) clk_lucid_evo_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_evo_pll_configure(&video_pll1, regmap, &video_pll1_config); =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-videocc")) + regmap_write(regmap, video_cc_mvs0c_div2_div_clk_src.reg, 2); + /* Keep some clocks always enabled */ qcom_branch_set_clk_en(regmap, 0x80ec); /* VIDEO_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x8144); /* VIDEO_CC_SLEEP_CLK */ --=20 2.25.1