From nobody Tue Nov 26 13:46:30 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8EBA202F73; Fri, 18 Oct 2024 11:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729249986; cv=none; b=okPN0hPRgsqYQ0Te9LNYKLnG+k3iwIeu/qRNzH9P5Me59/F7ez+tgPuaBOraOWVzg0rs/UTMnDgdg6kKJbngJueuIohYuozA7rlDAf/UgNCkhkh73xqecQ+OoabTQ6u0Qa0UpYF6weSf7oq/rpM2cM1NEJXr4rVPGRT6VYrFLUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729249986; c=relaxed/simple; bh=IosuIZXt5E73iLLBmLOT0LsthT4MlzdaSSqDMzkoFNk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qWG1M7vX01q/md7b7eyGEgRqXJDTMiQMB2zAFctHf7E6tbrhdqWrq0QTw68JaD7HngjH5uT1x/n74fzI89Ub/I5OQnrVCivIAHvDcZ3CBG3X5JR38VQdngYF4y75nRczZ7IAVbK2Fy2XGrGT/b+9KG3Fh3IO9HSQ2XGGKzwLksc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aPEaTs/6; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aPEaTs/6" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49IAdo95018281; Fri, 18 Oct 2024 11:13:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= FdKFBX0R5eTySPm5TvF6eehMwprJfxVydU2rOisit6o=; b=aPEaTs/6Pgvy0slN SgZh4AYFYYxgShTbBl543cCRK7i1xgC4QDSTfll0pz388L32A2zYvDA2Cm1K0pIY D0kVo1czfFICiQHkBu5Xgfe27KgV18n1nzw2J9zmisbnZ8c2YBd+THOfuNbwxYfg Sh8jGWhTGZN9HIoLWwXxinTQ29xCi8ocU4JXbOuhZ3ZVcaaGweXMbhjM4q3yPywl nHEFffGM4fwsN6JSbILxFHLRGS2cCacf+Eu0KC5tOSnWNyLKlxYzSp/4zbR+63Dv Yg+6d9T0dgXRD4Q3GTlatTRzVK82zpG3Q/NABLR+FlsJ9O8H4yCGdm2YxfY5XFHZ Da7sZQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42b0rx3tmp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Oct 2024 11:13:01 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49IBD0xS011201 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Oct 2024 11:13:00 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 18 Oct 2024 04:12:56 -0700 From: Imran Shaik Date: Fri, 18 Oct 2024 16:42:30 +0530 Subject: [PATCH 2/6] clk: qcom: Add support for GPU Clock Controller on QCS8300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241018-qcs8300-mm-patches-v1-2-859095e0776c@quicinc.com> References: <20241018-qcs8300-mm-patches-v1-0-859095e0776c@quicinc.com> In-Reply-To: <20241018-qcs8300-mm-patches-v1-0-859095e0776c@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hfdbJ1nqFc1g5qPUE8IOhYiGxw8NJgVI X-Proofpoint-ORIG-GUID: hfdbJ1nqFc1g5qPUE8IOhYiGxw8NJgVI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=895 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410180071 Add support to the QCS8300 GPU clock controller by extending the SA8775P GPU clock controller, which is mostly identical but QCS8300 has few additional clocks and minor differences. Signed-off-by: Imran Shaik Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/gpucc-sa8775p.c | 47 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 47 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa87= 75p.c index f8a8ac343d70..99a8344b00db 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x95e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_cx_ff_clk =3D { .halt_reg =3D 0x914c, .halt_check =3D BRANCH_HALT, @@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x95e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_gx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { .halt_reg =3D 0x7000, .halt_check =3D BRANCH_HALT_VOTED, @@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, [GPU_CC_CB_CLK] =3D &gpu_cc_cb_clk.clkr, [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, @@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_DEMET_DIV_CLK_SRC] =3D &gpu_cc_demet_div_clk_src.clkr, [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, [GPU_CC_HUB_AHB_DIV_CLK_SRC] =3D &gpu_cc_hub_ahb_div_clk_src.clkr, [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, @@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = =3D { }; =20 static const struct of_device_id gpu_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-gpucc" }, { .compatible =3D "qcom,sa8775p-gpucc" }, { } }; @@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device= *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) { + gpu_cc_pll0_config.l =3D 0x31; + gpu_cc_pll0_config.alpha =3D 0xe555; + + gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shif= t_clk.clkr; + gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shif= t_clk.clkr; + } + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); =20 --=20 2.25.1