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Signed-off-by: Imran Shaik --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 1 + include/dt-bindings/clock/qcom,sa8775p-gpucc.h | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Docu= mentation/devicetree/bindings/clock/qcom,gpucc.yaml index 0858fd635282..b2b8a1e0297f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -27,6 +27,7 @@ description: | properties: compatible: enum: + - qcom,qcs8300-gpucc - qcom,sdm845-gpucc - qcom,sa8775p-gpucc - qcom,sc7180-gpucc diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bi= ndings/clock/qcom,sa8775p-gpucc.h index a5fd784b1ea2..54eaaf1c4e52 100644 --- a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights re= served. * Copyright (c) 2023, Linaro Limited */ =20 @@ -31,6 +31,8 @@ #define GPU_CC_MEMNOC_GFX_CLK 20 #define GPU_CC_SLEEP_CLK 21 #define GPU_CC_XO_CLK_SRC 22 +#define GPU_CC_CX_ACCU_SHIFT_CLK 23 +#define GPU_CC_GX_ACCU_SHIFT_CLK 24 =20 /* GPU_CC resets */ #define GPUCC_GPU_CC_ACD_BCR 0 --=20 2.25.1 From nobody Tue Nov 26 11:48:40 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8EBA202F73; Fri, 18 Oct 2024 11:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729249986; cv=none; b=okPN0hPRgsqYQ0Te9LNYKLnG+k3iwIeu/qRNzH9P5Me59/F7ez+tgPuaBOraOWVzg0rs/UTMnDgdg6kKJbngJueuIohYuozA7rlDAf/UgNCkhkh73xqecQ+OoabTQ6u0Qa0UpYF6weSf7oq/rpM2cM1NEJXr4rVPGRT6VYrFLUE= ARC-Message-Signature: i=1; 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Signed-off-by: Imran Shaik Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/gpucc-sa8775p.c | 47 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 47 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa87= 75p.c index f8a8ac343d70..99a8344b00db 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x95e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_cx_ff_clk =3D { .halt_reg =3D 0x914c, .halt_check =3D BRANCH_HALT, @@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x95e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_gx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { .halt_reg =3D 0x7000, .halt_check =3D BRANCH_HALT_VOTED, @@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, [GPU_CC_CB_CLK] =3D &gpu_cc_cb_clk.clkr, [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, @@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_DEMET_DIV_CLK_SRC] =3D &gpu_cc_demet_div_clk_src.clkr, [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, [GPU_CC_HUB_AHB_DIV_CLK_SRC] =3D &gpu_cc_hub_ahb_div_clk_src.clkr, [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, @@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = =3D { }; =20 static const struct of_device_id gpu_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-gpucc" }, { .compatible =3D "qcom,sa8775p-gpucc" }, { } }; @@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device= *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) { + gpu_cc_pll0_config.l =3D 0x31; + gpu_cc_pll0_config.alpha =3D 0xe555; + + gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shif= t_clk.clkr; + gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shif= t_clk.clkr; + } + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); =20 --=20 2.25.1 From nobody Tue Nov 26 11:48:40 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 542E7202F9F; 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Signed-off-by: Imran Shaik --- Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml | 1 + include/dt-bindings/clock/qcom,sa8775p-camcc.h | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml index 36a60d8f5ae3..18cbc23b9a07 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml @@ -18,6 +18,7 @@ description: | properties: compatible: enum: + - qcom,qcs8300-camcc - qcom,sa8775p-camcc =20 clocks: diff --git a/include/dt-bindings/clock/qcom,sa8775p-camcc.h b/include/dt-bi= ndings/clock/qcom,sa8775p-camcc.h index 38531acd699f..36ac587a981a 100644 --- a/include/dt-bindings/clock/qcom,sa8775p-camcc.h +++ b/include/dt-bindings/clock/qcom,sa8775p-camcc.h @@ -93,6 +93,7 @@ #define CAM_CC_SM_OBS_CLK 83 #define CAM_CC_XO_CLK_SRC 84 #define CAM_CC_QDSS_DEBUG_XO_CLK 85 +#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK 86 =20 /* CAM_CC power domains */ #define CAM_CC_TITAN_TOP_GDSC 0 --=20 2.25.1 From nobody Tue Nov 26 11:48:40 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D32C02038A7; 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Signed-off-by: Imran Shaik Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/camcc-sa8775p.c | 99 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa87= 75p.c index c04801a5af35..0ef3c6015c34 100644 --- a/drivers/clk/qcom/camcc-sa8775p.c +++ b/drivers/clk/qcom/camcc-sa8775p.c @@ -1682,6 +1682,24 @@ static struct clk_branch cam_cc_sm_obs_clk =3D { }, }; =20 +static struct clk_branch cam_cc_titan_top_accu_shift_clk =3D { + .halt_reg =3D 0x131f0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x131f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_titan_top_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct gdsc cam_cc_titan_top_gdsc =3D { .gdscr =3D 0x131bc, .en_rest_wait_val =3D 0x2, @@ -1776,6 +1794,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] =3D= { [CAM_CC_SLEEP_CLK_SRC] =3D &cam_cc_sleep_clk_src.clkr, [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, [CAM_CC_SM_OBS_CLK] =3D &cam_cc_sm_obs_clk.clkr, + [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =3D NULL, [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, }; @@ -1812,6 +1831,7 @@ static struct qcom_cc_desc cam_cc_sa8775p_desc =3D { }; =20 static const struct of_device_id cam_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-camcc" }, { .compatible =3D "qcom,sa8775p-camcc" }, { } }; @@ -1842,10 +1862,81 @@ static int cam_cc_sa8775p_probe(struct platform_dev= ice *pdev) clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); =20 - /* Keep some clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) { + cam_cc_camnoc_axi_clk_src.cmd_rcgr =3D 0x13154; + cam_cc_camnoc_axi_clk.halt_reg =3D 0x1316c; + cam_cc_camnoc_axi_clk.clkr.enable_reg =3D 0x1316c; + cam_cc_camnoc_dcd_xo_clk.halt_reg =3D 0x13174; + cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg =3D 0x13174; + + cam_cc_csi0phytimer_clk_src.cmd_rcgr =3D 0x15054; + cam_cc_csi1phytimer_clk_src.cmd_rcgr =3D 0x15078; + cam_cc_csi2phytimer_clk_src.cmd_rcgr =3D 0x15098; + cam_cc_csid_clk_src.cmd_rcgr =3D 0x13134; + + cam_cc_mclk0_clk_src.cmd_rcgr =3D 0x15000; + cam_cc_mclk1_clk_src.cmd_rcgr =3D 0x1501c; + cam_cc_mclk2_clk_src.cmd_rcgr =3D 0x15038; + + cam_cc_fast_ahb_clk_src.cmd_rcgr =3D 0x13104; + cam_cc_slow_ahb_clk_src.cmd_rcgr =3D 0x1311c; + cam_cc_xo_clk_src.cmd_rcgr =3D 0x131b8; + cam_cc_sleep_clk_src.cmd_rcgr =3D 0x131d4; + + cam_cc_core_ahb_clk.halt_reg =3D 0x131b4; + cam_cc_core_ahb_clk.clkr.enable_reg =3D 0x131b4; + + cam_cc_cpas_ahb_clk.halt_reg =3D 0x130f4; + cam_cc_cpas_ahb_clk.clkr.enable_reg =3D 0x130f4; + cam_cc_cpas_fast_ahb_clk.halt_reg =3D 0x130fc; + cam_cc_cpas_fast_ahb_clk.clkr.enable_reg =3D 0x130fc; + + cam_cc_csi0phytimer_clk.halt_reg =3D 0x1506c; + cam_cc_csi0phytimer_clk.clkr.enable_reg =3D 0x1506c; + cam_cc_csi1phytimer_clk.halt_reg =3D 0x15090; + cam_cc_csi1phytimer_clk.clkr.enable_reg =3D 0x15090; + cam_cc_csi2phytimer_clk.halt_reg =3D 0x150b0; + cam_cc_csi2phytimer_clk.clkr.enable_reg =3D 0x150b0; + cam_cc_csid_clk.halt_reg =3D 0x1314c; + cam_cc_csid_clk.clkr.enable_reg =3D 0x1314c; + cam_cc_csid_csiphy_rx_clk.halt_reg =3D 0x15074; + cam_cc_csid_csiphy_rx_clk.clkr.enable_reg =3D 0x15074; + cam_cc_csiphy0_clk.halt_reg =3D 0x15070; + cam_cc_csiphy0_clk.clkr.enable_reg =3D 0x15070; + cam_cc_csiphy1_clk.halt_reg =3D 0x15094; + cam_cc_csiphy1_clk.clkr.enable_reg =3D 0x15094; + cam_cc_csiphy2_clk.halt_reg =3D 0x150b4; + cam_cc_csiphy2_clk.clkr.enable_reg =3D 0x150b4; + + cam_cc_mclk0_clk.halt_reg =3D 0x15018; + cam_cc_mclk0_clk.clkr.enable_reg =3D 0x15018; + cam_cc_mclk1_clk.halt_reg =3D 0x15034; + cam_cc_mclk1_clk.clkr.enable_reg =3D 0x15034; + cam_cc_mclk2_clk.halt_reg =3D 0x15050; + cam_cc_mclk2_clk.clkr.enable_reg =3D 0x15050; + + cam_cc_titan_top_gdsc.gdscr =3D 0x131a0; + + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =3D + &cam_cc_titan_top_accu_shift_clk.clkr; + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ + } else { + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + } =20 ret =3D qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); =20 --=20 2.25.1 From nobody Tue Nov 26 11:48:40 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FF592038CC; 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Signed-off-by: Imran Shaik --- Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.y= aml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml index 928131bff4c1..07e5d811d816 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml @@ -18,6 +18,7 @@ description: | properties: compatible: enum: + - qcom,qcs8300-videocc - qcom,sa8775p-videocc =20 clocks: --=20 2.25.1 From nobody Tue Nov 26 11:48:40 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84B4F20127B; Fri, 18 Oct 2024 11:13:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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Signed-off-by: Imran Shaik --- drivers/clk/qcom/videocc-sa8775p.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/videocc-sa8775p.c b/drivers/clk/qcom/videocc-= sa8775p.c index bf5de411fd5d..d0494ba81f5f 100644 --- a/drivers/clk/qcom/videocc-sa8775p.c +++ b/drivers/clk/qcom/videocc-sa8775p.c @@ -524,6 +524,7 @@ static struct qcom_cc_desc video_cc_sa8775p_desc =3D { =20 static const struct of_device_id video_cc_sa8775p_match_table[] =3D { { .compatible =3D "qcom,sa8775p-videocc" }, + { .compatible =3D "qcom,qcs8300-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sa8775p_match_table); @@ -550,6 +551,9 @@ static int video_cc_sa8775p_probe(struct platform_devic= e *pdev) clk_lucid_evo_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_evo_pll_configure(&video_pll1, regmap, &video_pll1_config); =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-videocc")) + regmap_write(regmap, video_cc_mvs0c_div2_div_clk_src.reg, 2); + /* Keep some clocks always enabled */ qcom_branch_set_clk_en(regmap, 0x80ec); /* VIDEO_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x8144); /* VIDEO_CC_SLEEP_CLK */ --=20 2.25.1