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The writes need to be separated by at least 4 cycles of the gated clock. See https://www.nxp.com.cn/docs/en/errata/IMX8_1N94W.pdf The workaround is implemented as follows: 1. For clocks running greater than or equal to 24MHz, a read followed by the write will provide sufficient delay. 2. For clocks running below 24MHz, add a delay of 4 clock cylces after the write to the LPCG register. Fixes: 2f77296d3df9 ("clk: imx: add lpcg clock support") Signed-off-by: Peng Fan --- drivers/clk/imx/clk-lpcg-scu.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c index dd5abd09f3e206a5073767561b517d5b3320b28c..cd42190233662c66f2c354f0a2e= ee3a2531eeb3a 100644 --- a/drivers/clk/imx/clk-lpcg-scu.c +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -6,10 +6,12 @@ =20 #include #include +#include #include #include #include #include +#include =20 #include "clk-scu.h" =20 @@ -41,6 +43,31 @@ struct clk_lpcg_scu { =20 #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) =20 +/* e10858 -LPCG clock gating register synchronization errata */ +static void lpcg_e10858_writel(unsigned long rate, void __iomem *reg, u32 = val) +{ + u32 reg1; + + writel(val, reg); + + if (rate >=3D 24 * HZ_PER_MHZ || rate =3D=3D 0) { + /* + * The time taken to access the LPCG registers from the AP core + * through the interconnect is longer than the minimum delay + * of 4 clock cycles required by the errata. + * Adding a readl will provide sufficient delay to prevent + * back-to-back writes. + */ + reg1 =3D readl(reg); + } else { + /* + * For clocks running below 24MHz, wait a minimum of + * 4 clock cycles. + */ + ndelay(4 * (DIV_ROUND_UP(1000 * HZ_PER_MHZ, rate))); + } +} + static int clk_lpcg_scu_enable(struct clk_hw *hw) { struct clk_lpcg_scu *clk =3D to_clk_lpcg_scu(hw); @@ -57,7 +84,8 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw) val |=3D CLK_GATE_SCU_LPCG_HW_SEL; =20 reg |=3D val << clk->bit_idx; - writel(reg, clk->reg); + + lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); =20 spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); =20 @@ -74,7 +102,7 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw) =20 reg =3D readl_relaxed(clk->reg); reg &=3D ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); - writel(reg, clk->reg); + lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); =20 spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); } @@ -149,9 +177,8 @@ static int __maybe_unused imx_clk_lpcg_scu_resume(struc= t device *dev) * FIXME: Sometimes writes don't work unless the CPU issues * them twice */ - - writel(clk->state, clk->reg); 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While during noirq suspend phase, "hdmi_ipg_clk" is disabled by HDMI IRQ STEER driver, so SError will be triggered when accessing the HDMI LPCG registers. Skip all HDMI LPCG clocks save/restore to avoid SError during system suspend/resume, it will NOT introduce additional power consumption as their parent clock is disabled when suspend. Signed-off-by: Peng Fan --- drivers/clk/imx/clk-lpcg-scu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c index cd42190233662c66f2c354f0a2eee3a2531eeb3a..07deadcf73e929841fe113c7feb= fb6c9b6c5e719 100644 --- a/drivers/clk/imx/clk-lpcg-scu.c +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -163,6 +163,9 @@ static int __maybe_unused imx_clk_lpcg_scu_suspend(stru= ct device *dev) { struct clk_lpcg_scu *clk =3D dev_get_drvdata(dev); =20 + if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) + return 0; + clk->state =3D readl_relaxed(clk->reg); dev_dbg(dev, "save lpcg state 0x%x\n", clk->state); =20 @@ -173,6 +176,9 @@ static int __maybe_unused imx_clk_lpcg_scu_resume(struc= t device *dev) { struct clk_lpcg_scu *clk =3D dev_get_drvdata(dev); =20 + if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) + return 0; + /* * FIXME: Sometimes writes don't work unless the CPU issues * them twice --=20 2.37.1 From nobody Tue Nov 26 11:42:19 2024 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2088.outbound.protection.outlook.com [40.107.247.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55FC8201009; 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Received: from PAXPR04MB8459.eurprd04.prod.outlook.com (2603:10a6:102:1da::15) by DBAPR04MB7285.eurprd04.prod.outlook.com (2603:10a6:10:1ac::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.20; Fri, 18 Oct 2024 09:52:45 +0000 Received: from PAXPR04MB8459.eurprd04.prod.outlook.com ([fe80::165a:30a2:5835:9630]) by PAXPR04MB8459.eurprd04.prod.outlook.com ([fe80::165a:30a2:5835:9630%6]) with mapi id 15.20.8069.016; Fri, 18 Oct 2024 09:52:40 +0000 From: "Peng Fan (OSS)" Date: Fri, 18 Oct 2024 18:00:57 +0800 Subject: [PATCH v2 3/4] clk: imx: fracn-gppll: correct PLL initialization flow Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241018-imx-clk-v1-v2-3-92c0b66ca970@nxp.com> References: <20241018-imx-clk-v1-v2-0-92c0b66ca970@nxp.com> In-Reply-To: <20241018-imx-clk-v1-v2-0-92c0b66ca970@nxp.com> To: Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Aisheng Dong Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Jacky Bai X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Program appropriate value of DIV[ODIV], DIV[RDIV] and DIV[MFI] as per Integer mode. 2. Wait for 5 =CE=BCs. 3. Program the following field in CTRL register. Set CTRL[POWERUP] to 1'b1 to enable PLL block. 4. Poll PLL_STATUS[PLL_LOCK] register, and wait till PLL_STATUS[PLL_LOCK] is 1'b1 and pll_lock output signal is 1'b1. 5. Set CTRL[CLKMUX_EN] to 1'b1 to enable PLL output clock. So move the CLKMUX_EN operation after PLL locked. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-fracn-gppll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-= gppll.c index 591e0364ee5c113859a7b6271c8c11e98a0e0ffc..4749c3e0b7051cf53876664808a= a28742f6861f7 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -303,13 +303,13 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw) val |=3D POWERUP_MASK; writel_relaxed(val, pll->base + PLL_CTRL); =20 - val |=3D CLKMUX_EN; - writel_relaxed(val, pll->base + PLL_CTRL); - ret =3D clk_fracn_gppll_wait_lock(pll); if (ret) return ret; =20 + val |=3D CLKMUX_EN; + writel_relaxed(val, pll->base + PLL_CTRL); + val &=3D ~CLKMUX_BYPASS; writel_relaxed(val, pll->base + PLL_CTRL); =20 --=20 2.37.1 From nobody Tue Nov 26 11:42:19 2024 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2088.outbound.protection.outlook.com [40.107.247.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E4D8201022; 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To make sure the value has been written into the hardware, using readl to read back the register could achieve the goal. current PLL power up flow can be simplified as below: 1. writel_relaxed to set the PLL POWERUP bit; 2. readl_poll_timeout to check the PLL lock bit: a). timeout =3D ktime_add_us(ktime_get(), timeout_us); b). readl the pll the lock reg; c). check if the pll lock bit ready d). check if timeout But in some corner cases, both the write in step 1 and read in step 2 will be blocked by other bus transaction in the SoC for a long time, saying the value into real hardware is just before step b). That means the timeout counting has begins for quite sometime since step a), but value still not written into real hardware until bus released just at a point before step b). Then there maybe chances that the pll lock bit is not ready when readl done but the timeout happens. readl_poll_timeout will err return due to timeout. To avoid such unexpected failure, read back the reg to make sure the write has been done in HW reg. So use readl after writel_relaxed to fix the issue. Since we are here, to avoid udelay to run before writel_relaxed, use readl before udelay. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-fracn-gppll.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-= gppll.c index 4749c3e0b7051cf53876664808aa28742f6861f7..85771afd4698ae6a0d8a7e82193= 301e187049255 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -254,9 +254,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw,= unsigned long drate, pll_div =3D FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | FIELD_PREP(PLL_MFI_MASK, rate->mfi); writel_relaxed(pll_div, pll->base + PLL_DIV); + readl(pll->base + PLL_DIV); if (pll->flags & CLK_FRACN_GPPLL_FRACN) { writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR); writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUME= RATOR); + readl(pll->base + PLL_NUMERATOR); } =20 /* Wait for 5us according to fracn mode pll doc */ @@ -265,6 +267,7 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, = unsigned long drate, /* Enable Powerup */ tmp |=3D POWERUP_MASK; writel_relaxed(tmp, pll->base + PLL_CTRL); + readl(pll->base + PLL_CTRL); =20 /* Wait Lock */ ret =3D clk_fracn_gppll_wait_lock(pll); @@ -302,6 +305,7 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw) =20 val |=3D POWERUP_MASK; writel_relaxed(val, pll->base + PLL_CTRL); + readl(pll->base + PLL_CTRL); =20 ret =3D clk_fracn_gppll_wait_lock(pll); if (ret) --=20 2.37.1