From nobody Tue Nov 26 17:24:00 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4ED081DED74; Thu, 17 Oct 2024 13:15:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729170924; cv=none; b=QFkPvCXRi2lhJ0PZlPdn2OqdWL8O8AKey9l4wu7bPmwqaOqhbUy5NiSfUuatMpRYlcHMOU1ceDhLDb4Prr/NfNZFmrLxVvy8vA84/KuUPDCQIaVzozmnS6iIOK68OeLdWrEUMzt1ah93iTsuKPxT0LJXaFkc1x32OEf9YH79K+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729170924; c=relaxed/simple; bh=BAwPOAmOIzEQJ4SLugo9T4c57oNNMmBoAWU3VeT+tA0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cNMvmmOygVgXrXn8R3ub5bLrWbX7snUy+giY1wSiTUGpOLszDfYK4BUR1+0W6AoZYqAlglbA9IhSilvPD06auOAkaWEG+R0jPUgjgtnqgJzr8+yps/5+tbnSOKeRPrFobWdNGHm35K+wYA1MJSwezB31TT0UwDFln/k5GPS7KME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8814D1570; Thu, 17 Oct 2024 06:15:49 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.35.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 44C813F71E; Thu, 17 Oct 2024 06:15:16 -0700 (PDT) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" Subject: [PATCH v7 08/11] arm64: mm: Avoid TLBI when marking pages as valid Date: Thu, 17 Oct 2024 14:14:31 +0100 Message-Id: <20241017131434.40935-9-steven.price@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241017131434.40935-1-steven.price@arm.com> References: <20241017131434.40935-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When __change_memory_common() is purely setting the valid bit on a PTE (e.g. via the set_memory_valid() call) there is no need for a TLBI as either the entry isn't changing (the valid bit was already set) or the entry was invalid and so should not have been cached in the TLB. Reviewed-by: Catalin Marinas Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose Signed-off-by: Steven Price --- v4: New patch --- arch/arm64/mm/pageattr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 0e270a1c51e6..547a9e0b46c2 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -60,7 +60,13 @@ static int __change_memory_common(unsigned long start, u= nsigned long size, ret =3D apply_to_page_range(&init_mm, start, size, change_page_range, &data); =20 - flush_tlb_kernel_range(start, start + size); + /* + * If the memory is being made valid without changing any other bits + * then a TLBI isn't required as a non-valid entry cannot be cached in + * the TLB. + */ + if (pgprot_val(set_mask) !=3D PTE_VALID || pgprot_val(clear_mask)) + flush_tlb_kernel_range(start, start + size); return ret; } =20 --=20 2.34.1