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Signed-off-by: Sricharan Ramabadhran --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 59 ++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 291 ++++++++++++++++++++ 3 files changed, 351 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5424.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index aea1d69db541..01b8af3dd18f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp468.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp474.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5424-rdp466.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts new file mode 100644 index 000000000000..d4d31026a026 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5424 RDP466 board device tree source + * + * Copyright (c) 2024 The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5424.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ5424 RDP466"; + compatible =3D "qcom,ipq5424-rdp466", "qcom,ipq5424"; + + aliases { + serial0 =3D &uart1; + }; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <24000000>; +}; + diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi new file mode 100644 index 000000000000..76af0d87e9a8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ5424 device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + enable-method =3D "psci"; + reg =3D <0x100>; + next-level-cache =3D <&l2_100>; + + l2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + enable-method =3D "psci"; + reg =3D <0x200>; + next-level-cache =3D <&l2_200>; + + l2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + enable-method =3D "psci"; + reg =3D <0x300>; + next-level-cache =3D <&l2_300>; + + l2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + pmu-dsu { + compatible =3D "arm,dsu-pmu"; + interrupts =3D ; + cpus =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + tz@8a600000 { + reg =3D <0x0 0x8a600000 0x0 0x200000>; + no-map; + }; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq5424-tlmm"; + reg =3D <0 0x01000000 0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 50>; + interrupt-controller; + #interrupt-cells =3D <2>; + + uart1_pins: uart1-state { + pins =3D "gpio43", "gpio44"; + function =3D "uart1"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,ipq5424-gcc"; + reg =3D <0 0x01800000 0 0x40000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x01ac0000 0 0x2000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + uart1: serial@1a84000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0 0x01a84000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_UART1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + }; + }; + + sdhc: mmc@7804000 { + compatible =3D "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>; + reg-names =3D "hc", "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + + status =3D "disabled"; + }; + + intc: interrupt-controller@f200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0xf200000 0 0x10000>, /* GICD */ + <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ + #interrupt-cells =3D <0x3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + interrupts =3D ; + mbi-ranges =3D <672 128>; + msi-controller; + }; + + timer@f420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0 0xf420000 0 0x1000>; + ranges =3D <0 0 0 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@f421000 { + reg =3D <0xf421000 0x1000>, + <0xf422000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@f423000 { + reg =3D <0xf423000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + status =3D "disabled"; + }; + + frame@f425000 { + reg =3D <0xf425000 0x1000>, + <0xf426000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + status =3D "disabled"; + }; + + frame@f427000 { + reg =3D <0xf427000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + status =3D "disabled"; + }; + + frame@f429000 { + reg =3D <0xf429000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + status =3D "disabled"; + }; + + frame@f42b000 { + reg =3D <0xf42b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + status =3D "disabled"; + }; + + frame@f42d000 { + reg =3D <0xf42d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + status =3D "disabled"; + }; + }; + + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; +}; --=20 2.34.1