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charset="utf-8" From: Lad Prabhakar Hogging of gpio pins used as interrupts is not required, as the rzg2l pinctrl driver sets the direction as input when the pin is requested as GPIO interrupt. Signed-off-by: Lad Prabhakar --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 18 ---------------- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 21 ------------------- 2 files changed, 39 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 71424e69939e..6e95933cd7ef 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -196,15 +196,6 @@ &sdhi2 { #endif =20 &pinctrl { -#if SW_CONFIG3 =3D=3D SW_ON - eth0-phy-irq-hog { - gpio-hog; - gpios =3D ; - input; - line-name =3D "eth0-phy-irq"; - }; -#endif - eth0_pins: eth0 { txc { pinmux =3D ; /* ET0_TXC */ @@ -239,15 +230,6 @@ mux { }; }; =20 -#if SW_CONFIG3 =3D=3D SW_ON - eth1-phy-irq-hog { - gpio-hog; - gpios =3D ; - input; - line-name =3D "eth1-phy-irq"; - }; -#endif - eth1_pins: eth1 { txc { pinmux =3D ; /* ET1_TXC */ diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot= /dts/renesas/rzg3s-smarc.dtsi index 4509151344c4..baeca5ff5d61 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -71,27 +71,6 @@ &i2c0 { }; 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Thu, 17 Oct 2024 04:39:51 -0700 (PDT) Received: from prasmi.Home ([2a02:c7c:e309:f400:f6f5:4306:392d:908d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d7fbf82b1sm7060399f8f.72.2024.10.17.04.39.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 04:39:50 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Linus Walleij , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/7] pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper Date: Thu, 17 Oct 2024 12:39:37 +0100 Message-ID: <20241017113942.139712-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 5eefbace7d91..8ffb9430a134 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2433,21 +2433,6 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct g= pio_chip *gc, return ret; } =20 -static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, - union gpio_irq_fwspec *gfwspec, - unsigned int parent_hwirq, - unsigned int parent_type) -{ - struct irq_fwspec *fwspec =3D &gfwspec->fwspec; - - fwspec->fwnode =3D chip->irq.parent_domain->fwnode; - fwspec->param_count =3D 2; - fwspec->param[0] =3D parent_hwirq; - fwspec->param[1] =3D parent_type; - - return 0; -} - static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) { struct irq_domain *domain =3D pctrl->gpio_chip.irq.domain; @@ -2649,7 +2634,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *= pctrl) girq->fwnode =3D dev_fwnode(pctrl->dev); girq->parent_domain =3D parent_domain; girq->child_to_parent_hwirq =3D rzg2l_gpio_child_to_parent_hwirq; - girq->populate_parent_alloc_arg =3D rzg2l_gpio_populate_parent_fwspec; + girq->populate_parent_alloc_arg =3D gpiochip_populate_parent_fwspec_twoce= ll; girq->child_irq_domain_ops.free =3D rzg2l_gpio_irq_domain_free; girq->init_valid_mask =3D rzg2l_init_irq_valid_mask; =20 --=20 2.43.0 From nobody Tue Nov 26 15:17:33 2024 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5911DA619; Thu, 17 Oct 2024 11:39:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" From: Lad Prabhakar The `free` callback in `struct irq_domain_ops` expects to free nr_irqs interrupts starting from virq. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 39 ++++++++++++++----------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 8ffb9430a134..1a09ccbfebad 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2477,25 +2477,30 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pin= ctrl *pctrl) static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned= int virq, unsigned int nr_irqs) { + struct rzg2l_pinctrl *pctrl; + irq_hw_number_t hwirq; + struct gpio_chip *gc; + unsigned long flags; struct irq_data *d; + unsigned int i, j; =20 - d =3D irq_domain_get_irq_data(domain, virq); - if (d) { - struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, g= pio_chip); - irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; 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charset="utf-8" From: Lad Prabhakar The order of function calls in the gpio free operation should be the reverse of that in the gpio request operation. Thus move pinctrl_gpio_free() call at the very end in rzg2l_gpio_free() Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 1a09ccbfebad..d8b942fbf537 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1774,8 +1774,6 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, u= nsigned int offset) { unsigned int virq; =20 - pinctrl_gpio_free(chip, offset); - virq =3D irq_find_mapping(chip->irq.domain, offset); if (virq) irq_dispose_mapping(virq); @@ -1785,6 +1783,8 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, u= nsigned int offset) * drive the GPIO pin as an output. */ rzg2l_gpio_direction_input(chip, offset); + + pinctrl_gpio_free(chip, offset); } =20 static const char * const rzg2l_gpio_names[] =3D { --=20 2.43.0 From nobody Tue Nov 26 15:17:33 2024 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E4C41DC1A2; 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charset="utf-8" From: Lad Prabhakar Drop calling rzg2l_gpio_request() in rzg2l_gpio_interrupt_input_mode() this was added to handle special case of bootloader setting the same gpio pin as function. When GPIO pin is requested as interrupt through `gpios` DT property the gpio_request() is called through the code path and when releasing GPIO pin it goes through the gpio_free() path, so drop calling gpio_request() in rzg2l_gpio_child_to_parent_hwirq() path and also drop rzg2l_gpio_free() in rzg2l_gpio_irq_domain_free(). This fixes case where rzg2l_gpio_free() was being called twice after the GPIO interrupt pin is freed (after unbinding the module). When GPIO pin is requested as interrupt through `interrupt` DT property this doesn't go through gpio_request()/gpio_free() code path. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 33 +++---------------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index d8b942fbf537..b9a8bf43a92a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2372,26 +2372,6 @@ static const struct irq_chip rzg2l_gpio_irqchip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 -static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigne= d int offset) -{ - struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(chip); - const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[offset]; - u64 *pin_data =3D pin_desc->drv_data; - u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); - u8 bit =3D RZG2L_PIN_ID_TO_PIN(offset); - u8 reg8; - int ret; - - reg8 =3D readb(pctrl->base + PMC(off)); - if (reg8 & BIT(bit)) { - ret =3D rzg2l_gpio_request(chip, offset); - if (ret) - return ret; - } - - return rzg2l_gpio_direction_input(chip, offset); -} - static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned int child, unsigned int child_type, @@ -2407,17 +2387,15 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct = gpio_chip *gc, if (gpioint < 0) return gpioint; =20 - ret =3D rzg2l_gpio_interrupt_input_mode(gc, child); + ret =3D rzg2l_gpio_direction_input(gc, child); if (ret) return ret; =20 spin_lock_irqsave(&pctrl->bitmap_lock, flags); irq =3D bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUP= T, get_order(1)); spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); - if (irq < 0) { - ret =3D -ENOSPC; - goto err; - } + if (irq < 0) + return -ENOSPC; =20 rzg2l_gpio_irq_endisable(pctrl, child, true); pctrl->hwirq[irq] =3D child; @@ -2427,10 +2405,6 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct g= pio_chip *gc, *parent_type =3D IRQ_TYPE_LEVEL_HIGH; *parent =3D RZG2L_PACK_HWIRQ(gpioint, irq); return 0; - -err: - rzg2l_gpio_free(gc, child); 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Thu, 17 Oct 2024 04:39:55 -0700 (PDT) Received: from prasmi.Home ([2a02:c7c:e309:f400:f6f5:4306:392d:908d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d7fbf82b1sm7060399f8f.72.2024.10.17.04.39.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 04:39:55 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Linus Walleij , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 6/7] pinctrl: pinmux: Introduce API to check if a pin is requested Date: Thu, 17 Oct 2024 12:39:41 +0100 Message-ID: <20241017113942.139712-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce `pin_requested` API to check if a pin is currently requested. This API allows pinctrl drivers to verify whether a pin is requested or not by checking if the pin is owned by either `gpio_owner` or `mux_owner`. GPIO pins used as interrupts through the `interrupts` DT property do not follow the usual `gpio_request`/`pin_request` path, unlike GPIO pins used as interrupts via the `gpios` property. As a result, such pins were reported as `UNCLAIMED` in the `pinmux-pins` sysfs file, even though they were in use as interrupts. With the newly introduced API, pinctrl drivers can check if a pin is already requested by the pinctrl core and ensure that pin is requested during when using as irq. This helps to ensure that the `pinmux-pins` sysfs file reflects the correct status of the pin. Signed-off-by: Lad Prabhakar Reviewed-by: Linus Walleij --- drivers/pinctrl/pinmux.c | 14 ++++++++++++++ drivers/pinctrl/pinmux.h | 5 +++++ 2 files changed, 19 insertions(+) diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 02033ea1c643..6c3d18b162ad 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -99,6 +99,20 @@ bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pct= ldev, unsigned int pin) return !(ops->strict && !!desc->gpio_owner); } =20 +bool pin_requested(struct pinctrl_dev *pctldev, int pin) +{ + struct pin_desc *desc; + + desc =3D pin_desc_get(pctldev, pin); + if (!desc) + return false; + + if (!desc->gpio_owner && !desc->mux_owner) + return false; + + return true; +} + /** * pin_request() - request a single pin to be muxed in, typically for GPIO * @pctldev: the associated pin controller device diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 2965ec20b77f..6d854eebaad4 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -42,6 +42,7 @@ int pinmux_map_to_setting(const struct pinctrl_map *map, void pinmux_free_setting(const struct pinctrl_setting *setting); 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Thu, 17 Oct 2024 04:39:56 -0700 (PDT) Received: from prasmi.Home ([2a02:c7c:e309:f400:f6f5:4306:392d:908d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d7fbf82b1sm7060399f8f.72.2024.10.17.04.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 04:39:56 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Linus Walleij , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 7/7] pinctrl: renesas: pinctrl-rzg2l: Override irq_request/release_resources Date: Thu, 17 Oct 2024 12:39:42 +0100 Message-ID: <20241017113942.139712-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Override the default `irq_request_resources` and `irq_release_resources` functions with `rzg2l_gpio_irq_request_resources` and `rzg2l_gpio_irq_release_resources` in the RZ/G2L pinctrl driver. The `rzg2l_gpio_irq_request_resources()` function now ensures that the pin is requested by the pinctrl core before locking the GPIO as an IRQ. This ensures that the `pinmux-pins` file in sysfs correctly reports the pin as claimed. Additionally, the `rzg2l_gpio_direction_input()` call is moved into the `rzg2l_gpio_irq_request_resources()` callback, as it makes sense to configure the GPIO pin as an input after it has been requested. The `rzg2l_gpio_irq_release_resources()` function unlocks the GPIO as an IRQ and then frees the GPIO, ensuring proper cleanup when the IRQ is no longer needed. This guarantees that the `pinmux-pins` file in sysfs correctly reports the pin as unclaimed. Also add a `pin_requested()` check in `rzg2l_gpio_free()` to return early if the pin is already released. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 41 +++++++++++++++++++++---- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index b9a8bf43a92a..47b3e296d094 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1772,8 +1772,12 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, un= signed int offset) =20 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) { + struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(chip); unsigned int virq; =20 + if (!pin_requested(pctrl->pctl, offset)) + return; + virq =3D irq_find_mapping(chip->irq.domain, offset); if (virq) irq_dispose_mapping(virq); @@ -2357,6 +2361,35 @@ static int rzg2l_gpio_irq_set_wake(struct irq_data *= data, unsigned int on) return 0; } =20 +static int rzg2l_gpio_irq_request_resources(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, gp= io_chip); + unsigned int child =3D irqd_to_hwirq(d); + int ret; + + if (!pin_requested(pctrl->pctl, child)) { + ret =3D rzg2l_gpio_request(gc, child); + if (ret) + return ret; + } + + ret =3D rzg2l_gpio_direction_input(gc, child); + if (ret) + return ret; + + return gpiochip_irq_reqres(d); +} + +static void rzg2l_gpio_irq_release_resources(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + unsigned int child =3D irqd_to_hwirq(d); + + gpiochip_irq_relres(d); + rzg2l_gpio_free(gc, child); +} + static const struct irq_chip rzg2l_gpio_irqchip =3D { .name =3D "rzg2l-gpio", .irq_disable =3D rzg2l_gpio_irq_disable, @@ -2368,8 +2401,9 @@ static const struct irq_chip rzg2l_gpio_irqchip =3D { .irq_print_chip =3D rzg2l_gpio_irq_print_chip, .irq_set_affinity =3D irq_chip_set_affinity_parent, .irq_set_wake =3D rzg2l_gpio_irq_set_wake, + .irq_request_resources =3D rzg2l_gpio_irq_request_resources, + .irq_release_resources =3D rzg2l_gpio_irq_release_resources, .flags =3D IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, @@ -2381,16 +2415,11 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct = gpio_chip *gc, struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(gc); unsigned long flags; int gpioint, irq; - int ret; =20 gpioint =3D rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; =20 - ret =3D rzg2l_gpio_direction_input(gc, child); - if (ret) - return ret; - spin_lock_irqsave(&pctrl->bitmap_lock, flags); irq =3D bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUP= T, get_order(1)); spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); --=20 2.43.0