From nobody Tue Nov 26 17:17:17 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A9F017E46E; Thu, 17 Oct 2024 03:04:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729134282; cv=none; b=pJh01+RrB3D4NV1/lV86pGrrCYvBhvMK6P/YRxUbg/vIPW50UdZjU5WEGNLtO97NLdvyMpF9ZMZnc28NFhb8DGRxho+L78lgUztsejtfrdCJRrCBKUqaUTGMcHA6qyFSmEOCn0SoKuh7LwxjYqUthfc4SGkOL2ZuKRs+6P6YcCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729134282; c=relaxed/simple; bh=eBFW8CfQ3gEDPL7ZftKPyZ/FKbZzXRdT+yLK3E1jol0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=vGd12qDeKvhO17urW9ry+d5C4vEiw6FloGNoTZ10UY2oStDqM1aHWewKFR0u7Q78ma+gtVfWphw5Et183ZEfE3nP5uU/XjUA2UL39JBKNL84dwfurNBLUUIHeY4u1MM407zFzWvYdSBrvujPVBg00VwKy6hmYQKsZLSkIlhrCHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=et5cHCHT; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="et5cHCHT" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49GIoWCe011837; Thu, 17 Oct 2024 03:04:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ksjmpu+gP6F 6t3NW+fwH7MutOFcoJ/x3YG3lGuhFixw=; b=et5cHCHTlBgcDQJG0TKTEjU74tW hAoJwziJ2sk180Zz185Io7eYSyn5eTk1RM0OcB0p/mAnD/FvC9xeicmZNRHej0Cz VRzmQqy/MeqTEe0Ew87R21PHCqhTsxPxF+94mz4MMfpllRZmlk5ZS938micUdQFm x8vhfB8hhRN6NyE0D0iT979MCKeL2oCxdmfkciFY0AOKBTp+TlP9JQPIr0WClZW0 akwLSI93jVMT5kKgVGQF5eClpjiNf34atdChhZF/icaKMMmmJP0AOx3ULDa7bZnW XvMySEPcwsLkrqd9zKMzZrPyt/FBSL16LaVXcpQp3YWO0+0GelnfUwd7DLw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42abm5jhqd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 03:04:22 +0000 (GMT) Received: from pps.filterd (NALASPPMTA05.qualcomm.com [127.0.0.1]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 49H34JWW028360; Thu, 17 Oct 2024 03:04:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA05.qualcomm.com (PPS) with ESMTPS id 42aj55ku18-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 03:04:21 +0000 Received: from NALASPPMTA05.qualcomm.com (NALASPPMTA05.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49H301hi021671; Thu, 17 Oct 2024 03:04:21 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA05.qualcomm.com (PPS) with ESMTPS id 49H34L1A028403 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 03:04:21 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id 164CB650; Wed, 16 Oct 2024 20:04:21 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, johan+linaro@kernel.org, Qiang Yu Subject: [PATCH v7 7/7] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Date: Wed, 16 Oct 2024 20:04:12 -0700 Message-Id: <20241017030412.265000-8-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241017030412.265000-1-quic_qianyu@quicinc.com> References: <20241017030412.265000-1-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: cTtxH9lpYaWT60EftiX-FzgVQLFh_two X-Proofpoint-GUID: cTtxH9lpYaWT60EftiX-FzgVQLFh_two X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170021 Content-Type: text/plain; charset="utf-8" Describe PCIe3 controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe3. Signed-off-by: Qiang Yu Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Reviewed-by: Johan Hovold --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 204 ++++++++++++++++++++++++- 1 file changed, 203 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a36076e3c56b..c615c930cf0c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -744,7 +744,7 @@ gcc: clock-controller@100000 { =20 clocks =3D <&bi_tcxo_div2>, <&sleep_clk>, - <0>, + <&pcie3_phy>, <&pcie4_phy>, <&pcie5_phy>, <&pcie6a_phy>, @@ -2907,6 +2907,208 @@ mmss_noc: interconnect@1780000 { #interconnect-cells =3D <2>; }; =20 + pcie3: pcie@1bd0000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01bd0000 0x0 0x3000>, + <0x0 0x78000000 0x0 0xf1d>, + <0x0 0x78000f40 0x0 0xa8>, + <0x0 0x78001000 0x0 0x1000>, + <0x0 0x78100000 0x0 0x100000>, + <0x0 0x01bd3000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, + <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, + <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <3>; + num-lanes =3D <8>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks =3D <&gcc GCC_PCIE_3_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_south_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_3_BCR>, + <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_3_GDSC>; + + phys =3D <&pcie3_phy>; + phy-names =3D "pciephy"; + + operating-points-v2 =3D <&pcie3_opp_table>; + + status =3D "disabled"; + + pcie3_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 1 x4 and GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 1 x8 and GEN 2 x4 */ + opp-20000000 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + }; + + /* GEN 2 x8 */ + opp-40000000 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 3 x4 and GEN 4 x2 */ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + }; + + /* GEN 3 x8 and GEN 4 x4 */ + opp-64000000 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + }; + + /* GEN 4 x8 */ + opp-128000000 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <15753000 1>; + }; + }; + }; + + pcie3_phy: phy@1be0000 { + compatible =3D "qcom,x1e80100-qmp-gen4x8-pcie-phy"; + reg =3D <0 0x01be0000 0 0x10000>; + + clocks =3D <&gcc GCC_PCIE_3_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_8L_CLKREF_EN>, + <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3_PIPE_CLK>, + <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets =3D <&gcc GCC_PCIE_3_PHY_BCR>, + <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc GCC_PCIE_3_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie3_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + pcie6a: pci@1bf8000 { device_type =3D "pci"; compatible =3D "qcom,pcie-x1e80100"; --=20 2.34.1