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Thu, 17 Oct 2024 03:04:20 +0000 (GMT) Received: from pps.filterd (NALASPPMTA05.qualcomm.com [127.0.0.1]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 49H2wd5O019941; Thu, 17 Oct 2024 03:04:19 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA05.qualcomm.com (PPS) with ESMTPS id 42aj55ku0w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 03:04:19 +0000 Received: from NALASPPMTA05.qualcomm.com (NALASPPMTA05.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49H301hg021671; Thu, 17 Oct 2024 03:04:18 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA05.qualcomm.com (PPS) with ESMTPS id 49H34ItY028351 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 03:04:18 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id 81173650; Wed, 16 Oct 2024 20:04:18 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, johan+linaro@kernel.org, Qiang Yu Subject: [PATCH v7 5/7] PCI: qcom: Remove BDF2SID mapping config for SC8280X family SoC Date: Wed, 16 Oct 2024 20:04:10 -0700 Message-Id: <20241017030412.265000-6-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241017030412.265000-1-quic_qianyu@quicinc.com> References: <20241017030412.265000-1-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PlsxN7ofUOsYMUc0WlTFl8elfxSH2X8- X-Proofpoint-GUID: PlsxN7ofUOsYMUc0WlTFl8elfxSH2X8- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170021 Content-Type: text/plain; charset="utf-8" On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by introducing a new ops struct, namely ops_1_21_0 which is same as ops_1_9_0 without config_sid() callback so that BDF2SID mapping won't be configured during init. Fixes: 70574511f3fc ("PCI: qcom: Add support for SC8280XP") Signed-off-by: Qiang Yu Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 88a98be930e3..468bd4242e61 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 =3D { .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, }; =20 +/* Qcom IP rev.: 1.21.0 */ +static const struct qcom_pcie_ops ops_1_21_0 =3D { + .get_resources =3D qcom_pcie_get_resources_2_7_0, + .init =3D qcom_pcie_init_2_7_0, + .post_init =3D qcom_pcie_post_init_2_7_0, + .host_post_init =3D qcom_pcie_host_post_init_2_7_0, + .deinit =3D qcom_pcie_deinit_2_7_0, + .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 =3D { .ops =3D &ops_1_0_0, }; @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 =3D { }; =20 static const struct qcom_pcie_cfg cfg_sc8280xp =3D { - .ops =3D &ops_1_9_0, + .ops =3D &ops_1_21_0, .no_l0s =3D true, }; =20 --=20 2.34.1