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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a00007078sm821563e87.212.2024.10.17.09.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 09:57:28 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 17 Oct 2024 19:57:03 +0300 Subject: [PATCH 13/14] clk: qcom: dispcc-sm8550: enable support for SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241017-sar2130p-clocks-v1-13-f75e740f0a8d@linaro.org> References: <20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org> In-Reply-To: <20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3462; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=fbvu1iWZ6scTvWN5W30gahzXbQWngQ6ZKmmxqc762gA=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnEUHelKbwpXrCLcfkbLA7qsgVjwlFOHUuLisTN ArAU0n6afSJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxFB3gAKCRAU23LtvoBl uDGfD/9wfL32JAfP60O6G+BHASkW5WfD8VWGCMiDYhmMfP9juzbIu9/VnhrdpkL8ZxV5Bzijj7w t6BzcYqROOZZKma1+XrKgcKttzFXVO3tupfYuSWmobuNmvZijbmJmwnso4/b9tdfyVryZxh2uxH oVSkQnLmh75oEX7bNLZomjR4rxqnkQp04c2nZVRkOTuiy3ojN8lOtnbmndRYWHbq2AhyhO/KzH+ RHU2Y1JZbXfquCs8K1EA9xEIPSFmrUvW3BnMxSpFVcaSRqS5KkKz5WPqiywgaJDyUcZpwzyaZ8+ oI4jNKtV0xnZu30EASg/e5OYzmvkhXtugkhiCIowtC1UYD6L6tUzL1ZSkSqpgmYVKJoXZxVKKsk xGjWtvxPuUNX37mGuPUcttBxl0RY54i2apEDAABGc6tzkP36/DIfSrSbgp7QU9LSnEgm8fc3eED R9dbv1G9oJgmvttVbC09tBQ8Zhy6Mhwj0j5vMrHkEUni3spk5ATZfLvuBwHoPuyKxKZDkATHItD xun5HqKVfguEohdQJXfIS4aIzVavs1qL2WalVXdT3mVC1RFRodX6/1fUGQH9nBbDBwsvz0qZDtv JEsHoyRonCPUV05F8c66m5KbOJEn3jgZqLQyj2brs9fBgvhNbdmVTJ0cL1n7MN99oGNkpTSyZRE WedYc4h8pZOdqlg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The display clock controller on SAR2130P is very close to the clock controller on SM8550 (and SM8650). Reuse existing driver to add support for the controller on SAR2130P. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/Kconfig | 4 ++-- drivers/clk/qcom/dispcc-sm8550.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 5f7bf9db76cfcef1ab18a6ba09fb4dc506695f9d..f314f26fe136c0fc1612edc0cca= 23c4deba5cd9f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -968,10 +968,10 @@ config SM_DISPCC_8450 config SM_DISPCC_8550 tristate "SM8550 Display Clock Controller" depends on ARM64 || COMPILE_TEST - depends on SM_GCC_8550 || SM_GCC_8650 + depends on SM_GCC_8550 || SM_GCC_8650 || SAR_GCC_2130P help Support for the display clock controller on Qualcomm Technologies, Inc - SM8550 or SM8650 devices. + SAR2130P, SM8550 or SM8650 devices. Say Y if you want to support display devices and functionality such as splash screen. =20 diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index 7f9021ca0ecb0ef743a40bed1bb3d2cbcfa23dc7..e41d4104d77021cae6438886bcb= 7015469d86a9f 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -75,7 +75,7 @@ static struct pll_vco lucid_ole_vco[] =3D { { 249600000, 2000000000, 0 }, }; =20 -static const struct alpha_pll_config disp_cc_pll0_config =3D { +static struct alpha_pll_config disp_cc_pll0_config =3D { .l =3D 0xd, .alpha =3D 0x6492, .config_ctl_val =3D 0x20485699, @@ -106,7 +106,7 @@ static struct clk_alpha_pll disp_cc_pll0 =3D { }, }; =20 -static const struct alpha_pll_config disp_cc_pll1_config =3D { +static struct alpha_pll_config disp_cc_pll1_config =3D { .l =3D 0x1f, .alpha =3D 0x4000, .config_ctl_val =3D 0x20485699, @@ -594,6 +594,13 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk= _src[] =3D { { } }; =20 +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] =3D { + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] =3D { F(19200000, P_BI_TCXO, 1, 0, 0), F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), @@ -1750,6 +1757,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc =3D { }; =20 static const struct of_device_id disp_cc_sm8550_match_table[] =3D { + { .compatible =3D "qcom,sar2130p-dispcc" }, { .compatible =3D "qcom,sm8550-dispcc" }, { .compatible =3D "qcom,sm8650-dispcc" }, { } @@ -1780,6 +1788,12 @@ static int disp_cc_sm8550_probe(struct platform_devi= ce *pdev) disp_cc_mdss_mdp_clk_src.freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src_sm86= 50; disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = =3D &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw; + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-disp= cc")) { + disp_cc_pll0_config.l =3D 0x1f; + disp_cc_pll0_config.alpha =3D 0x4000; + disp_cc_pll0_config.user_ctl_val =3D 0x1; + disp_cc_pll1_config.user_ctl_val =3D 0x1; + disp_cc_mdss_mdp_clk_src.freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src_sar2= 130p; } =20 clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); --=20 2.39.5