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Thu, 17 Oct 2024 15:36:02 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49HFa1KZ020141 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 15:36:01 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 08:35:57 -0700 From: Krishna chaitanya chundru Date: Thu, 17 Oct 2024 21:05:50 +0530 Subject: [PATCH v6 1/2] PCI: starfive: Enable PCIe controller's runtime PM before probing host bridge Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241017-runtime_pm-v6-1-55eab5c2c940@quicinc.com> References: <20241017-runtime_pm-v6-0-55eab5c2c940@quicinc.com> In-Reply-To: <20241017-runtime_pm-v6-0-55eab5c2c940@quicinc.com> To: Kevin Xie , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , "Rob Herring" , Bjorn Helgaas CC: , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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To enable runtime PM of PCIe host bridge device (child device), it is must to enable parent device's runtime PM to avoid seeing the below warning from PM core: pcie-starfive 940000000.pcie: Enabling runtime PM for inactive device with active children Fix this issue by enabling starfive pcie controller device's runtime PM before calling pci_host_probe() in plda_pcie_host_init(). Tested-by: Marek Szyprowski Signed-off-by: Mayank Rana Reviewed-by: Manivannan Sadhasivam --- v3->v6: - no change Link to v3: https://patchwork.kernel.org/project/linux-pci/patch/2024101416= 2607.1247611-1-quic_mrana@quicinc.com/ v2->v3: - Update commit description based on Mani's feedback - Updated Reviewed-by tag Link to v2: https://patchwork.kernel.org/project/linux-pci/patch/2024101123= 5530.3919347-1-quic_mrana@quicinc.com/ v1->v2: Updated commit description based on Bjorn's feedback Link to v1: https://patchwork.kernel.org/project/linux-pci/patch/2024101020= 2950.3263899-1-quic_mrana@quicinc.com/ --- drivers/pci/controller/plda/pcie-starfive.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/cont= roller/plda/pcie-starfive.c index c9933ecf6833..0564fdce47c2 100644 --- a/drivers/pci/controller/plda/pcie-starfive.c +++ b/drivers/pci/controller/plda/pcie-starfive.c @@ -404,6 +404,9 @@ static int starfive_pcie_probe(struct platform_device *= pdev) if (ret) return ret; =20 + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + plda->host_ops =3D &sf_host_ops; plda->num_events =3D PLDA_MAX_EVENT_NUM; /* mask doorbell event */ @@ -413,11 +416,12 @@ static int starfive_pcie_probe(struct platform_device= *pdev) plda->events_bitmap <<=3D PLDA_NUM_DMA_EVENTS; ret =3D plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops, &stf_pcie_event); - if (ret) + if (ret) { + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); return ret; + } =20 - pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); platform_set_drvdata(pdev, pcie); =20 return 0; --=20 2.34.1 From nobody Tue Nov 26 13:27:18 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADD291DF252; Thu, 17 Oct 2024 15:36:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 17 Oct 2024 15:36:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49HFa5dV020314 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 15:36:05 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 08:36:01 -0700 From: Krishna chaitanya chundru Date: Thu, 17 Oct 2024 21:05:51 +0530 Subject: [PATCH v6 2/2] PCI: Enable runtime pm of the host bridge Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241017-runtime_pm-v6-2-55eab5c2c940@quicinc.com> References: <20241017-runtime_pm-v6-0-55eab5c2c940@quicinc.com> In-Reply-To: <20241017-runtime_pm-v6-0-55eab5c2c940@quicinc.com> To: Kevin Xie , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , "Rob Herring" , Bjorn Helgaas CC: , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729179352; l=3930; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=llSVQH0QoXZvzZ7i15pua9CmboZduEdW7xXVZb9NBPM=; b=OmRc9u26RdgyYNKBosU1tQn6OU1Tx42+UBOFF2KAqDp9M8fyis3Nshr5kwNb6xcumEAqmE5RR AMSpWlLbwpRCQinEBoXScmJefSgz6wdYL6uj8eduD3q7OtKvRCgDzTo X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: bbPYzdNBGg0Uu81EuQLqZXbfNatAOFS2 X-Proofpoint-GUID: bbPYzdNBGg0Uu81EuQLqZXbfNatAOFS2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170107 The Controller driver is the parent device of the PCIe host bridge, PCI-PCI bridge and PCIe endpoint as shown below. PCIe controller(Top level parent & parent of host bridge) | v PCIe Host bridge(Parent of PCI-PCI bridge) | v PCI-PCI bridge(Parent of endpoint driver) | v PCIe endpoint driver Now, when the controller device goes to runtime suspend, PM framework will check the runtime PM state of the child device (host bridge) and will find it to be disabled. So it will allow the parent (controller device) to go to runtime suspend. Only if the child device's state was 'active' it will prevent the parent to get suspended. It is a property of the runtime PM framework that it can only follow continuous dependency chains. That is, if there is a device with runtime PM disabled in a dependency chain, runtime PM cannot be enabled for devices below it and above it in that chain both at the same time. Since runtime PM is disabled for host bridge, the state of the child devices under the host bridge is not taken into account by PM framework for the top level parent, PCIe controller. So PM framework, allows the controller driver to enter runtime PM irrespective of the state of the devices under the host bridge. And this causes the topology breakage and also possible PM issues like controller driver goes to runtime suspend while endpoint driver is doing some transfers. Because of the above, in order to enable runtime PM for a PCIe controller device, one needs to ensure that runtime PM is enabled for all devices in every dependency chain between it and any PCIe endpoint (as runtime PM is enabled for PCIe endpoints). This means that runtime PM needs to be enabled for the host bridge device, which is present in all of these dependency chains. After this change, the host bridge device will be runtime-suspended by the runtime PM framework automatically after suspending its last child and it will be runtime-resumed automatically before resuming its first child which will allow the runtime PM framework to track dependencies between the host bridge device and all of its descendants. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- Changes in v6: - no change Changes in v5: - call pm_runtime_no_callbacks() as suggested by Rafael. - include the commit texts as suggested by Rafael. - Link to v4: https://lore.kernel.org/linux-pci/20240708-runtime_pm-v4-1-c0= 2a3663243b@quicinc.com/ Changes in v4: - Changed pm_runtime_enable() to devm_pm_runtime_enable() (suggested by may= ank) - Link to v3: https://lore.kernel.org/lkml/20240609-runtime_pm-v3-1-3d0460b= 49d60@quicinc.com/ Changes in v3: - Moved the runtime API call's from the dwc driver to PCI framework as it is applicable for all (suggested by mani) - Updated the commit message. - Link to v2: https://lore.kernel.org/all/20240305-runtime_pm_enable-v2-1-a= 849b74091d1@quicinc.com Changes in v2: - Updated commit message as suggested by mani. - Link to v1: https://lore.kernel.org/r/20240219-runtime_pm_enable-v1-1-d39= 660310504@quicinc.com --- drivers/pci/probe.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4f68414c3086..8409e1dde0d1 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -3106,6 +3106,11 @@ int pci_host_probe(struct pci_host_bridge *bridge) pcie_bus_configure_settings(child); =20 pci_bus_add_devices(bus); + + pm_runtime_set_active(&bridge->dev); + pm_runtime_no_callbacks(&bridge->dev); + devm_pm_runtime_enable(&bridge->dev); + return 0; } EXPORT_SYMBOL_GPL(pci_host_probe); --=20 2.34.1