From nobody Tue Nov 26 17:36:36 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF8A61B2189; Wed, 16 Oct 2024 23:31:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121463; cv=none; b=iCIwj8qVchMr1/P3O4P8Lo5x7kV4sAquNQu4fRJxVrGJbs29v8yWLhrJ33NCVL/NrjepAFW6QDOo2os+IcEwkucdMR++MRiDEYfH6Cr1m+vkcBa/LbAV5ROfRPnHL64N/t8U/8OS2pOsTQXXwRZ0qBAxskhUZnDf7qDLBKwQLZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121463; c=relaxed/simple; bh=Bvd5/aDKVnBXSMgbh6YxppH/ko44fGCm0qPggmep0zo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NRslKr3IBZhlLxJttKeT5wYMX7CaZr6qhf7DAAcBfsbI/BnpCUGpxDNJRdI1TmhKi480MAJI0zAZD18/wClkIuKVCdJ/ioXBsRWFGl8qJuuje0bKwTjB1rNOvh0qv6F72pvdnqnWdDNRkMA2UFd4OlFZgb/yDY4jBWLS6M/IkDE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=cpyl2Lrj; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cpyl2Lrj" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUl3s095571; Wed, 16 Oct 2024 18:30:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729121447; bh=yJPRxcazgjxA07gw7TbK7yglPZYiEd2pkShwp68iM60=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cpyl2LrjGDyEgzwegVqdNcoZ4avD2NDyNlZ9BahOEazlxrXQ+A7OLcvq927eeCbq6 7IXKxHMbIBK016VOgjeWHvGezx6Ldzpx0t9fDs6eG/iXJeu016TrmeaZZ5FI/y2LtW 3cBjEpu7VgGjxalzyMvKsbQKdWsY194vuUirzTY0= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49GNUlQ9011745 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2024 18:30:47 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:46 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7k070988; Wed, 16 Oct 2024 18:30:46 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region Date: Wed, 16 Oct 2024 18:30:42 -0500 Message-ID: <20241016233044.240699-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 9386bf3ef9f68..45091aa0fb1b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,6 +32,11 @@ scm_conf: scm-conf@100000 { #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x1c000>; =20 + pcie1_ctrl: pcie-ctrl@4074 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4074 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x4080 0x20>; @@ -745,7 +750,7 @@ pcie1_rc: pcie@2910000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <4>; power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; --=20 2.39.2