From nobody Tue Nov 26 15:22:55 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF84E161326; Wed, 16 Oct 2024 23:31:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121462; cv=none; b=PBoAxJD7TTUAjiJ72Lk1QVWQGX3F2yFqLtpu0Xmsush4n4aLGllONzbnaRd0t9Zf6r7j10FmtbFZ5Y0/WwHUwSxfu5dvdZBTR0IoRNP6yXwrFN2DrSPNTw4SSmUg7JGXgGYpRESsiu8O9nX29iyUS85q1/dGjW+lbkRH3mImw6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121462; c=relaxed/simple; bh=yoHj3elEoBQc7qApUDMxTNIZqiijiO+9KRtTLxKfyUw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nieeYvAyu3FQmsEmV1gSW5EqJncLqnSQHKmk2RksK/L3rtO/zZqIj+51ELiHLCzRV+Y8Fnvk/Oqxl2mYhTLOgvXO8om4LaI8iPywoEJfan7qfk6jXaS/ZbvRZoIr22OFCEt+xtoOepgTTPyxNjCy59kJc/YNtKtZuR73exLleZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=kwETLeIb; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="kwETLeIb" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUkOW095566; Wed, 16 Oct 2024 18:30:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729121446; bh=VVT5NjucKejzRiT5jUNXrU8R/6dUkvf+IblHz9+7Bmc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kwETLeIbzrxTavbqp+dk4lTCsIk9zyNR/MzLT/n8mHYT1hbGpZ1y276vew32NvMLo Aftm7if1jM4KQeZ/4K3WvarHaP8VADl1LRYLHH4rPrSDL3T7FxGdef09HF5LETGIUr jPAc3jY9iSi/sPRdEYVNx8qLrolAXxx3sEJ8ikDY= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49GNUkYI011740 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2024 18:30:46 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:46 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7i070988; Wed, 16 Oct 2024 18:30:45 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 1/5] dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl property Date: Wed, 16 Oct 2024 18:30:40 -0500 Message-ID: <20241016233044.240699-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add a pattern property for pcie-ctrl which can be part of this controller. Signed-off-by: Andrew Davis --- .../bindings/soc/ti/ti,j721e-system-controller.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-contr= oller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-contr= oller.yaml index 378e9cc5fac2a..2a64fc61d1262 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.y= aml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.y= aml @@ -68,6 +68,11 @@ patternProperties: description: The node corresponding to SoC chip identification. =20 + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: + This is the PCIe control region. + required: - compatible - reg --=20 2.39.2 From nobody Tue Nov 26 15:22:55 2024 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ACCF1D1747; Wed, 16 Oct 2024 23:31:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121464; cv=none; b=SIO97xYCKaPVIjvVq/cScnOST4h5pgZQNRlOMdsmNBUrWeZSqRyXFGI3uZxn9GSLYAYXL7Ntfx3qmDvUvj0NP2ZOS5rTJj9nnn/Uy7lcNQAS7gCBP+4q/MMtQ9+ld+A4Dnm+lMy/7S9rsj33GEBQA25UfSd6w65EeTDJ67Luzvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121464; c=relaxed/simple; bh=Ihq9yKIeH+aoD6Yk6tRdFeC137TsNgMKdDmhpt2dfUc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fKvQDe3+OJdg0syYayHpHaTiOVg6hwbIQaXlTHLMe57cGH+FKjOygBCv6/NZnFvBzKV5QgMwHr1bSGgl8atHivN9dZ2KwyGG9dvoJcgSCtXD9rP0x1UMWZX3l0zDc2JcC6wxN1R+0yzGDIGtST2MooFbpy8o3kHoHQQEIgsxwvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=o69j6gGs; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="o69j6gGs" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUkAi016130; Wed, 16 Oct 2024 18:30:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729121446; bh=RJdIXxeQZdLKxRUVJuHwy/nEqfURaOs7bbsYKHNkBFU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=o69j6gGsn5BQhDdKgQGWCFQC58P6g1yLegtOnN8Q7Gz8y5ueDDcsYzMRAaeztnYXS pXyehI92st1robpEE3NPTielXWbQf1RnWd1kJEbCoIpUPqLfu1K83vemd0DlGvlTVP cIBvc+CgBSIX76CeSMHs2rk++SttAaYCnl30s+tE= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49GNUkgH086782 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2024 18:30:46 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:46 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7j070988; Wed, 16 Oct 2024 18:30:46 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 2/5] arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region Date: Wed, 16 Oct 2024 18:30:41 -0500 Message-ID: <20241016233044.240699-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe nodes. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++--- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64= /boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso index 4062709d65792..a8a502a6207f6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso @@ -38,7 +38,7 @@ pcie0_ep: pcie-ep@2900000 { reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names =3D "link_state"; interrupts =3D ; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <1>; power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 0da785be80ff4..3b08e71081df3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -44,6 +44,26 @@ scm_conf: scm-conf@100000 { #size-cells =3D <1>; ranges =3D <0x0 0x0 0x00100000 0x1c000>; =20 + pcie0_ctrl: pcie-ctrl@4070 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4070 0x4>; + }; + + pcie1_ctrl: pcie-ctrl@4074 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4074 0x4>; + }; + + pcie2_ctrl: pcie-ctrl@4078 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4078 0x4>; + }; + + pcie3_ctrl: pcie-ctrl@407c { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x407c 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x4080 0x50>; @@ -945,7 +965,7 @@ pcie0_rc: pcie@2900000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -974,7 +994,7 @@ pcie1_rc: pcie@2910000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -1003,7 +1023,7 @@ pcie2_rc: pcie@2920000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4078>; + ti,syscon-pcie-ctrl =3D <&pcie2_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -1032,7 +1052,7 @@ pcie3_rc: pcie@2930000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x407c>; + ti,syscon-pcie-ctrl =3D <&pcie3_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; --=20 2.39.2 From nobody Tue Nov 26 15:22:55 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF8A61B2189; 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Wed, 16 Oct 2024 18:30:47 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:46 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7k070988; Wed, 16 Oct 2024 18:30:46 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region Date: Wed, 16 Oct 2024 18:30:42 -0500 Message-ID: <20241016233044.240699-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 9386bf3ef9f68..45091aa0fb1b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,6 +32,11 @@ scm_conf: scm-conf@100000 { #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x1c000>; =20 + pcie1_ctrl: pcie-ctrl@4074 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4074 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x4080 0x20>; @@ -745,7 +750,7 @@ pcie1_rc: pcie@2910000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <4>; power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; --=20 2.39.2 From nobody Tue Nov 26 15:22:55 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3E011D5ABE; Wed, 16 Oct 2024 23:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121466; cv=none; b=du80Uw/RXs8G6E3Gd9xMHbjzAOhE3bW91Ri0Y1XyTsY3q5DNLPauQdBd8PVZKuDOM4DWqDux9egQJm5UGG/wdHct04n79EpyU3TcMy9iz0A2++XYMa3T0S68DEnnP3h9LPzmsCirETlKnVhmfhf8S0D8vZ51DzaploJqkhfOUR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121466; c=relaxed/simple; bh=nA0RE8tX12e28bYjQkkUvdt6eLsQzyRzH+TpAKmSYZI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lb0S9VuS9Z6L1XlmQgtKyblCbnz1Kco2Q/TZN1RfBD+73QjdU4XFNwIqwJewU1p3wQskFKJdWSzUpJS3ZrXww8AYVVtR6kkB49ZRa0lO5BeU0yBdKwLxewKdXLIAYL5KqML+1BfEkAb9sojRYYsZNgVzyTRL855BtGcVGxWOnJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Ds0gdHEe; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Ds0gdHEe" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUlbM053750; Wed, 16 Oct 2024 18:30:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729121447; bh=v3vQxJMPxC/rFVD7hZcDs0KM4zN+9zW2SXYuhWcXwSs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ds0gdHEes7RPbfS+hiymtycqhcbwquo2jDhnk/DCnHD27thBPI099X5ud9zaPYf3s g9wPmeMkeCX1/PKP2QY81aWek6Uty8YPZnGGm/GdEPdNN8OnFOvEiS/eOcdyp47vZy bI/UfdciArl9O79Qg3h+l44Idp00ScZ9xMuwsZT8= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49GNUlmE011750 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2024 18:30:47 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:47 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:47 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7l070988; Wed, 16 Oct 2024 18:30:46 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 4/5] arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region Date: Wed, 16 Oct 2024 18:30:43 -0500 Message-ID: <20241016233044.240699-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm6= 4/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso index 5ff390915b75b..8c2cd99cf2b42 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -38,7 +38,7 @@ pcie1_ep: pcie-ep@2910000 { reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names =3D "link_state"; interrupts =3D ; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <1>; power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9d..b32b0ce8be462 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -57,6 +57,11 @@ phy_gmii_sel_cpsw: phy@34 { #phy-cells =3D <1>; }; =20 + pcie1_ctrl: pcie-ctrl@74 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x74 0x4>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible =3D "reg-mux"; reg =3D <0x80 0x10>; @@ -1398,7 +1403,7 @@ pcie1_rc: pcie@2910000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <4>; power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; --=20 2.39.2 From nobody Tue Nov 26 15:22:55 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3DA91D5ABD; Wed, 16 Oct 2024 23:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729121466; 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Wed, 16 Oct 2024 18:30:47 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:47 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7m070988; Wed, 16 Oct 2024 18:30:47 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 5/5] arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region Date: Wed, 16 Oct 2024 18:30:44 -0500 Message-ID: <20241016233044.240699-6-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index 7eae18399caa6..66587f20aa0fe 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -51,6 +51,11 @@ chipid@14 { reg =3D <0x00000014 0x4>; }; =20 + pcie0_ctrl: pcie-ctrl@4070 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4070 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x4080 0x4>; @@ -1036,7 +1041,7 @@ pcie0_rc: pcie@f102000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&main_conf 0x4070>; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; max-link-speed =3D <2>; num-lanes =3D <1>; power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; --=20 2.39.2