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Shutemov" , Shuah Khan , devicetree@vger.kernel.org, Anup Patel , linux-kernel@vger.kernel.org, Jonathan Corbet , kvm-riscv@lists.infradead.org, Conor Dooley , kasan-dev@googlegroups.com, linux-doc@vger.kernel.org, Evgenii Stepanov , Charlie Jenkins , Krzysztof Kozlowski , Samuel Holland Subject: [PATCH v5 06/10] riscv: Allow ptrace control of the tagged address ABI Date: Wed, 16 Oct 2024 13:27:47 -0700 Message-ID: <20241016202814.4061541-7-samuel.holland@sifive.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20241016202814.4061541-1-samuel.holland@sifive.com> References: <20241016202814.4061541-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This allows a tracer to control the ABI of the tracee, as on arm64. Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/kernel/ptrace.c | 42 ++++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 43 insertions(+) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 92731ff8c79a..ea67e9fb7a58 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -28,6 +28,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_V REGSET_V, #endif +#ifdef CONFIG_RISCV_ISA_SUPM + REGSET_TAGGED_ADDR_CTRL, +#endif }; =20 static int riscv_gpr_get(struct task_struct *target, @@ -152,6 +155,35 @@ static int riscv_vr_set(struct task_struct *target, } #endif =20 +#ifdef CONFIG_RISCV_ISA_SUPM +static int tagged_addr_ctrl_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + long ctrl =3D get_tagged_addr_ctrl(target); + + if (IS_ERR_VALUE(ctrl)) + return ctrl; + + return membuf_write(&to, &ctrl, sizeof(ctrl)); +} + +static int tagged_addr_ctrl_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + long ctrl; + + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); + if (ret) + return ret; + + return set_tagged_addr_ctrl(target, ctrl); +} +#endif + static const struct user_regset riscv_user_regset[] =3D { [REGSET_X] =3D { .core_note_type =3D NT_PRSTATUS, @@ -182,6 +214,16 @@ static const struct user_regset riscv_user_regset[] = =3D { .set =3D riscv_vr_set, }, #endif +#ifdef CONFIG_RISCV_ISA_SUPM + [REGSET_TAGGED_ADDR_CTRL] =3D { + .core_note_type =3D NT_RISCV_TAGGED_ADDR_CTRL, + .n =3D 1, + .size =3D sizeof(long), + .align =3D sizeof(long), + .regset_get =3D tagged_addr_ctrl_get, + .set =3D tagged_addr_ctrl_set, + }, +#endif }; =20 static const struct user_regset_view riscv_user_native_view =3D { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b9935988da5c..a920cf8934dc 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -450,6 +450,7 @@ typedef struct elf64_shdr { #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ +#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (= prctl()) */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension regist= ers */ --=20 2.45.1