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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003AE8.mail.protection.outlook.com (10.167.248.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8069.17 via Frontend Transport; Wed, 16 Oct 2024 05:18:43 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 16 Oct 2024 00:18:38 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v6 7/9] iommu/amd: Move erratum 63 logic to write_dte_lower128() Date: Wed, 16 Oct 2024 05:17:54 +0000 Message-ID: <20241016051756.4317-8-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> References: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE8:EE_|MW4PR12MB6875:EE_ X-MS-Office365-Filtering-Correlation-Id: 86d5a05b-f055-4f85-4848-08dceda200b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:43.1457 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86d5a05b-f055-4f85-4848-08dceda200b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6875 Content-Type: text/plain; charset="utf-8" To simplify DTE programming, and remove amd_iommu_apply_erratum_63() and helper functions since no longer used. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 - drivers/iommu/amd/amd_iommu_types.h | 2 ++ drivers/iommu/amd/init.c | 36 ----------------------------- drivers/iommu/amd/iommu.c | 6 +++-- 4 files changed, 6 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 96c3bfc234f8..1467bfc34fdf 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -16,7 +16,6 @@ irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *da= ta); irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data); irqreturn_t amd_iommu_int_thread_galog(int irq, void *data); irqreturn_t amd_iommu_int_handler(int irq, void *data); -void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, u8 cntrl_intr, u8 cntrl_log, u32 status_run_mask, u32 status_overflow_mask); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 3f53d3bc79cb..53e129835b26 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -220,6 +220,8 @@ #define DEV_ENTRY_EX 0x67 #define DEV_ENTRY_SYSMGT1 0x68 #define DEV_ENTRY_SYSMGT2 0x69 +#define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40) + #define DEV_ENTRY_IRQ_TBL_EN 0x80 #define DEV_ENTRY_INIT_PASS 0xb8 #define DEV_ENTRY_EINT_PASS 0xb9 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 552a13f7668c..31f10a071abd 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1014,29 +1014,6 @@ static void __set_dev_entry_bit(struct dev_table_ent= ry *dev_table, dev_table[devid].data[i] |=3D (1UL << _bit); } =20 -static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) -{ - struct dev_table_entry *dev_table =3D get_dev_table(iommu); - - return __set_dev_entry_bit(dev_table, devid, bit); -} - -static int __get_dev_entry_bit(struct dev_table_entry *dev_table, - u16 devid, u8 bit) -{ - int i =3D (bit >> 6) & 0x03; - int _bit =3D bit & 0x3f; - - return (dev_table[devid].data[i] & (1UL << _bit)) >> _bit; -} - -static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) -{ - struct dev_table_entry *dev_table =3D get_dev_table(iommu); - - return __get_dev_entry_bit(dev_table, devid, bit); -} - static bool __copy_device_table(struct amd_iommu *iommu) { u64 int_ctl, int_tab_len, entry =3D 0; @@ -1152,17 +1129,6 @@ static bool copy_device_table(void) return true; } =20 -void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid) -{ - int sysmgt; - - sysmgt =3D get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) | - (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1); - - if (sysmgt =3D=3D 0x01) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW); -} - /* * This function takes the device specific flags read from the ACPI * table and sets up the device table entry with that information @@ -1185,8 +1151,6 @@ static void __init set_dev_entry_from_acpi(struct amd= _iommu *iommu, if (flags & ACPI_DEVFLAG_LINT1) set_dte_cache_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); =20 - amd_iommu_apply_erratum_63(iommu, devid); - amd_iommu_set_rlookup_table(iommu, devid); } =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index c03e2d9d2990..a8c0a57003a8 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -105,6 +105,10 @@ static void write_dte_lower128(struct dev_table_entry = *ptr, struct dev_table_ent =20 old.data128[0] =3D READ_ONCE(ptr->data128[0]); do { + /* Apply erratum 63 */ + if (FIELD_GET(DTE_DATA1_SYSMGT_MASK, new->data[1]) =3D=3D 0x1) + new->data[0] |=3D DTE_FLAG_IW; + /* Note: try_cmpxchg inherently update &old.data128[0] on failure */ } while (!try_cmpxchg128(&ptr->data128[0], &old.data128[0], new->data128[= 0])); } @@ -2117,8 +2121,6 @@ static void clear_dte_entry(struct amd_iommu *iommu, = u16 devid) dev_table[devid].data[0] |=3D DTE_FLAG_TV; =20 dev_table[devid].data[1] &=3D DTE_FLAG_MASK; - - amd_iommu_apply_erratum_63(iommu, devid); } =20 /* Update and flush DTE for the given device */ --=20 2.34.1