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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:18.9095 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e13ef077-0d9b-4739-1fb5-08dceda1f247 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8958 Content-Type: text/plain; charset="utf-8" According to the AMD IOMMU spec, IOMMU hardware reads the entire DTE in a single 256-bit transaction. It is recommended to update DTE using 128-bit operation followed by an INVALIDATE_DEVTAB_ENTYRY command when the IV=3D1b or V=3D1b before the change. According to the AMD BIOS and Kernel Developer's Guide (BDKG) dated back to family 10h Processor [1], which is the first introduction of AMD IOMMU, AMD processor always has CPUID Fn0000_0001_ECX[CMPXCHG16B]=3D1. Therefore, it is safe to assume cmpxchg128 is available with all AMD processor w/ IOMMU. In addition, the CMPXCHG16B feature has already been checked separately before enabling the GA, XT, and GAM modes. Consolidate the detection logic, and fail the IOMMU initialization if the feature is not supported. [1] https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/pro= grammer-references/31116.pdf Reviewed-by: Jason Gunthorpe Suggested-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 43131c3a2172..a1a0bd398c14 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1764,13 +1764,8 @@ static int __init init_iommu_one(struct amd_iommu *i= ommu, struct ivhd_header *h, else iommu->mmio_phys_end =3D MMIO_CNTR_CONF_OFFSET; =20 - /* - * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. - * GAM also requires GA mode. Therefore, we need to - * check cmpxchg16b support before enabling it. - */ - if (!boot_cpu_has(X86_FEATURE_CX16) || - ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) =3D=3D 0)) + /* GAM requires GA mode. */ + if ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) =3D=3D 0) amd_iommu_guest_ir =3D AMD_IOMMU_GUEST_IR_LEGACY; break; case 0x11: @@ -1780,13 +1775,8 @@ static int __init init_iommu_one(struct amd_iommu *i= ommu, struct ivhd_header *h, else iommu->mmio_phys_end =3D MMIO_CNTR_CONF_OFFSET; =20 - /* - * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. - * XT, GAM also requires GA mode. Therefore, we need to - * check cmpxchg16b support before enabling them. - */ - if (!boot_cpu_has(X86_FEATURE_CX16) || - ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) =3D=3D 0)) { + /* XT and GAM require GA mode. */ + if ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) =3D=3D 0) { amd_iommu_guest_ir =3D AMD_IOMMU_GUEST_IR_LEGACY; break; } @@ -3051,6 +3041,11 @@ static int __init early_amd_iommu_init(void) return -EINVAL; } =20 + if (!boot_cpu_has(X86_FEATURE_CX16)) { + pr_err("Failed to initialize. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:23.2434 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b45b28e8-34bd-4c1f-6bcd-08dceda1f4dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5757 Content-Type: text/plain; charset="utf-8" From: Uros Bizjak Currently, [READ|WRITE]_ONCE() do not support variable of type __int128. Re-define "__dword_type" from type "long long" to __int128 if supported. Signed-off-by: Uros Bizjak Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jason Gunthorpe --- include/asm-generic/rwonce.h | 2 +- include/linux/compiler_types.h | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h index 8d0a6280e982..8bf942ad5ef3 100644 --- a/include/asm-generic/rwonce.h +++ b/include/asm-generic/rwonce.h @@ -33,7 +33,7 @@ * (e.g. a virtual address) and a strong prevailing wind. */ #define compiletime_assert_rwonce_type(t) \ - compiletime_assert(__native_word(t) || sizeof(t) =3D=3D sizeof(long long)= , \ + compiletime_assert(__native_word(t) || sizeof(t) =3D=3D sizeof(__dword_ty= pe), \ "Unsupported access size for {READ,WRITE}_ONCE().") =20 /* diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h index 1a957ea2f4fe..54b56ae25db7 100644 --- a/include/linux/compiler_types.h +++ b/include/linux/compiler_types.h @@ -469,6 +469,12 @@ struct ftrace_likely_data { unsigned type: (unsigned type)0, \ signed type: (signed type)0 =20 +#ifdef __SIZEOF_INT128__ +#define __dword_type __int128 +#else +#define __dword_type long long +#endif + #define __unqual_scalar_typeof(x) typeof( \ _Generic((x), \ char: (char)0, \ @@ -476,7 +482,7 @@ struct ftrace_likely_data { __scalar_type_to_expr_cases(short), \ __scalar_type_to_expr_cases(int), \ __scalar_type_to_expr_cases(long), \ - __scalar_type_to_expr_cases(long long), \ + __scalar_type_to_expr_cases(__dword_type), \ default: (x))) =20 /* Is this type a native word size -- useful for atomic operations */ --=20 2.34.1 From nobody Tue Mar 11 05:08:41 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2043.outbound.protection.outlook.com [40.107.243.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E79F18BBB7 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:27.2533 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6932237c-5e26-4b75-4a12-08dceda1f740 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7412 Content-Type: text/plain; charset="utf-8" The current implementation does not follow 128-bit write requirement to update DTE as specified in the AMD I/O Virtualization Techonology (IOMMU) Specification. Therefore, modify the struct dev_table_entry to contain union of u128 data array, and introduce a helper functions update_dte256() to update DTE using two 128-bit cmpxchg operations to update 256-bit DTE with the modified structure, and take into account the DTE[V, GV] bits when programming the DTE to ensure proper order of DTE programming and flushing. In addition, introduce a per-DTE spin_lock struct dev_data.dte_lock to provide synchronization when updating the DTE to prevent cmpxchg128 failure. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 10 ++- drivers/iommu/amd/iommu.c | 112 ++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 601fb4ee6900..f537b264f118 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -425,9 +425,13 @@ #define DTE_GCR3_SHIFT_C 43 =20 #define DTE_GPT_LEVEL_SHIFT 54 +#define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54) =20 #define GCR3_VALID 0x01ULL =20 +/* DTE[128:179] | DTE[184:191] */ +#define DTE_DATA2_INTR_MASK ~GENMASK_ULL(55, 52) + #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR) #define IOMMU_PTE_DIRTY(pte) ((pte) & IOMMU_PTE_HD) @@ -832,6 +836,7 @@ struct devid_map { struct iommu_dev_data { /*Protect against attach/detach races */ spinlock_t lock; + spinlock_t dte_lock; /* DTE lock for 256-bit access */ =20 struct list_head list; /* For domain->dev_list */ struct llist_node dev_data_list; /* For global dev_data_list */ @@ -882,7 +887,10 @@ extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; * Structure defining one entry in the device table */ struct dev_table_entry { - u64 data[4]; + union { + u64 data[4]; + u128 data128[2]; + }; }; =20 /* diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 8364cd6fa47d..ab0d3f46871e 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -77,12 +77,114 @@ static void detach_device(struct device *dev); static void set_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data *dev_data); =20 +static void iommu_flush_dte_sync(struct amd_iommu *iommu, u16 devid); + /*************************************************************************= *** * * Helper functions * *************************************************************************= ***/ =20 +static void write_dte_upper128(struct dev_table_entry *ptr, struct dev_tab= le_entry *new) +{ + struct dev_table_entry old =3D {}; + + old.data128[1] =3D READ_ONCE(ptr->data128[1]); + do { + /* Need to preserve DTE_DATA2_INTR_MASK */ + new->data[2] &=3D ~DTE_DATA2_INTR_MASK; + new->data[2] |=3D old.data[2] & DTE_DATA2_INTR_MASK; + + /* Note: try_cmpxchg inherently update &old.data128[1] on failure */ + } while (!try_cmpxchg128(&ptr->data128[1], &old.data128[1], new->data128[= 1])); +} + +static void write_dte_lower128(struct dev_table_entry *ptr, struct dev_tab= le_entry *new) +{ + struct dev_table_entry old =3D {}; + + old.data128[0] =3D READ_ONCE(ptr->data128[0]); + do { + /* Note: try_cmpxchg inherently update &old.data128[0] on failure */ + } while (!try_cmpxchg128(&ptr->data128[0], &old.data128[0], new->data128[= 0])); +} + +/* + * Note: + * IOMMU reads the entire Device Table entry in a single 256-bit transacti= on + * but the driver is programming DTE using 2 128-bit cmpxchg. So, the driv= er + * need to ensure the following: + * - DTE[V|GV] bit is being written last when setting. + * - DTE[V|GV] bit is being written first when clearing. + * + * This function is used only by code, which updates DMA translation part = of the DTE. + * So, only consider control bits related to DMA when updating the entry. + */ +static void update_dte256(struct amd_iommu *iommu, struct iommu_dev_data *= dev_data, + struct dev_table_entry *new) +{ + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + struct dev_table_entry *ptr =3D &dev_table[dev_data->devid]; + + spin_lock(&dev_data->dte_lock); + + if (!(ptr->data[0] & DTE_FLAG_V)) { + /* Existing DTE is not valid. */ + write_dte_upper128(ptr, new); + write_dte_lower128(ptr, new); + iommu_flush_dte_sync(iommu, dev_data->devid); + } else if (!(new->data[0] & DTE_FLAG_V)) { + /* Existing DTE is valid. New DTE is not valid. */ + write_dte_lower128(ptr, new); + write_dte_upper128(ptr, new); + iommu_flush_dte_sync(iommu, dev_data->devid); + } else if (!FIELD_GET(DTE_FLAG_GV, ptr->data[0])) { + /* + * Both DTEs are valid. + * Existing DTE has no guest page table. + */ + write_dte_upper128(ptr, new); + write_dte_lower128(ptr, new); + iommu_flush_dte_sync(iommu, dev_data->devid); + } else if (!FIELD_GET(DTE_FLAG_GV, new->data[0])) { + /* + * Both DTEs are valid. + * Existing DTE has guest page table, + * new DTE has no guest page table, + */ + write_dte_lower128(ptr, new); + write_dte_upper128(ptr, new); + iommu_flush_dte_sync(iommu, dev_data->devid); + } else if (FIELD_GET(DTE_GPT_LEVEL_MASK, ptr->data[2]) !=3D + FIELD_GET(DTE_GPT_LEVEL_MASK, new->data[2])) { + /* + * Both DTEs are valid and have guest page table, + * but have different number of levels. So, we need + * to upadte both upper and lower 128-bit value, which + * require disabling and flushing. + */ + struct dev_table_entry clear =3D {}; + + /* First disable DTE */ + write_dte_lower128(ptr, &clear); + iommu_flush_dte_sync(iommu, dev_data->devid); + + /* Then update DTE */ + write_dte_upper128(ptr, new); + write_dte_lower128(ptr, new); + iommu_flush_dte_sync(iommu, dev_data->devid); + } else { + /* + * Both DTEs are valid and have guest page table, + * and same number of levels. We just need to only + * update the lower 128-bit. So no need to disable DTE. + */ + write_dte_lower128(ptr, new); + } + + spin_unlock(&dev_data->dte_lock); +} + static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom) { return (pdom && (pdom->pd_mode =3D=3D PD_MODE_V2)); @@ -203,6 +305,7 @@ static struct iommu_dev_data *alloc_dev_data(struct amd= _iommu *iommu, u16 devid) return NULL; =20 spin_lock_init(&dev_data->lock); + spin_lock_init(&dev_data->dte_lock); dev_data->devid =3D devid; ratelimit_default_init(&dev_data->rs); =20 @@ -1272,6 +1375,15 @@ static int iommu_flush_dte(struct amd_iommu *iommu, = u16 devid) return iommu_queue_command(iommu, &cmd); } =20 +static void iommu_flush_dte_sync(struct amd_iommu *iommu, u16 devid) +{ + int ret; + + ret =3D iommu_flush_dte(iommu, devid); + if (!ret) + iommu_completion_wait(iommu); +} + static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) { u32 devid; --=20 2.34.1 From nobody Tue Mar 11 05:08:41 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2086.outbound.protection.outlook.com [40.107.244.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6044D18BBB8 for ; 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Wed, 16 Oct 2024 00:18:26 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v6 4/9] iommu/amd: Introduce per-device DTE cache to store persistent bits Date: Wed, 16 Oct 2024 05:17:51 +0000 Message-ID: <20241016051756.4317-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> References: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AEA:EE_|SA1PR12MB6995:EE_ X-MS-Office365-Filtering-Correlation-Id: eca275b5-5bbd-4d23-81c9-08dceda1fb03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:33.5658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eca275b5-5bbd-4d23-81c9-08dceda1fb03 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6995 Content-Type: text/plain; charset="utf-8" Currently, IOMMU driver initializes each Device Table Entry (DTE) starting from when it parses the ACPI IVRS table during one-time initialization, and the value is directly programmed into the table. The value is stored in the table until next system reset. This makes the DTE programming difficult since it needs to ensure that all persistent DTE bits are not overwritten during runtime. Introduce per-device DTE cache to store persistent DTE bits. Please note also that the amd_iommu_apply_erratum_63() is not updated since it will be removed in subsequent patch. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/amd_iommu_types.h | 21 +++++++++++---------- drivers/iommu/amd/init.c | 26 +++++++++++++++++++------- drivers/iommu/amd/iommu.c | 2 +- 4 files changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 6386fa4556d9..96c3bfc234f8 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -177,3 +177,5 @@ void amd_iommu_domain_set_pgtable(struct protection_dom= ain *domain, struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); =20 #endif + +struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index f537b264f118..3f53d3bc79cb 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -830,6 +830,16 @@ struct devid_map { /* Device may request super-user privileges */ #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 =20 +/* + * Structure defining one entry in the device table + */ +struct dev_table_entry { + union { + u64 data[4]; + u128 data128[2]; + }; +}; + /* * This struct contains device specific data for the IOMMU */ @@ -858,6 +868,7 @@ struct iommu_dev_data { bool defer_attach; =20 struct ratelimit_state rs; /* Ratelimit IOPF messages */ + struct dev_table_entry dte_cache; }; =20 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ @@ -883,16 +894,6 @@ extern struct list_head amd_iommu_list; */ extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; =20 -/* - * Structure defining one entry in the device table - */ -struct dev_table_entry { - union { - u64 data[4]; - u128 data128[2]; - }; -}; - /* * One entry for unity mappings parsed out of the ACPI table. */ diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index a1a0bd398c14..552a13f7668c 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -992,6 +992,18 @@ static void iommu_enable_gt(struct amd_iommu *iommu) iommu_feature_enable(iommu, CONTROL_GT_EN); } =20 +static void set_dte_cache_bit(struct amd_iommu *iommu, u16 devid, u8 bit) +{ + int i =3D (bit >> 6) & 0x03; + int _bit =3D bit & 0x3f; + struct iommu_dev_data *dev_data =3D find_dev_data(iommu, devid); + + if (!dev_data) + return; + + dev_data->dte_cache.data[i] |=3D (1UL << _bit); +} + /* sets a specific bit in the device table entry. */ static void __set_dev_entry_bit(struct dev_table_entry *dev_table, u16 devid, u8 bit) @@ -1159,19 +1171,19 @@ static void __init set_dev_entry_from_acpi(struct a= md_iommu *iommu, u16 devid, u32 flags, u32 ext_flags) { if (flags & ACPI_DEVFLAG_INITPASS) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS); + set_dte_cache_bit(iommu, devid, DEV_ENTRY_INIT_PASS); if (flags & ACPI_DEVFLAG_EXTINT) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS); + set_dte_cache_bit(iommu, devid, DEV_ENTRY_EINT_PASS); if (flags & ACPI_DEVFLAG_NMI) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); + set_dte_cache_bit(iommu, devid, DEV_ENTRY_NMI_PASS); if (flags & ACPI_DEVFLAG_SYSMGT1) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1); + set_dte_cache_bit(iommu, devid, DEV_ENTRY_SYSMGT1); if (flags & ACPI_DEVFLAG_SYSMGT2) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2); + set_dte_cache_bit(iommu, devid, DEV_ENTRY_SYSMGT2); if (flags & ACPI_DEVFLAG_LINT0) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS); + set_dte_cache_bit(iommu, devid, DEV_ENTRY_LINT0_PASS); if (flags & ACPI_DEVFLAG_LINT1) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); + set_dte_cache_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); =20 amd_iommu_apply_erratum_63(iommu, devid); =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index ab0d3f46871e..28516d89168a 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -393,7 +393,7 @@ static void setup_aliases(struct amd_iommu *iommu, stru= ct device *dev) clone_aliases(iommu, dev); } =20 -static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 d= evid) +struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid) { struct iommu_dev_data *dev_data; =20 --=20 2.34.1 From nobody Tue Mar 11 05:08:41 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2083.outbound.protection.outlook.com [40.107.92.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B28118BC10 for ; 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Wed, 16 Oct 2024 00:18:30 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v6 5/9] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers Date: Wed, 16 Oct 2024 05:17:52 +0000 Message-ID: <20241016051756.4317-6-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> References: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE4:EE_|BY5PR12MB4275:EE_ X-MS-Office365-Filtering-Correlation-Id: 55791d10-2374-4c20-7780-08dceda1fc05 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:35.2564 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55791d10-2374-4c20-7780-08dceda1fc05 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4275 Content-Type: text/plain; charset="utf-8" Also, the set_dte_entry() is used to program several DTE fields (e.g. stage1 table, stage2 table, domain id, and etc.), which is difficult to keep track with current implementation. Therefore, separate logic for clearing DTE (i.e. make_clear_dte) and another function for setting up the GCR3 Table Root Pointer, GIOV, GV, GLX, and GuestPagingMode into another function set_dte_gcr3_table(). Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 126 ++++++++++++++++++++++---------------- 1 file changed, 73 insertions(+), 53 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 28516d89168a..1e61201baf92 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1954,90 +1954,110 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *de= v_data, ioasid_t pasid) return ret; } =20 +static void make_clear_dte(struct iommu_dev_data *dev_data, struct dev_tab= le_entry *ptr, + struct dev_table_entry *new) +{ + /* All existing DTE must have V bit set */ + new->data128[0] =3D DTE_FLAG_V; + new->data128[1] =3D 0; +} + +/* + * Note: + * The old value for GCR3 table and GPT have been cleared from caller. + */ +static void set_dte_gcr3_table(struct amd_iommu *iommu, + struct iommu_dev_data *dev_data, + struct dev_table_entry *target) +{ + struct gcr3_tbl_info *gcr3_info =3D &dev_data->gcr3_info; + u64 tmp, gcr3; + + if (!gcr3_info->gcr3_tbl) + return; + + pr_debug("%s: devid=3D%#x, glx=3D%#x, gcr3_tbl=3D%#llx\n", + __func__, dev_data->devid, gcr3_info->glx, + (unsigned long long)gcr3_info->gcr3_tbl); + + tmp =3D gcr3_info->glx; + target->data[0] |=3D (tmp & DTE_GLX_MASK) << DTE_GLX_SHIFT; + if (pdom_is_v2_pgtbl_mode(dev_data->domain)) + target->data[0] |=3D DTE_FLAG_GIOV; + target->data[0] |=3D DTE_FLAG_GV; + + + gcr3 =3D iommu_virt_to_phys(gcr3_info->gcr3_tbl); + + /* Encode GCR3 table into DTE */ + tmp =3D DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; + target->data[0] |=3D tmp; + tmp =3D DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; + tmp |=3D DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; + target->data[1] |=3D tmp; + + /* Guest page table can only support 4 and 5 levels */ + if (amd_iommu_gpt_level =3D=3D PAGE_MODE_5_LEVEL) + target->data[2] |=3D ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); +} + static void set_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data *dev_data) { - u64 pte_root =3D 0; - u64 flags =3D 0; - u32 old_domid; - u16 devid =3D dev_data->devid; u16 domid; + u32 old_domid; + struct dev_table_entry new =3D {}; struct protection_domain *domain =3D dev_data->domain; - struct dev_table_entry *dev_table =3D get_dev_table(iommu); struct gcr3_tbl_info *gcr3_info =3D &dev_data->gcr3_info; + struct dev_table_entry *dte =3D &get_dev_table(iommu)[dev_data->devid]; =20 if (gcr3_info && gcr3_info->gcr3_tbl) domid =3D dev_data->gcr3_info.domid; else domid =3D domain->id; =20 + make_clear_dte(dev_data, dte, &new); + if (domain->iop.mode !=3D PAGE_MODE_NONE) - pte_root =3D iommu_virt_to_phys(domain->iop.root); + new.data[0] =3D iommu_virt_to_phys(domain->iop.root); =20 - pte_root |=3D (domain->iop.mode & DEV_ENTRY_MODE_MASK) + new.data[0] |=3D (domain->iop.mode & DEV_ENTRY_MODE_MASK) << DEV_ENTRY_MODE_SHIFT; =20 - pte_root |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V; + new.data[0] |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V; =20 /* * When SNP is enabled, Only set TV bit when IOMMU * page translation is in use. */ if (!amd_iommu_snp_en || (domid !=3D 0)) - pte_root |=3D DTE_FLAG_TV; - - flags =3D dev_table[devid].data[1]; - - if (dev_data->ats_enabled) - flags |=3D DTE_FLAG_IOTLB; + new.data[0] |=3D DTE_FLAG_TV; =20 if (dev_data->ppr) - pte_root |=3D 1ULL << DEV_ENTRY_PPR; + new.data[0] |=3D 1ULL << DEV_ENTRY_PPR; =20 if (domain->dirty_tracking) - pte_root |=3D DTE_FLAG_HAD; - - if (gcr3_info && gcr3_info->gcr3_tbl) { - u64 gcr3 =3D iommu_virt_to_phys(gcr3_info->gcr3_tbl); - u64 glx =3D gcr3_info->glx; - u64 tmp; - - pte_root |=3D DTE_FLAG_GV; - pte_root |=3D (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; - - /* First mask out possible old values for GCR3 table */ - tmp =3D DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; - flags &=3D ~tmp; + new.data[0] |=3D DTE_FLAG_HAD; =20 - tmp =3D DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; - flags &=3D ~tmp; - - /* Encode GCR3 table into DTE */ - tmp =3D DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; - pte_root |=3D tmp; - - tmp =3D DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; - flags |=3D tmp; + if (dev_data->ats_enabled) + new.data[1] |=3D DTE_FLAG_IOTLB; + else + new.data[1] &=3D ~DTE_FLAG_IOTLB; =20 - tmp =3D DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; - flags |=3D tmp; + old_domid =3D READ_ONCE(dte->data[1]) & DEV_DOMID_MASK; + new.data[1] &=3D ~DEV_DOMID_MASK; + new.data[1] |=3D domid; =20 - if (amd_iommu_gpt_level =3D=3D PAGE_MODE_5_LEVEL) { - dev_table[devid].data[2] |=3D - ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); - } - - /* GIOV is supported with V2 page table mode only */ - if (pdom_is_v2_pgtbl_mode(domain)) - pte_root |=3D DTE_FLAG_GIOV; - } + /* + * Restore cached persistent DTE bits, which can be set by information + * in IVRS table. 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Wed, 16 Oct 2024 05:18:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003AE9.mail.protection.outlook.com (10.167.248.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8069.17 via Frontend Transport; Wed, 16 Oct 2024 05:18:39 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 16 Oct 2024 00:18:34 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v6 6/9] iommu/amd: Introduce helper function get_dte256() Date: Wed, 16 Oct 2024 05:17:53 +0000 Message-ID: <20241016051756.4317-7-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> References: <20241016051756.4317-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE9:EE_|MW6PR12MB8734:EE_ X-MS-Office365-Filtering-Correlation-Id: 279d2c3b-6f9c-417f-395b-08dceda1fe68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:39.2591 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 279d2c3b-6f9c-417f-395b-08dceda1fe68 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8734 Content-Type: text/plain; charset="utf-8" And use it in clone_alias() along with update_dte256(). Also use get_dte256() in dump_dte_entry(). Reviewed-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 59 +++++++++++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 1e61201baf92..c03e2d9d2990 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -185,6 +185,20 @@ static void update_dte256(struct amd_iommu *iommu, str= uct iommu_dev_data *dev_da spin_unlock(&dev_data->dte_lock); } =20 +static void get_dte256(struct amd_iommu *iommu, struct iommu_dev_data *dev= _data, + struct dev_table_entry *dte) +{ + struct dev_table_entry *ptr; + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + + ptr =3D &dev_table[dev_data->devid]; + + spin_lock(&dev_data->dte_lock); + dte->data128[0] =3D READ_ONCE(ptr->data128[0]); + dte->data128[1] =3D READ_ONCE(ptr->data128[1]); + spin_unlock(&dev_data->dte_lock); +} + static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom) { return (pdom && (pdom->pd_mode =3D=3D PD_MODE_V2)); @@ -333,9 +347,11 @@ static struct iommu_dev_data *search_dev_data(struct a= md_iommu *iommu, u16 devid =20 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data) { + struct dev_table_entry new; struct amd_iommu *iommu; - struct dev_table_entry *dev_table; + struct iommu_dev_data *dev_data, *alias_data; u16 devid =3D pci_dev_id(pdev); + int ret =3D 0; =20 if (devid =3D=3D alias) return 0; @@ -344,13 +360,27 @@ static int clone_alias(struct pci_dev *pdev, u16 alia= s, void *data) if (!iommu) return 0; =20 - amd_iommu_set_rlookup_table(iommu, alias); - dev_table =3D get_dev_table(iommu); - memcpy(dev_table[alias].data, - dev_table[devid].data, - sizeof(dev_table[alias].data)); + /* Copy the data from pdev */ + dev_data =3D dev_iommu_priv_get(&pdev->dev); + if (!dev_data) { + pr_err("%s : Failed to get dev_data for 0x%x\n", __func__, devid); + ret =3D -EINVAL; + goto out; + } + get_dte256(iommu, dev_data, &new); =20 - return 0; + /* Setup alias */ + alias_data =3D find_dev_data(iommu, alias); + if (!alias_data) { + pr_err("%s : Failed to get alias dev_data for 0x%x\n", __func__, alias); + ret =3D -EINVAL; + goto out; + } + update_dte256(iommu, alias_data, &new); + + amd_iommu_set_rlookup_table(iommu, alias); +out: + return ret; } =20 static void clone_aliases(struct amd_iommu *iommu, struct device *dev) @@ -623,6 +653,12 @@ static int iommu_init_device(struct amd_iommu *iommu, = struct device *dev) return -ENOMEM; =20 dev_data->dev =3D dev; + + /* + * The dev_iommu_priv_set() needes to be called before setup_aliases. + * Otherwise, subsequent call to dev_iommu_priv_get() will fail. + */ + dev_iommu_priv_set(dev, dev_data); setup_aliases(iommu, dev); =20 /* @@ -636,8 +672,6 @@ static int iommu_init_device(struct amd_iommu *iommu, s= truct device *dev) dev_data->flags =3D pdev_get_caps(to_pci_dev(dev)); } =20 - dev_iommu_priv_set(dev, dev_data); - return 0; } =20 @@ -684,10 +718,13 @@ static void amd_iommu_uninit_device(struct device *de= v) static void dump_dte_entry(struct amd_iommu *iommu, u16 devid) { int i; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:43.1457 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86d5a05b-f055-4f85-4848-08dceda200b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6875 Content-Type: text/plain; charset="utf-8" To simplify DTE programming, and remove amd_iommu_apply_erratum_63() and helper functions since no longer used. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 - drivers/iommu/amd/amd_iommu_types.h | 2 ++ drivers/iommu/amd/init.c | 36 ----------------------------- drivers/iommu/amd/iommu.c | 6 +++-- 4 files changed, 6 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 96c3bfc234f8..1467bfc34fdf 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -16,7 +16,6 @@ irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *da= ta); irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data); irqreturn_t amd_iommu_int_thread_galog(int irq, void *data); irqreturn_t amd_iommu_int_handler(int irq, void *data); -void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, u8 cntrl_intr, u8 cntrl_log, u32 status_run_mask, u32 status_overflow_mask); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 3f53d3bc79cb..53e129835b26 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -220,6 +220,8 @@ #define DEV_ENTRY_EX 0x67 #define DEV_ENTRY_SYSMGT1 0x68 #define DEV_ENTRY_SYSMGT2 0x69 +#define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40) + #define DEV_ENTRY_IRQ_TBL_EN 0x80 #define DEV_ENTRY_INIT_PASS 0xb8 #define DEV_ENTRY_EINT_PASS 0xb9 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 552a13f7668c..31f10a071abd 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1014,29 +1014,6 @@ static void __set_dev_entry_bit(struct dev_table_ent= ry *dev_table, dev_table[devid].data[i] |=3D (1UL << _bit); } =20 -static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) -{ - struct dev_table_entry *dev_table =3D get_dev_table(iommu); - - return __set_dev_entry_bit(dev_table, devid, bit); -} - -static int __get_dev_entry_bit(struct dev_table_entry *dev_table, - u16 devid, u8 bit) -{ - int i =3D (bit >> 6) & 0x03; - int _bit =3D bit & 0x3f; - - return (dev_table[devid].data[i] & (1UL << _bit)) >> _bit; -} - -static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) -{ - struct dev_table_entry *dev_table =3D get_dev_table(iommu); - - return __get_dev_entry_bit(dev_table, devid, bit); -} - static bool __copy_device_table(struct amd_iommu *iommu) { u64 int_ctl, int_tab_len, entry =3D 0; @@ -1152,17 +1129,6 @@ static bool copy_device_table(void) return true; } =20 -void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid) -{ - int sysmgt; - - sysmgt =3D get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) | - (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1); - - if (sysmgt =3D=3D 0x01) - set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW); -} - /* * This function takes the device specific flags read from the ACPI * table and sets up the device table entry with that information @@ -1185,8 +1151,6 @@ static void __init set_dev_entry_from_acpi(struct amd= _iommu *iommu, if (flags & ACPI_DEVFLAG_LINT1) set_dte_cache_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); =20 - amd_iommu_apply_erratum_63(iommu, devid); - amd_iommu_set_rlookup_table(iommu, devid); } =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index c03e2d9d2990..a8c0a57003a8 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -105,6 +105,10 @@ static void write_dte_lower128(struct dev_table_entry = *ptr, struct dev_table_ent =20 old.data128[0] =3D READ_ONCE(ptr->data128[0]); do { + /* Apply erratum 63 */ + if (FIELD_GET(DTE_DATA1_SYSMGT_MASK, new->data[1]) =3D=3D 0x1) + new->data[0] |=3D DTE_FLAG_IW; + /* Note: try_cmpxchg inherently update &old.data128[0] on failure */ } while (!try_cmpxchg128(&ptr->data128[0], &old.data128[0], new->data128[= 0])); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:47.2122 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f51f484a-94a9-4b74-2a0b-08dceda20328 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7270 Content-Type: text/plain; charset="utf-8" By reusing the make_clear_dte() and update_dte256(). Also, there is no need to set TV bit for non-SNP system when clearing DTE for blocked domain. Reviewed-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a8c0a57003a8..9ef6ddae3b66 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2110,17 +2110,13 @@ static void set_dte_entry(struct amd_iommu *iommu, } } =20 -static void clear_dte_entry(struct amd_iommu *iommu, u16 devid) +static void clear_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data= *dev_data) { - struct dev_table_entry *dev_table =3D get_dev_table(iommu); - - /* remove entry from the device table seen by the hardware */ - dev_table[devid].data[0] =3D DTE_FLAG_V; - - if (!amd_iommu_snp_en) - dev_table[devid].data[0] |=3D DTE_FLAG_TV; + struct dev_table_entry new =3D {}; + struct dev_table_entry *dte =3D &get_dev_table(iommu)[dev_data->devid]; =20 - dev_table[devid].data[1] &=3D DTE_FLAG_MASK; + make_clear_dte(dev_data, dte, &new); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 05:18:51.1198 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f547ddb4-2577-47b4-080b-08dceda2057a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9188 Content-Type: text/plain; charset="utf-8" When updating only within a 64-bit tuple of a DTE, just lock the DTE and use WRITE_ONCE() because it is writing to memory read back by HW. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 43 +++++++++++++++++++---------------- 2 files changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 1467bfc34fdf..23b9e92cc33b 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -178,3 +178,4 @@ struct dev_table_entry *get_dev_table(struct amd_iommu = *iommu); #endif =20 struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid); +struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 9ef6ddae3b66..caea101df7b9 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -331,7 +331,7 @@ static struct iommu_dev_data *alloc_dev_data(struct amd= _iommu *iommu, u16 devid) return dev_data; } =20 -static struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16= devid) +struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid) { struct iommu_dev_data *dev_data; struct llist_node *node; @@ -2787,12 +2787,12 @@ static int amd_iommu_set_dirty_tracking(struct iomm= u_domain *domain, bool enable) { struct protection_domain *pdomain =3D to_pdomain(domain); - struct dev_table_entry *dev_table; + struct dev_table_entry *dte; struct iommu_dev_data *dev_data; bool domain_flush =3D false; struct amd_iommu *iommu; unsigned long flags; - u64 pte_root; + u64 new; =20 spin_lock_irqsave(&pdomain->lock, flags); if (!(pdomain->dirty_tracking ^ enable)) { @@ -2801,16 +2801,15 @@ static int amd_iommu_set_dirty_tracking(struct iomm= u_domain *domain, } =20 list_for_each_entry(dev_data, &pdomain->dev_list, list) { + spin_lock(&dev_data->dte_lock); iommu =3D get_amd_iommu_from_dev_data(dev_data); - - dev_table =3D get_dev_table(iommu); - pte_root =3D dev_table[dev_data->devid].data[0]; - - pte_root =3D (enable ? pte_root | DTE_FLAG_HAD : - pte_root & ~DTE_FLAG_HAD); + dte =3D &get_dev_table(iommu)[dev_data->devid]; + new =3D READ_ONCE(dte->data[0]); + new =3D (enable ? new | DTE_FLAG_HAD : new & ~DTE_FLAG_HAD); + WRITE_ONCE(dte->data[0], new); + spin_unlock(&dev_data->dte_lock); =20 /* Flush device DTE */ - dev_table[dev_data->devid].data[0] =3D pte_root; device_flush_dte(dev_data); domain_flush =3D true; } @@ -3075,17 +3074,23 @@ static void iommu_flush_irt_and_complete(struct amd= _iommu *iommu, u16 devid) static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid, struct irq_remap_table *table) { - u64 dte; - struct dev_table_entry *dev_table =3D get_dev_table(iommu); + u64 new; + struct dev_table_entry *dte =3D &get_dev_table(iommu)[devid]; + struct iommu_dev_data *dev_data =3D search_dev_data(iommu, devid); + + if (dev_data) + spin_lock(&dev_data->dte_lock); =20 - dte =3D dev_table[devid].data[2]; - dte &=3D ~DTE_IRQ_PHYS_ADDR_MASK; - dte |=3D iommu_virt_to_phys(table->table); - dte |=3D DTE_IRQ_REMAP_INTCTL; - dte |=3D DTE_INTTABLEN; - dte |=3D DTE_IRQ_REMAP_ENABLE; + new =3D READ_ONCE(dte->data[2]); + new &=3D ~DTE_IRQ_PHYS_ADDR_MASK; + new |=3D iommu_virt_to_phys(table->table); + new |=3D DTE_IRQ_REMAP_INTCTL; + new |=3D DTE_INTTABLEN; + new |=3D DTE_IRQ_REMAP_ENABLE; + WRITE_ONCE(dte->data[2], new); =20 - dev_table[devid].data[2] =3D dte; + if (dev_data) + spin_unlock(&dev_data->dte_lock); } =20 static struct irq_remap_table *get_irq_table(struct amd_iommu *iommu, u16 = devid) --=20 2.34.1