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Correct the _MASK and _SHIFT macros to use the appropriate mask and shift. Fixes: 35f74c0c5dce ("stmmac: add GMAC4 DMA/CORE Header File") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/eth= ernet/stmicro/stmmac/dwmac4.h index 93a78fd0737b..acbe5a027c85 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -389,8 +389,8 @@ static inline u32 mtl_chanx_base_addr(const struct dwma= c4_addrs *addrs, =20 #define MTL_OP_MODE_EHFC BIT(7) =20 -#define MTL_OP_MODE_RTC_MASK 0x18 -#define MTL_OP_MODE_RTC_SHIFT 3 +#define MTL_OP_MODE_RTC_MASK GENMASK(1, 0) +#define MTL_OP_MODE_RTC_SHIFT 0 =20 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) #define MTL_OP_MODE_RTC_64 0 --=20 2.34.1 From nobody Tue Nov 26 07:01:11 2024 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2126.outbound.protection.partner.outlook.cn [139.219.146.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C7D818756A; Wed, 16 Oct 2024 03:18:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.126 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729048741; cv=fail; b=B/APHm9d3hxJ3ivRJDq7Z0Y42ltIylzqJXc+pkgN1kOs3DvMZojDByHkHrvqLRjK2slV4vjiqlDNGOQ70h+yVAYVQrT80Qm3Ilfg8X75+Bu32eE80yyd8ObM1lyQ4be6phiRmv8hT4fp8gYVmZ/5E7z7uRhQPsNt6t8Wkeyx8oo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729048741; c=relaxed/simple; bh=HW8KSwXWeO/6JE4pbs1n16h4fsVPU8jQQFlgxBrKAI0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=IIqX+f2SKOEui5hZGDFTYmnFFgPTG1ltjQ2QO+J2h/26muQzLn4tThQserE2vcmUcqWqg7yCJTPk2CRgB8EaEta3e2s7nK0AaFZkiLCEv1iWkoPYd0lnIviRzteLuZ3/xcEZcOBPruDuTyV8+nhK7qDCWxril8QNkxejfpqLwv0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.146.126 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=U32De4qvwgVrbFAvEXm3lVD3JjO4SbLlKTbdnYh6gZ0IKsCQ/ZStb8Zqtrvw2pTTZgBstourqgon/5VeXZ7wZCf3poyaQDC7zFIgq654KT7U/8OXPy/gw1lT213LADrIw+CCCWitA4fTagAWFJsuvxc9eSVLH+DKDp7Lxei6ABqO+syhJ4Fcyrslq+Z2qod/bTHiH3PXZir4qjRX6+NNsmnUo6nzoDo9M1TDuiqRtwrhYC0eDMubDQ8cQPnyYCcC5oS8yKvMuBEHhn57Yad0ADRM+LoifMaeQC9eTFDeKnOHJsPansn24j/k2dZDs3IYWkLdvvM7236ciUd8XzrWHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ImfW7z7XD5azVTc+abegwuNShrnp0d2Wh4zrw+IKVkY=; b=L7CxUQ+rVV1NTLSMET62sqLnajtDTg2qjzYhtLtEwDB86RPI/2pXspo1JwbmzUyi9fIbRG5Uw4c1oJLHUanCmRxFj17ugNKF382LhztmgRPnDKCYGd7uReFgWJRGcgaHCcSKX3U8OA/L5oAKiod521ppur1SbtMNv0YRcb/coWbe0JoYxzRe9CBI8kY8Qo/FuTMoBJJgSYC/quXXV3nttaLOV9rE1BXqBjCfA2H0mYNJ2S7AzwvX4X1biuDWqJdeN9iqdRobV42xivC5OfjvyvMeSyb8pmFzsQx31O8F2+N4cZKDZw170fmUhlu/SXzofw5g4D+N5XRkub5ulKkeDA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) by ZQZPR01MB0961.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:9::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.21; Wed, 16 Oct 2024 03:18:56 +0000 Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095]) by ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095%4]) with mapi id 15.20.8048.013; Wed, 16 Oct 2024 03:18:56 +0000 From: Ley Foon Tan To: Alexandre Torgue , Jose Abreu Cc: "David S . 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charset="utf-8" In order to mask off the bits, we need to use the '~' operator to invert all the bits of _MASK and clear them. Fixes: 48863ce5940f ("stmmac: add DMA support for GMAC 4.xx") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_dma.c index e0165358c4ac..4e1b1bd98f68 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -266,7 +266,7 @@ static void dwmac4_dma_rx_chan_op_mode(struct stmmac_pr= iv *priv, } else { pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); mtl_rx_op &=3D ~MTL_OP_MODE_RSF; - mtl_rx_op &=3D MTL_OP_MODE_RTC_MASK; + mtl_rx_op &=3D ~MTL_OP_MODE_RTC_MASK; if (mode <=3D 32) mtl_rx_op |=3D MTL_OP_MODE_RTC_32; else if (mode <=3D 64) @@ -335,7 +335,7 @@ static void dwmac4_dma_tx_chan_op_mode(struct stmmac_pr= iv *priv, } else { pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); mtl_tx_op &=3D ~MTL_OP_MODE_TSF; - mtl_tx_op &=3D MTL_OP_MODE_TTC_MASK; + mtl_tx_op &=3D ~MTL_OP_MODE_TTC_MASK; /* Set the transmit threshold */ if (mode <=3D 32) mtl_tx_op |=3D MTL_OP_MODE_TTC_32; --=20 2.34.1 From nobody Tue Nov 26 07:01:11 2024 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2131.outbound.protection.partner.outlook.cn [139.219.146.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7720618A6AA; Wed, 16 Oct 2024 03:19:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.131 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729048745; cv=fail; b=CaV39Ckk6gulpDYOVM9y1aXd98Ho9fbgg3v8SK9DK3TebqkGN4nHKQV3dSM0hw3/MZdo8l75eQ/pgir2B0cjiY2JyYGGeeVNMTzYanmvcR8bEjh1+g6M/OSwDfO2rshPDADlCVN1FyOjaVTbz7RE/IkwfF6Vu3uhSsuvDUnZ3gM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729048745; c=relaxed/simple; bh=R+EeBlj86pRNtPtgXv896mqaSsSseyfHwsT8jQ5djoc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=PyE0CAeLPAKiNZvvziSuEjFNciXm6pt5lLWABmeR+b4eoBX1BX9R3P9DtqOneYUj4Cl+7Mpy32ADwsxGzOoFoh87xrSIZ5lLmz7raaNRFqG7SWNHsX2E0Ic48AcDAgozeFhzJGTxTET8qyPL3mGNvHOjihjze3fxXFwwOO45mFE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.146.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BbyjTeA07B1TMFziCaQcJkhKK31rX+VxlcArzux8ocF3oVPwG9VSW6JPrnM1oZt/1vyt/PCBTqM3ZK0gLX1rY8UaDBmWecVVy65umdXjfSamRFj8uFBL4szF38N2Ogm6/82gZ50Ydu0+PxQfR4IaHVhjEcftd0FBcd8Qu+nigbHngXTUfgTEnhyprHS5NI0hB//f++Y12LALmRq3nkG43Rzw81UyNCjzDeV5qn+vZlJuOGuwbCrVX0lefzIWT8OezzLmdlogtmqDT8SvMNuoVI9ELgmM2icj9/8qfVMJCZ5P6m8tzCKXOixSTMemt2JBz0h+/UfuagalXjhIqrml4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/sNVfhZi9kq6WRMkg6s9bACOW5z61wVpEKgboggd3Zs=; b=JdqgtoHYGz42Xqsjkwcmms6IGeXU0qPjlN+vVqLXLNAOVQnWLOr0nfNYf7eTujhcBCVvZQ58nxmj27Fo3Jhdylry7COSmkxwllyh3NCmq+tZHBZiv64FdBqzKOdGKR0kQ9GZHYlzVztXA/2U25JqHY9n3EM7CxcgSI4WdOHI3uSO7uOt/V0dvZtfzxbdmDytoxQTO7qjIvt3x4Vh5vAM7O1npQ0MspXAulRMy5LwsabBOJ0kk/LJ4UVhfSvX4ZFouFc5lWpeM9QBpoOqaYlhyPnOk5stDcgDjyhhvd/fQmUXjb7KfVEMrTKlo+TnNjybWYNIzOpIXRgzWlflvtmOZA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) by ZQZPR01MB1060.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:b::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18; Wed, 16 Oct 2024 03:18:58 +0000 Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095]) by ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095%4]) with mapi id 15.20.8048.013; Wed, 16 Oct 2024 03:18:58 +0000 From: Ley Foon Tan To: Alexandre Torgue , Jose Abreu Cc: "David S . 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charset="utf-8" The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal Interrupt Summary (AIS). Move the RWT handling out of the AIS condition statement. From databook, the AIS is the logical OR of the following interrupt bits: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Fixes: 48863ce5940f ("stmmac: add DMA support for GMAC 4.xx") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_lib.c index 0d185e54eb7e..57c03d491774 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void= __iomem *ioaddr, x->rx_buf_unav_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_RPS)) x->rx_process_stopped_irq++; - if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) - x->rx_watchdog_irq++; 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charset="utf-8" The high address will display as 0 if the driver does not set the reg_space[]. To fix this, read the high address registers and update the reg_space[] accordingly. Fixes: fbf68229ffe7 ("net: stmmac: unify registers dumps methods") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 ++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_dma.c index 4e1b1bd98f68..60cee7a06ba2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -203,8 +203,12 @@ static void _dwmac4_dump_dma_regs(struct stmmac_priv *= priv, readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel)); reg_space[DMA_CHAN_RX_CONTROL(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_TX_BASE_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_TX_BASE_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_RX_BASE_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_RX_BASE_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel)); reg_space[DMA_CHAN_TX_END_ADDR(default_addrs, channel) / 4] =3D @@ -225,8 +229,12 @@ static void _dwmac4_dump_dma_regs(struct stmmac_priv *= priv, readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel)); reg_space[DMA_CHAN_CUR_RX_DESC(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_CUR_TX_BUF_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_CUR_RX_BUF_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel)); reg_space[DMA_CHAN_STATUS(default_addrs, channel) / 4] =3D diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_dma.h index 17d9120db5fe..4f980dcd3958 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h @@ -127,7 +127,9 @@ static inline u32 dma_chanx_base_addr(const struct dwma= c4_addrs *addrs, #define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x)= + 0x3c) #define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x= 44) #define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x= 4c) +#define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, = x) + 0x50) #define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) = + 0x54) +#define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, = x) + 0x58) #define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) = + 0x5c) #define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60) =20 --=20 2.34.1