From nobody Tue Nov 26 22:27:37 2024 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CCED16C687; Wed, 16 Oct 2024 02:24:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729045470; cv=none; b=pF5z/5DMesm7YmKYDASTXgUE4b1L7l+oDWBP6Z2dwinN4r46V7MrMZsuFmQybg4tb2NUiO8UDt20tP2DuAgqUDCbI4YCs+QH0XfDoZYbsGbglPxM3P+4daf8AgMRod0CK0dOfBWomgzfgyaE4giVHOAicVMP9XhhL/VuEIP1UPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729045470; c=relaxed/simple; bh=/gs8OVCe+lyzg0Vqu1cVRIlxnwv7ZmkRglBidgWBdy4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Jz+9GDcO3p/7U999mkpNIsbKrUrC1Ee5V85lm49SEsr4JzOtwe3z6LEJaoDP2s49sX7qdBxdIJUKZVcwRJHn+WmG/Kfp8VGua6lGMT44kEcbwooYaQ/ZAbIFsUJ+lJZZNyetZU3tnG3yl1vqpr2yOCh85bPMTwOGzbrOpK424WE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 16 Oct 2024 10:24:14 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Wed, 16 Oct 2024 10:24:14 +0800 From: Kevin Chen To: , , , , , , , , , , Subject: [PATCH v4 2/2] irqchip/aspeed-intc: Add AST27XX INTC support Date: Wed, 16 Oct 2024 10:24:10 +0800 Message-ID: <20241016022410.1154574-3-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241016022410.1154574-1-kevin_chen@aspeedtech.com> References: <20241016022410.1154574-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Aspeed Interrupt Controller on Aspeed Silicon SoCs. ASPEED interrupt controller(INTC) maps the internal interrupt sources to a parent interrupt controller, which can be GIC or INTC. Signed-off-by: Kevin Chen --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-aspeed-intc.c | 140 ++++++++++++++++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 drivers/irqchip/irq-aspeed-intc.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e3679ec2b9f7..086911bf4db6 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_SEI) +=3D irq-mvebu-sei.o obj-$(CONFIG_LS_EXTIRQ) +=3D irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o +obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-intc.o obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o obj-$(CONFIG_STM32_EXTI) +=3D irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) +=3D qcom-irq-combiner.o diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed= -intc.c new file mode 100644 index 000000000000..faf18a675395 --- /dev/null +++ b/drivers/irqchip/irq-aspeed-intc.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Aspeed Interrupt Controller. + * + * Copyright (C) 2023 ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTC_INT_ENABLE_REG 0x00 +#define INTC_INT_STATUS_REG 0x04 +#define INTC_IRQS_PER_WORD 32 + +struct aspeed_intc_ic { + void __iomem *base; + raw_spinlock_t gic_lock; + raw_spinlock_t intc_lock; + struct irq_domain *irq_domain; +}; + +static void aspeed_intc_ic_irq_handler(struct irq_desc *desc) +{ + struct aspeed_intc_ic *intc_ic =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + scoped_guard(raw_spinlock, &intc_ic->gic_lock) { + unsigned long bit, status; + + status =3D readl(intc_ic->base + INTC_INT_STATUS_REG); + for_each_set_bit(bit, &status, INTC_IRQS_PER_WORD) { + generic_handle_domain_irq(intc_ic->irq_domain, bit); + writel(BIT(bit), intc_ic->base + INTC_INT_STATUS_REG); + } + } + + chained_irq_exit(chip, desc); +} + +static void aspeed_intc_irq_mask(struct irq_data *data) +{ + struct aspeed_intc_ic *intc_ic =3D irq_data_get_irq_chip_data(data); + unsigned int mask =3D readl(intc_ic->base + INTC_INT_ENABLE_REG) & ~BIT(d= ata->hwirq); + + guard(raw_spinlock)(&intc_ic->intc_lock); + writel(mask, intc_ic->base + INTC_INT_ENABLE_REG); +} + +static void aspeed_intc_irq_unmask(struct irq_data *data) +{ + struct aspeed_intc_ic *intc_ic =3D irq_data_get_irq_chip_data(data); + unsigned int unmask =3D readl(intc_ic->base + INTC_INT_ENABLE_REG) | BIT(= data->hwirq); + + guard(raw_spinlock)(&intc_ic->intc_lock); + writel(unmask, intc_ic->base + INTC_INT_ENABLE_REG); +} + +static struct irq_chip aspeed_intc_chip =3D { + .name =3D "ASPEED INTC", + .irq_mask =3D aspeed_intc_irq_mask, + .irq_unmask =3D aspeed_intc_irq_unmask, +}; + +static int aspeed_intc_ic_map_irq_domain(struct irq_domain *domain, unsign= ed int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &aspeed_intc_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops aspeed_intc_ic_irq_domain_ops =3D { + .map =3D aspeed_intc_ic_map_irq_domain, +}; + +static int __init aspeed_intc_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_intc_ic *intc_ic; + int ret =3D 0; + int irq, i; + + intc_ic =3D kzalloc(sizeof(*intc_ic), GFP_KERNEL); + if (!intc_ic) + return -ENOMEM; + + intc_ic->base =3D of_iomap(node, 0); + if (!intc_ic->base) { + pr_err("Failed to iomap intc_ic base\n"); + ret =3D -ENOMEM; + goto err_free_ic; + } + writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG); + writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG); + + intc_ic->irq_domain =3D irq_domain_add_linear(node, INTC_IRQS_PER_WORD, + &aspeed_intc_ic_irq_domain_ops, intc_ic); + if (!intc_ic->irq_domain) { + ret =3D -ENOMEM; + goto err_iounmap; + } + + raw_spin_lock_init(&intc_ic->gic_lock); + raw_spin_lock_init(&intc_ic->intc_lock); + + /* Check all the irq numbers valid. If not, unmaps all the base and frees= the data. */ + for (i =3D 0; i < of_irq_count(node); i++) { + irq =3D irq_of_parse_and_map(node, i); + if (!irq) { + pr_err("Failed to get irq number\n"); + ret =3D -EINVAL; + goto err_iounmap; + } + } + + for (i =3D 0; i < of_irq_count(node); i++) { + irq =3D irq_of_parse_and_map(node, i); + irq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_i= c); + } + + return 0; + +err_iounmap: + iounmap(intc_ic->base); +err_free_ic: + kfree(intc_ic); + return ret; +} + +IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-ic", aspeed_intc_ic_= of_init); --=20 2.34.1