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When 'bad_data_bit' is less than 32, 'bad_data_bit - 32' becomes negative, and left-shifting by a negative value in C is undefined behavior. Fix this by combining 'cap_high' and 'cap_low' into a 64-bit variable. Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx") Signed-off-by: Priyanka Singh Reviewed-by: Sherry Sun Signed-off-by: Li Yang Signed-off-by: Frank Li --- drivers/edac/fsl_ddr_edac.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index 7a9fb1202f1a0..846a4ba25342a 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -328,6 +328,9 @@ static void fsl_mc_check(struct mem_ctl_info *mci) * TODO: Add support for 32-bit wide buses */ if ((err_detect & DDR_EDE_SBE) && (bus_width =3D=3D 64)) { + u64 cap =3D (u64)cap_high << 32 | (u64)cap_low; + u32 s =3D syndrome; + sbe_ecc_decode(cap_high, cap_low, syndrome, &bad_data_bit, &bad_ecc_bit); =20 @@ -338,11 +341,15 @@ static void fsl_mc_check(struct mem_ctl_info *mci) fsl_mc_printk(mci, KERN_ERR, "Faulty ECC bit: %d\n", bad_ecc_bit); =20 + if (bad_data_bit >=3D 0) + cap ^=3D 1ULL << bad_data_bit; + + if (bad_ecc_bit >=3D 0) + s ^=3D 1 << bad_ecc_bit; + fsl_mc_printk(mci, KERN_ERR, "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", - cap_high ^ (1 << (bad_data_bit - 32)), - cap_low ^ (1 << bad_data_bit), - syndrome ^ (1 << bad_ecc_bit)); + upper_32_bits(cap), lower_32_bits(cap), s); } =20 fsl_mc_printk(mci, KERN_ERR, --=20 2.34.1