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Each co-existing SE can have one or multiple e= xclusive +MUs, dedicated to itself. None of the MU is shared between two SEs. +Communication of the MU is realized using the Linux mailbox driver. + +NXP Secure Enclave(SE) Interface +-------------------------------- +Although MU(s) is/are not shared between SE(s). But for SoC like i.MX95 wh= ich has +multiple SE(s) like HSM, V2X-HSM, V2X-SHE; all the SE(s) and their interfa= ces 'se-if' +that is/are dedicated to a particular SE will be enumerated and provisione= d using the +single compatible node("fsl,imx95-se"). + +Each 'se-if' comprise of twp layers: +- (C_DEV Layer) User-Space software-access interface. +- (Service Layer) OS-level software-access interface. + + +--------------------------------------------+ + | Character Device(C_DEV) | + | | + | +---------+ +---------+ +---------+ | + | | misc #1 | | misc #2 | ... | misc #n | | + | | dev | | dev | | dev | | + | +---------+ +---------+ +---------+ | + | +-------------------------+ | + | | Misc. Dev Synchr. Logic | | + | +-------------------------+ | + | | + +--------------------------------------------+ + + +--------------------------------------------+ + | Service Layer | + | | + | +-----------------------------+ | + | | Message Serialization Logic | | + | +-----------------------------+ | + | +---------------+ | + | | imx-mailbox | | + | | mailbox.c | | + | +---------------+ | + | | + +--------------------------------------------+ + +- service layer: + This layer is responsible for ensuring the communication protocol that i= s defined + for communication with firmware. + + FW Communication protocol ensures two things: + - Serializing the messages to be sent over an MU. + + - FW can handle one command message at a time. + +- c_dev: + This layer offers character device contexts, created as '/dev/_mux_c= hx'. + Using these multiple device contexts that are getting multiplexed over a= single MU, + userspace application(s) can call fops like write/read to send the comma= nd message, + and read back the command response message to/from Firmware. + fops like read & write use the above defined service layer API(s) to com= municate with + Firmware. + + Misc-device(/dev/_mux_chn) synchronization protocol: + + Non-Secure + Secure + | + | + +---------+ +-------------+ | + | se_fw.c +<---->+imx-mailbox.c| | + | | | mailbox.c +<-->+------+ +------+ + +---+-----+ +-------------+ | MU X +<-->+ ELE | + | +------+ +------+ + +----------------+ | + | | | + v v | + logical logical | + receiver waiter | + + + | + | | | + | | | + | +----+------+ | + | | | | + | | | | + device_ctx device_ctx device_ctx | + | + User 0 User 1 User Y | + +------+ +------+ +------+ | + |misc.c| |misc.c| |misc.c| | + kernel space +------+ +------+ +------+ | + | + +------------------------------------------------------ | + | | | | + userspace /dev/ele_muXch0 | | | + /dev/ele_muXch1 | | + /dev/ele_muXchY | + | + +When a user sends a command to the firmware, it registers its device_ctx +as waiter of a response from firmware. + +Enclave's Firmware owns the storage management, over Linux filesystem. +For this c_dev provisions a dedicated slave device called "receiver". + +.. kernel-doc:: drivers/firmware/imx/se_fw.c + :export: --=20 2.34.1 From nobody Tue Nov 26 17:19:49 2024 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2076.outbound.protection.outlook.com [40.107.22.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B82A0210192; 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This driver enables communication ensuring well defined message sequence protocol between Application Core and enclave's firmware. Driver configures multiple misc-device on the MU, for multiple user-space applications, to be able to communicate over single MU. It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc. Signed-off-by: Pankaj Gupta Reviewed-by: Rob Herring (Arm) Reviewed-by: Conor Dooley --- .../devicetree/bindings/firmware/fsl,imx-se.yaml | 91 ++++++++++++++++++= ++++ 1 file changed, 91 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/fsl,imx-se.yaml b/D= ocumentation/devicetree/bindings/firmware/fsl,imx-se.yaml new file mode 100644 index 000000000000..0b617f61640f --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/fsl,imx-se.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/fsl,imx-se.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX HW Secure Enclave(s) EdgeLock Enclave + +maintainers: + - Pankaj Gupta + +description: | + NXP's SoC may contain one or multiple embedded secure-enclave HW + IP(s) like i.MX EdgeLock Enclave, V2X etc. These NXP's HW IP(s) + enables features like + - Hardware Security Module (HSM), + - Security Hardware Extension (SHE), and + - Vehicular to Anything (V2X) + + Communication interface to the secure-enclaves(se) is based on the + messaging unit(s). + +properties: + compatible: + enum: + - fsl,imx8ulp-se + - fsl,imx93-se + - fsl,imx95-se + + mboxes: + items: + - description: mailbox phandle to send message to se firmware + - description: mailbox phandle to receive message from se firmware + + mbox-names: + items: + - const: tx + - const: rx + + memory-region: + maxItems: 1 + + sram: + maxItems: 1 + +required: + - compatible + - mboxes + - mbox-names + +allOf: + # memory-region + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8ulp-se + - fsl,imx93-se + then: + required: + - memory-region + else: + properties: + memory-region: false + + # sram + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8ulp-se + then: + required: + - sram + + else: + properties: + sram: false + +additionalProperties: false + +examples: + - | + secure-enclave { + compatible =3D "fsl,imx95-se"; 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EdgeLock Enclave has a hardware limitation of restricted access to DDR address: 0x80000000 to 0xAFFFFFFF, so reserve 1MB of DDR memory region from 0x80000000. Signed-off-by: Pankaj Gupta --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 17 ++++++++++++++++- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 13 +++++++++++-- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boo= t/dts/freescale/imx8ulp-evk.dts index e937e5f8fa8b..f5963f4043c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2024 NXP */ =20 /dts-v1/; @@ -19,6 +19,17 @@ memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0 0x80000000>; }; + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ele_reserved: ele-reserved@90000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x90000000 0 0x100000>; + no-map; + }; + }; =20 reserved-memory { #address-cells =3D <2>; @@ -204,6 +215,10 @@ &usdhc0 { status =3D "okay"; }; =20 +&ele_if0 { + memory-region =3D <&ele_reserved>; +}; + &fec { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&pinctrl_enet>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index e32d5afcf4a9..f98629b7f4cc 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2024 NXP */ =20 #include @@ -152,7 +152,7 @@ sosc: clock-sosc { #clock-cells =3D <0>; }; =20 - sram@2201f000 { + sram0: sram@2201f000 { compatible =3D "mmio-sram"; reg =3D <0x0 0x2201f000 0x0 0x1000>; =20 @@ -167,6 +167,8 @@ scmi_buf: scmi-sram-section@0 { }; =20 firmware { + #address-cells =3D <1>; + #size-cells =3D <0>; scmi { compatible =3D "arm,scmi-smc"; arm,smc-id =3D <0xc20000fe>; @@ -184,6 +186,13 @@ scmi_sensor: protocol@15 { #thermal-sensor-cells =3D <1>; }; }; + + ele_if0: secure-enclave { + compatible =3D "fsl,imx8ulp-se"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241016-imx-se-if-v9-4-fd8fa0c04eab@nxp.com> References: <20241016-imx-se-if-v9-0-fd8fa0c04eab@nxp.com> In-Reply-To: <20241016-imx-se-if-v9-0-fd8fa0c04eab@nxp.com> To: Jonathan Corbet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Pankaj Gupta Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729095547; l=39201; i=pankaj.gupta@nxp.com; s=20240523; h=from:subject:message-id; bh=EpQSowENmv2+76MaNuhYEIyM0LGtLX4F0BAw4YtV4+0=; b=BJvt8paJdPNcPRFT+HGOdGO46zzqvzlGyVuaDonyivAwdNnzpBPtm/CK3/sQ3/mqAAePV1ZkK 8Tw3jKvMYTWCPP6VXtJIMJWmcuiFkNkz7nG2EOgOQUPBWv7m2xZCUKq X-Developer-Key: i=pankaj.gupta@nxp.com; a=ed25519; pk=OA0pBQoupy5lV0XfKzD8B0OOBVB6tpAoIf+0x1bYGRg= X-ClientProxiedBy: SG2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:3:18::25) To DU2PR04MB8599.eurprd04.prod.outlook.com (2603:10a6:10:2da::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8599:EE_|AM0PR04MB6884:EE_ X-MS-Office365-Filtering-Correlation-Id: c0b91ca0-66f6-471c-3ac5-08dcedfee5bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|376014|1800799024|7416014|366016|38350700014; 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The secure enclave FW communicates on a dedicated messaging unit(MU) based interface(s) with application core, where kernel is running. It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93. This patch adds the driver for communication interface to secure-enclave, for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock Enclave (ELE) from Kernel-space, used by kernel management layers like - DM-Crypt. Signed-off-by: Pankaj Gupta --- drivers/firmware/imx/Kconfig | 13 + drivers/firmware/imx/Makefile | 2 + drivers/firmware/imx/ele_base_msg.c | 279 ++++++++++++++++++ drivers/firmware/imx/ele_base_msg.h | 94 ++++++ drivers/firmware/imx/ele_common.c | 320 +++++++++++++++++++++ drivers/firmware/imx/ele_common.h | 51 ++++ drivers/firmware/imx/se_ctrl.c | 552 ++++++++++++++++++++++++++++++++= ++++ drivers/firmware/imx/se_ctrl.h | 94 ++++++ include/linux/firmware/imx/se_api.h | 14 + 9 files changed, 1419 insertions(+) diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig index 477d3f32d99a..ccd9f9e0652e 100644 --- a/drivers/firmware/imx/Kconfig +++ b/drivers/firmware/imx/Kconfig @@ -33,3 +33,16 @@ config IMX_SCMI_MISC_DRV core that could provide misc functions such as board control. =20 This driver can also be built as a module. + +config IMX_SEC_ENCLAVE + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver= ." + depends on IMX_MBOX && ARCH_MXC && ARM64 + select FW_LOADER + default m if ARCH_MXC + + help + It is possible to use APIs exposed by the iMX Secure Enclave HW IP call= ed: + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93), + like base, HSM, V2X & SHE using the SAB protocol via the shared Messa= ging + Unit. This driver exposes these interfaces via a set of file descript= ors + allowing to configure shared memory, send and receive messages. diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile index 8d046c341be8..4e1d2706535d 100644 --- a/drivers/firmware/imx/Makefile +++ b/drivers/firmware/imx/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_IMX_DSP) +=3D imx-dsp.o obj-$(CONFIG_IMX_SCU) +=3D imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-so= c.o obj-${CONFIG_IMX_SCMI_MISC_DRV} +=3D sm-misc.o +sec_enclave-objs =3D se_ctrl.o ele_common.o ele_base_msg.o +obj-${CONFIG_IMX_SEC_ENCLAVE} +=3D sec_enclave.o diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele= _base_msg.c new file mode 100644 index 000000000000..53c83eddd52a --- /dev/null +++ b/drivers/firmware/imx/ele_base_msg.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include + +#include +#include +#include + +#include "ele_base_msg.h" +#include "ele_common.h" + +int ele_get_info(struct se_if_priv *priv, struct ele_dev_info *s_info) +{ + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_api_msg *rx_msg __free(kfree) =3D NULL; + dma_addr_t get_info_addr =3D 0; + u32 *get_info_data =3D NULL; + int ret =3D 0; + + if (!priv) { + ret =3D -EINVAL; + return ret; + } + + memset(s_info, 0x0, sizeof(*s_info)); + + if (priv->mem_pool) + get_info_data =3D gen_pool_dma_alloc(priv->mem_pool, + ELE_GET_INFO_BUFF_SZ, + &get_info_addr); + else + get_info_data =3D dma_alloc_coherent(priv->dev, + ELE_GET_INFO_BUFF_SZ, + &get_info_addr, + GFP_KERNEL); + if (!get_info_data) { + ret =3D -ENOMEM; + dev_dbg(priv->dev, + "%s: Failed to allocate get_info_addr.\n", + __func__); + return ret; + } + + tx_msg =3D kzalloc(ELE_GET_INFO_REQ_MSG_SZ, GFP_KERNEL); + if (!tx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + rx_msg =3D kzalloc(ELE_GET_INFO_RSP_MSG_SZ, GFP_KERNEL); + if (!rx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + ret =3D se_fill_cmd_msg_hdr(priv, + (struct se_msg_hdr *)&tx_msg->header, + ELE_GET_INFO_REQ, + ELE_GET_INFO_REQ_MSG_SZ, + true); + if (ret) + goto exit; + + tx_msg->data[0] =3D upper_32_bits(get_info_addr); + tx_msg->data[1] =3D lower_32_bits(get_info_addr); + tx_msg->data[2] =3D sizeof(*s_info); + ret =3D ele_msg_send_rcv(priv, + tx_msg, + ELE_GET_INFO_REQ_MSG_SZ, + rx_msg, + ELE_GET_INFO_RSP_MSG_SZ); + if (ret < 0) + goto exit; + + ret =3D se_val_rsp_hdr_n_status(priv, + rx_msg, + ELE_GET_INFO_REQ, + ELE_GET_INFO_RSP_MSG_SZ, + true); + + memcpy(s_info, get_info_data, sizeof(*s_info)); + +exit: + if (priv->mem_pool) + gen_pool_free(priv->mem_pool, + (u64) get_info_data, + ELE_GET_INFO_BUFF_SZ); + else + dma_free_coherent(priv->dev, + ELE_GET_INFO_BUFF_SZ, + get_info_data, + get_info_addr); + + return ret; +} + +int ele_fetch_soc_info(struct se_if_priv *priv, u16 *soc_rev, u64 *serial_= num) +{ + struct ele_dev_info s_info =3D {0}; + int err; + + err =3D ele_get_info(priv, &s_info); + if (err < 0) + return err; + + if (soc_rev) + *soc_rev =3D s_info.d_info.soc_rev; + if (serial_num) + *serial_num =3D GET_SERIAL_NUM_FROM_UID(s_info.d_info.uid, MAX_UID_SIZE = >> 2); + + return err; +} + +int ele_ping(struct se_if_priv *priv) +{ + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_api_msg *rx_msg __free(kfree) =3D NULL; + int ret =3D 0; + + if (!priv) { + ret =3D -EINVAL; + goto exit; + } + + tx_msg =3D kzalloc(ELE_PING_REQ_SZ, GFP_KERNEL); + if (!tx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + rx_msg =3D kzalloc(ELE_PING_RSP_SZ, GFP_KERNEL); + if (!rx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + ret =3D se_fill_cmd_msg_hdr(priv, + (struct se_msg_hdr *)&tx_msg->header, + ELE_PING_REQ, ELE_PING_REQ_SZ, true); + if (ret) { + dev_err(priv->dev, "Error: se_fill_cmd_msg_hdr failed.\n"); + goto exit; + } + + ret =3D ele_msg_send_rcv(priv, + tx_msg, + ELE_PING_REQ_SZ, + rx_msg, + ELE_PING_RSP_SZ); + if (ret < 0) + goto exit; + + ret =3D se_val_rsp_hdr_n_status(priv, + rx_msg, + ELE_PING_REQ, + ELE_PING_RSP_SZ, + true); +exit: + return ret; +} + +int ele_service_swap(struct se_if_priv *priv, + phys_addr_t addr, + u32 addr_size, u16 flag) +{ + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_api_msg *rx_msg __free(kfree) =3D NULL; + int ret =3D 0; + + if (!priv) { + ret =3D -EINVAL; + goto exit; + } + + tx_msg =3D kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ, GFP_KERNEL); + if (!tx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + rx_msg =3D kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ, GFP_KERNEL); + if (!rx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + ret =3D se_fill_cmd_msg_hdr(priv, + (struct se_msg_hdr *)&tx_msg->header, + ELE_SERVICE_SWAP_REQ, + ELE_SERVICE_SWAP_REQ_MSG_SZ, true); + if (ret) + goto exit; + + tx_msg->data[0] =3D flag; + tx_msg->data[1] =3D addr_size; + tx_msg->data[2] =3D ELE_NONE_VAL; + tx_msg->data[3] =3D lower_32_bits(addr); + tx_msg->data[4] =3D se_add_msg_crc((uint32_t *)&tx_msg[0], + ELE_SERVICE_SWAP_REQ_MSG_SZ); + ret =3D ele_msg_send_rcv(priv, + tx_msg, + ELE_SERVICE_SWAP_REQ_MSG_SZ, + rx_msg, + ELE_SERVICE_SWAP_RSP_MSG_SZ); + if (ret < 0) + goto exit; + + ret =3D se_val_rsp_hdr_n_status(priv, + rx_msg, + ELE_SERVICE_SWAP_REQ, + ELE_SERVICE_SWAP_RSP_MSG_SZ, + true); + if (ret) + goto exit; + + if (flag =3D=3D ELE_IMEM_EXPORT) + ret =3D rx_msg->data[1]; + else + ret =3D 0; + +exit: + + return ret; +} + +int ele_fw_authenticate(struct se_if_priv *priv, phys_addr_t addr) +{ + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_api_msg *rx_msg __free(kfree) =3D NULL; + int ret =3D 0; + + if (!priv) { + ret =3D -EINVAL; + goto exit; + } + + tx_msg =3D kzalloc(ELE_FW_AUTH_REQ_SZ, GFP_KERNEL); + if (!tx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + rx_msg =3D kzalloc(ELE_FW_AUTH_RSP_MSG_SZ, GFP_KERNEL); + if (!rx_msg) { + ret =3D -ENOMEM; + goto exit; + } + + ret =3D se_fill_cmd_msg_hdr(priv, + (struct se_msg_hdr *)&tx_msg->header, + ELE_FW_AUTH_REQ, + ELE_FW_AUTH_REQ_SZ, + true); + if (ret) + goto exit; + + tx_msg->data[1] =3D upper_32_bits(addr); + tx_msg->data[0] =3D lower_32_bits(addr); + tx_msg->data[2] =3D addr; + + ret =3D ele_msg_send_rcv(priv, + tx_msg, + ELE_FW_AUTH_REQ_SZ, + rx_msg, + ELE_FW_AUTH_RSP_MSG_SZ); + if (ret < 0) + goto exit; + + ret =3D se_val_rsp_hdr_n_status(priv, + rx_msg, + ELE_FW_AUTH_REQ, + ELE_FW_AUTH_RSP_MSG_SZ, + true); +exit: + return ret; +} diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele= _base_msg.h new file mode 100644 index 000000000000..e390d35fc787 --- /dev/null +++ b/drivers/firmware/imx/ele_base_msg.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + * + * Header file for the EdgeLock Enclave Base API(s). + */ + +#ifndef ELE_BASE_MSG_H +#define ELE_BASE_MSG_H + +#include +#include + +#include "se_ctrl.h" + +#define ELE_NONE_VAL 0x0 + +#define ELE_GET_INFO_REQ 0xDA +#define ELE_GET_INFO_REQ_MSG_SZ 0x10 +#define ELE_GET_INFO_RSP_MSG_SZ 0x08 + +#define SOC_ID_MASK 0x0000FFFF + +#define MAX_UID_SIZE (16) +#define DEV_GETINFO_ROM_PATCH_SHA_SZ (32) +#define DEV_GETINFO_FW_SHA_SZ (32) +#define DEV_GETINFO_OEM_SRKH_SZ (64) +#define DEV_GETINFO_MIN_VER_MASK 0xFF +#define DEV_GETINFO_MAJ_VER_MASK 0xFF00 +#define ELE_DEV_INFO_EXTRA_SZ 0x60 + +struct dev_info { + uint8_t cmd; + uint8_t ver; + uint16_t length; + uint16_t soc_id; + uint16_t soc_rev; + uint16_t lmda_val; + uint8_t ssm_state; + uint8_t dev_atts_api_ver; + uint8_t uid[MAX_UID_SIZE]; + uint8_t sha_rom_patch[DEV_GETINFO_ROM_PATCH_SHA_SZ]; + uint8_t sha_fw[DEV_GETINFO_FW_SHA_SZ]; +}; + +struct dev_addn_info { + uint8_t oem_srkh[DEV_GETINFO_OEM_SRKH_SZ]; + uint8_t trng_state; + uint8_t csal_state; + uint8_t imem_state; + uint8_t reserved2; +}; + +struct ele_dev_info { + struct dev_info d_info; + struct dev_addn_info d_addn_info; +}; + +#define ELE_GET_INFO_BUFF_SZ (sizeof(struct ele_dev_info) \ + + ELE_DEV_INFO_EXTRA_SZ) + +#define GET_SERIAL_NUM_FROM_UID(x, uid_word_sz) \ + (((u64)(((u32 *)(x))[(uid_word_sz) - 1]) << 32) | ((u32 *)(x))[0]) + +#define ELE_DEBUG_DUMP_REQ 0x21 +#define ELE_DEBUG_DUMP_RSP_SZ 0x14 + +#define ELE_PING_REQ 0x01 +#define ELE_PING_REQ_SZ 0x04 +#define ELE_PING_RSP_SZ 0x08 + +#define ELE_SERVICE_SWAP_REQ 0xDF +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18 +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C +#define ELE_IMEM_SIZE 0x10000 +#define ELE_IMEM_STATE_OK 0xCA +#define ELE_IMEM_STATE_BAD 0xFE +#define ELE_IMEM_STATE_WORD 0x27 +#define ELE_IMEM_STATE_MASK 0x00ff0000 +#define ELE_IMEM_EXPORT 0x1 +#define ELE_IMEM_IMPORT 0x2 + +#define ELE_FW_AUTH_REQ 0x02 +#define ELE_FW_AUTH_REQ_SZ 0x10 +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08 + +int ele_get_info(struct se_if_priv *priv, struct ele_dev_info *s_info); +int ele_fetch_soc_info(struct se_if_priv *priv, u16 *soc_rev, u64 *serial_= num); +int ele_ping(struct se_if_priv *priv); +int ele_service_swap(struct se_if_priv *priv, + phys_addr_t addr, + u32 addr_size, u16 flag); +int ele_fw_authenticate(struct se_if_priv *priv, phys_addr_t addr); +#endif diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_c= ommon.c new file mode 100644 index 000000000000..f7c760bbc7a3 --- /dev/null +++ b/drivers/firmware/imx/ele_common.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include "ele_base_msg.h" +#include "ele_common.h" + +u32 se_add_msg_crc(u32 *msg, u32 msg_len) +{ + u32 nb_words =3D msg_len / (u32)sizeof(u32); + u32 crc =3D 0; + u32 i; + + for (i =3D 0; i < nb_words - 1; i++) + crc ^=3D *(msg + i); + + return crc; +} + +int ele_msg_rcv(struct se_if_priv *priv, + struct se_clbk_handle *se_clbk_hdl) +{ + int err =3D 0; + + do { + /* If callback is executed before entrying to wait state, + * it will immediately come out after entering the wait state, + * but completion_done(&se_clbk_hdl->done), will return false + * after exiting the wait state, with err =3D 0. + */ + err =3D wait_for_completion_interruptible(&se_clbk_hdl->done); + if (err =3D=3D -ERESTARTSYS) { + if (priv->waiting_rsp_clbk_hdl.rx_msg) { + priv->waiting_rsp_clbk_hdl.signal_rcvd =3D true; + continue; + } + dev_err(priv->dev, + "Err[0x%x]:Interrupted by signal.\n", + err); + err =3D -EINTR; + break; + } + } while (err !=3D 0); + + return err ? err : se_clbk_hdl->rx_msg_sz; +} + +int ele_msg_send(struct se_if_priv *priv, + void *tx_msg, + int tx_msg_sz) +{ + struct se_msg_hdr *header; + int err; + + header =3D tx_msg; + + /* + * Check that the size passed as argument matches the size + * carried in the message. + */ + if (header->size << 2 !=3D tx_msg_sz) { + err =3D -EINVAL; + dev_err(priv->dev, + "User buf hdr: 0x%x, sz mismatced with input-sz (%d !=3D %d).", + *(u32 *)header, + header->size << 2, tx_msg_sz); + goto exit; + } + + err =3D mbox_send_message(priv->tx_chan, tx_msg); + if (err < 0) { + dev_err(priv->dev, "Error: mbox_send_message failure.\n"); + return err; + } + err =3D tx_msg_sz; + +exit: + return err; +} + +/* API used for send/receive blocking call. */ +int ele_msg_send_rcv(struct se_if_priv *priv, + void *tx_msg, + int tx_msg_sz, + void *rx_msg, + int exp_rx_msg_sz) +{ + int err; + + guard(mutex)(&priv->se_if_cmd_lock); + + priv->waiting_rsp_clbk_hdl.rx_msg_sz =3D exp_rx_msg_sz; + priv->waiting_rsp_clbk_hdl.rx_msg =3D rx_msg; + + err =3D ele_msg_send(priv, tx_msg, tx_msg_sz); + if (err < 0) + goto exit; + + err =3D ele_msg_rcv(priv, &priv->waiting_rsp_clbk_hdl); + + if (priv->waiting_rsp_clbk_hdl.signal_rcvd) { + err =3D -EINTR; + priv->waiting_rsp_clbk_hdl.signal_rcvd =3D false; + } + +exit: + return err; +} + +static bool exception_for_size(struct se_if_priv *priv, + struct se_msg_hdr *header) +{ + /* List of API(s) that can be accepte variable length + * response buffer. + */ + if (header->command =3D=3D ELE_DEBUG_DUMP_REQ && + header->ver =3D=3D priv->if_defs->base_api_ver && + header->size >=3D 0 && + header->size <=3D ELE_DEBUG_DUMP_RSP_SZ) + return true; + + return false; +} + +/* + * Callback called by mailbox FW, when data is received. + */ +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg) +{ + struct se_clbk_handle *se_clbk_hdl; + struct device *dev =3D mbox_cl->dev; + struct se_msg_hdr *header; + struct se_if_priv *priv; + u32 rx_msg_sz; + + priv =3D dev_get_drvdata(dev); + + /* The function can be called with NULL msg */ + if (!msg) { + dev_err(dev, "Message is invalid\n"); + return; + } + + header =3D msg; + rx_msg_sz =3D header->size << 2; + + /* Incoming command: wake up the receiver if any. */ + if (header->tag =3D=3D priv->if_defs->cmd_tag) { + se_clbk_hdl =3D &priv->cmd_receiver_clbk_hdl; + dev_dbg(dev, + "Selecting cmd receiver for mesg header:0x%x.", + *(u32 *) header); + + /* Pre-allocated buffer of MAX_NVM_MSG_LEN + * as the NVM command are initiated by FW. + * Size is revealed as part of this call function. + */ + if (rx_msg_sz > MAX_NVM_MSG_LEN) { + dev_err(dev, + "CMD-RCVER NVM: hdr(0x%x) with different sz(%d !=3D %d).\n", + *(u32 *) header, + rx_msg_sz, se_clbk_hdl->rx_msg_sz); + + se_clbk_hdl->rx_msg_sz =3D MAX_NVM_MSG_LEN; + } + se_clbk_hdl->rx_msg_sz =3D rx_msg_sz; + + } else if (header->tag =3D=3D priv->if_defs->rsp_tag) { + se_clbk_hdl =3D &priv->waiting_rsp_clbk_hdl; + dev_dbg(dev, + "Selecting resp waiter for mesg header:0x%x.", + *(u32 *) header); + + if (rx_msg_sz !=3D se_clbk_hdl->rx_msg_sz + && !exception_for_size(priv, header)) { + dev_err(dev, + "Rsp to CMD: hdr(0x%x) with different sz(%d !=3D %d).\n", + *(u32 *) header, + rx_msg_sz, se_clbk_hdl->rx_msg_sz); + + se_clbk_hdl->rx_msg_sz =3D min(rx_msg_sz, se_clbk_hdl->rx_msg_sz); + } + } else { + dev_err(dev, "Failed to select a device for message: %.8x\n", + *((u32 *) header)); + return; + } + + memcpy(se_clbk_hdl->rx_msg, msg, se_clbk_hdl->rx_msg_sz); + + /* Allow user to read */ + complete(&se_clbk_hdl->done); +} + +int se_val_rsp_hdr_n_status(struct se_if_priv *priv, + struct se_api_msg *msg, + uint8_t msg_id, + uint8_t sz, + bool is_base_api) +{ + u32 status; + struct se_msg_hdr *header =3D &msg->header; + + if (header->tag !=3D priv->if_defs->rsp_tag) { + dev_err(priv->dev, + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x !=3D 0x%x)", + msg_id, header->tag, priv->if_defs->rsp_tag); + return -EINVAL; + } + + if (header->command !=3D msg_id) { + dev_err(priv->dev, + "MSG Header: Cmd id mismatch. (0x%x !=3D 0x%x)", + header->command, msg_id); + return -EINVAL; + } + + if (header->size !=3D (sz >> 2)) { + dev_err(priv->dev, + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x !=3D 0x%x)", + msg_id, header->size, (sz >> 2)); + return -EINVAL; + } + + if (is_base_api && (header->ver !=3D priv->if_defs->base_api_ver)) { + dev_err(priv->dev, + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x !=3D 0x%x)", + msg_id, header->ver, priv->if_defs->base_api_ver); + return -EINVAL; + } else if (!is_base_api && header->ver !=3D priv->if_defs->fw_api_ver) { + dev_err(priv->dev, + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x !=3D 0x%x)", + msg_id, header->ver, priv->if_defs->fw_api_ver); + return -EINVAL; + } + + status =3D RES_STATUS(msg->data[0]); + if (status !=3D priv->if_defs->success_tag) { + dev_err(priv->dev, "Command Id[%d], Response Failure =3D 0x%x", + header->command, status); + return -EPERM; + } + + return 0; +} + +int se_save_imem_state(struct se_if_priv *priv, struct se_imem_buf *imem) +{ + int ret; + + /* EXPORT command will save encrypted IMEM to given address, + * so later in resume, IMEM can be restored from the given + * address. + * + * Size must be at least 64 kB. + */ + ret =3D ele_service_swap(priv, + imem->phyaddr, + ELE_IMEM_SIZE, + ELE_IMEM_EXPORT); + if (ret < 0) + dev_err(priv->dev, "Failed to export IMEM\n"); + else + dev_info(priv->dev, + "Exported %d bytes of encrypted IMEM\n", + ret); + + return ret; +} + +int se_restore_imem_state(struct se_if_priv *priv, struct se_imem_buf *ime= m) +{ + struct ele_dev_info s_info; + int ret; + + /* get info from ELE */ + ret =3D ele_get_info(priv, &s_info); + if (ret) { + dev_err(priv->dev, "Failed to get info from ELE.\n"); + return ret; + } + imem->state =3D s_info.d_addn_info.imem_state; + + /* Get IMEM state, if 0xFE then import IMEM */ + if (s_info.d_addn_info.imem_state =3D=3D ELE_IMEM_STATE_BAD) { + /* IMPORT command will restore IMEM from the given + * address, here size is the actual size returned by ELE + * during the export operation + */ + ret =3D ele_service_swap(priv, + imem->phyaddr, + imem->size, + ELE_IMEM_IMPORT); + if (ret) { + dev_err(priv->dev, "Failed to import IMEM\n"); + goto exit; + } + } else + goto exit; + + /* After importing IMEM, check if IMEM state is equal to 0xCA + * to ensure IMEM is fully loaded and + * ELE functionality can be used. + */ + ret =3D ele_get_info(priv, &s_info); + if (ret) { + dev_err(priv->dev, "Failed to get info from ELE.\n"); + goto exit; + } + imem->state =3D s_info.d_addn_info.imem_state; + + if (s_info.d_addn_info.imem_state =3D=3D ELE_IMEM_STATE_OK) + dev_info(priv->dev, "Successfully restored IMEM\n"); + else + dev_err(priv->dev, "Failed to restore IMEM\n"); + +exit: + return ret; +} diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_c= ommon.h new file mode 100644 index 000000000000..3d8b6f83fb9d --- /dev/null +++ b/drivers/firmware/imx/ele_common.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + */ + + +#ifndef __ELE_COMMON_H__ +#define __ELE_COMMON_H__ + +#include "se_ctrl.h" + +#define ELE_SUCCESS_IND 0xD6 + +#define IMX_ELE_FW_DIR "imx/ele/" + +uint32_t se_add_msg_crc(uint32_t *msg, uint32_t msg_len); +int ele_msg_rcv(struct se_if_priv *priv, + struct se_clbk_handle *se_clbk_hdl); +int ele_msg_send(struct se_if_priv *priv, + void *tx_msg, + int tx_msg_sz); +int ele_msg_send_rcv(struct se_if_priv *priv, + void *tx_msg, + int tx_msg_sz, + void *rx_msg, + int exp_rx_msg_sz); +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg); +int se_val_rsp_hdr_n_status(struct se_if_priv *priv, + struct se_api_msg *msg, + uint8_t msg_id, + uint8_t sz, + bool is_base_api); + +/* Fill a command message header with a given command ID and length in byt= es. */ +static inline int se_fill_cmd_msg_hdr(struct se_if_priv *priv, + struct se_msg_hdr *hdr, + u8 cmd, u32 len, + bool is_base_api) +{ + hdr->tag =3D priv->if_defs->cmd_tag; + hdr->ver =3D (is_base_api) ? priv->if_defs->base_api_ver : priv->if_defs-= >fw_api_ver; + hdr->command =3D cmd; + hdr->size =3D len >> 2; + + return 0; +} + +int se_save_imem_state(struct se_if_priv *priv, struct se_imem_buf *imem); +int se_restore_imem_state(struct se_if_priv *priv, struct se_imem_buf *ime= m); + +#endif /*__ELE_COMMON_H__ */ diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c new file mode 100644 index 000000000000..40d815d0ac9b --- /dev/null +++ b/drivers/firmware/imx/se_ctrl.c @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ele_base_msg.h" +#include "ele_common.h" +#include "se_ctrl.h" + +#define MBOX_TX_NAME "tx" +#define MBOX_RX_NAME "rx" +#define SE_TYPE_HSM "hsm" + +struct se_fw_load_info { + const u8 *prim_fw_nm_in_rfs; + const u8 *seco_fw_nm_in_rfs; + struct mutex se_fw_load; + bool is_fw_loaded; + bool handle_susp_resm; + struct se_imem_buf imem; +}; + +struct se_if_node_info { + u8 se_if_id; + u8 se_if_did; + struct se_if_defines if_defs; + u8 *se_name; + u8 *pool_name; + bool soc_register; + bool reserved_dma_ranges; + int (*se_fetch_soc_info)(struct se_if_priv *priv, u16 *soc_rev, u64 *seri= al_num); +}; + +struct se_if_node_info_list { + const u8 num_mu; + const u16 soc_id; + struct se_fw_load_info load_hsm_fw; + const struct se_if_node_info info[]; +}; + +static u16 se_soc_rev; +static struct se_if_node_info_list imx8ulp_info =3D { + .num_mu =3D 1, + .soc_id =3D SOC_ID_OF_IMX8ULP, + .load_hsm_fw =3D { + .prim_fw_nm_in_rfs =3D IMX_ELE_FW_DIR + "mx8ulpa2-ahab-container.img", + .seco_fw_nm_in_rfs =3D IMX_ELE_FW_DIR + "mx8ulpa2ext-ahab-container.img", + .is_fw_loaded =3D false, + .handle_susp_resm =3D true, + .imem =3D { + .state =3D ELE_IMEM_STATE_OK, + }, + }, + .info =3D { + { + .se_if_id =3D 0, + .se_if_did =3D 7, + .if_defs =3D { + .cmd_tag =3D 0x17, + .rsp_tag =3D 0xe1, + .success_tag =3D ELE_SUCCESS_IND, + .base_api_ver =3D MESSAGING_VERSION_6, + .fw_api_ver =3D MESSAGING_VERSION_7, + }, + .se_name =3D SE_TYPE_HSM"1", + .pool_name =3D "sram", + .soc_register =3D true, + .reserved_dma_ranges =3D true, + .se_fetch_soc_info =3D ele_fetch_soc_info, + }, + }, +}; + +static struct se_if_node_info_list imx93_info =3D { + .num_mu =3D 1, + .soc_id =3D SOC_ID_OF_IMX93, + .load_hsm_fw =3D { + .prim_fw_nm_in_rfs =3D NULL, + .seco_fw_nm_in_rfs =3D NULL, + .is_fw_loaded =3D true, + .handle_susp_resm =3D false, + }, + .info =3D { + { + .se_if_id =3D 2, + .se_if_did =3D 3, + .if_defs =3D { + .cmd_tag =3D 0x17, + .rsp_tag =3D 0xe1, + .success_tag =3D ELE_SUCCESS_IND, + .base_api_ver =3D MESSAGING_VERSION_6, + .fw_api_ver =3D MESSAGING_VERSION_7, + }, + .se_name =3D SE_TYPE_HSM"1", + .reserved_dma_ranges =3D true, + .soc_register =3D true, + }, + }, +}; + +static const struct of_device_id se_match[] =3D { + { .compatible =3D "fsl,imx8ulp-se", .data =3D (void *)&imx8ulp_info}, + { .compatible =3D "fsl,imx93-se", .data =3D (void *)&imx93_info}, + {}, +}; + +static const struct se_if_node_info + *get_se_if_node_info(const struct se_if_node_info_list *info_list, + const u32 idx) +{ + return &info_list->info[idx]; +} + +static int se_soc_info(struct se_if_priv *priv) +{ + const struct se_if_node_info *info; + struct se_if_node_info_list *info_list; + struct soc_device_attribute *attr; + struct soc_device *sdev; + u64 serial_num; + int err =3D 0; + + info =3D container_of(priv->if_defs, + typeof(*info), + if_defs); + info_list =3D container_of(info, + typeof(*info_list), + info[info->se_if_id]); + + /* This function should be called once. + * Check if the se_soc_rev is zero to continue. + */ + if (se_soc_rev) + return err; + + if (info->se_fetch_soc_info) { + err =3D info->se_fetch_soc_info(priv, &se_soc_rev, &serial_num); + if (err < 0) { + dev_err(priv->dev, "Failed to fetch SoC Info."); + return err; + } + } else { + dev_err(priv->dev, "Failed to fetch SoC revision."); + if (info->soc_register) + dev_err(priv->dev, "Failed to do SoC registration."); + err =3D -EINVAL; + return err; + } + + if (!info->soc_register) + return 0; + + attr =3D devm_kzalloc(priv->dev, sizeof(*attr), GFP_KERNEL); + if (!attr) + return -ENOMEM; + + if (FIELD_GET(DEV_GETINFO_MIN_VER_MASK, se_soc_rev)) + attr->revision =3D devm_kasprintf(priv->dev, GFP_KERNEL, "%x.%x", + FIELD_GET(DEV_GETINFO_MIN_VER_MASK, + se_soc_rev), + FIELD_GET(DEV_GETINFO_MAJ_VER_MASK, + se_soc_rev)); + else + attr->revision =3D devm_kasprintf(priv->dev, GFP_KERNEL, "%x", + FIELD_GET(DEV_GETINFO_MAJ_VER_MASK, + se_soc_rev)); + + switch (info_list->soc_id) { + case SOC_ID_OF_IMX8ULP: + attr->soc_id =3D devm_kasprintf(priv->dev, GFP_KERNEL, + "i.MX8ULP"); + break; + case SOC_ID_OF_IMX93: + attr->soc_id =3D devm_kasprintf(priv->dev, GFP_KERNEL, + "i.MX93"); + break; + } + + err =3D of_property_read_string(of_root, "model", + &attr->machine); + if (err) + return -EINVAL; + + attr->family =3D devm_kasprintf(priv->dev, GFP_KERNEL, "Freescale i.MX"); + + attr->serial_number + =3D devm_kasprintf(priv->dev, GFP_KERNEL, "%016llX", serial_num); + + sdev =3D soc_device_register(attr); + if (IS_ERR(sdev)) + return PTR_ERR(sdev); + + return 0; +} + +static struct se_fw_load_info *get_load_fw_instance(struct se_if_priv *pri= v) +{ + const struct se_if_node_info *info =3D container_of(priv->if_defs, + typeof(*info), + if_defs); + struct se_if_node_info_list *info_list; + struct se_fw_load_info *load_fw =3D NULL; + + info_list =3D container_of(info, + typeof(*info_list), + info[info->se_if_id]); + + if (!memcmp(SE_TYPE_HSM, info->se_name, strlen(SE_TYPE_HSM))) + load_fw =3D &info_list->load_hsm_fw; + else + dev_err(priv->dev, "Invalid load fw configuration."); + + return load_fw; +} + +static int se_load_firmware(struct se_if_priv *priv) +{ + struct se_fw_load_info *load_fw =3D get_load_fw_instance(priv); + const struct firmware *fw; + phys_addr_t se_fw_phyaddr; + const u8 *se_img_file_to_load; + u8 *se_fw_buf; + int ret; + + guard(mutex)(&load_fw->se_fw_load); + if (load_fw->is_fw_loaded) + return 0; + + se_img_file_to_load =3D load_fw->seco_fw_nm_in_rfs; + if (load_fw->prim_fw_nm_in_rfs) { + /* allocate buffer where SE store encrypted IMEM */ + load_fw->imem.buf =3D dmam_alloc_coherent(priv->dev, ELE_IMEM_SIZE, + &load_fw->imem.phyaddr, + GFP_KERNEL); + if (!load_fw->imem.buf) { + dev_err(priv->dev, + "dmam-alloc-failed: To store encr-IMEM.\n"); + ret =3D -ENOMEM; + goto exit; + } + if (load_fw->imem.state =3D=3D ELE_IMEM_STATE_BAD) + se_img_file_to_load + =3D load_fw->prim_fw_nm_in_rfs; + } + + do { + ret =3D request_firmware(&fw, se_img_file_to_load, priv->dev); + if (ret) + goto exit; + + dev_info(priv->dev, "loading firmware %s\n", se_img_file_to_load); + + /* allocate buffer to store the SE FW */ + se_fw_buf =3D dma_alloc_coherent(priv->dev, fw->size, + &se_fw_phyaddr, GFP_KERNEL); + if (!se_fw_buf) { + ret =3D -ENOMEM; + goto exit; + } + + memcpy(se_fw_buf, fw->data, fw->size); + ret =3D ele_fw_authenticate(priv, se_fw_phyaddr); + if (ret < 0) { + dev_err(priv->dev, + "Error %pe: Authenticate & load SE firmware %s.\n", + ERR_PTR(ret), + se_img_file_to_load); + ret =3D -EPERM; + } + + dma_free_coherent(priv->dev, + fw->size, + se_fw_buf, + se_fw_phyaddr); + + release_firmware(fw); + + if (!ret && load_fw->imem.state =3D=3D ELE_IMEM_STATE_BAD && + se_img_file_to_load =3D=3D load_fw->prim_fw_nm_in_rfs) + se_img_file_to_load =3D load_fw->seco_fw_nm_in_rfs; + else + se_img_file_to_load =3D NULL; + + } while (se_img_file_to_load); + + if (!ret) + load_fw->is_fw_loaded =3D true; + +exit: + return ret; +} + +/* interface for managed res to free a mailbox channel */ +static void if_mbox_free_channel(void *mbox_chan) +{ + mbox_free_channel(mbox_chan); +} + +static int se_if_request_channel(struct device *dev, + struct mbox_chan **chan, + struct mbox_client *cl, + const char *name) +{ + struct mbox_chan *t_chan; + int ret =3D 0; + + t_chan =3D mbox_request_channel_byname(cl, name); + if (IS_ERR(t_chan)) { + ret =3D PTR_ERR(t_chan); + return dev_err_probe(dev, ret, + "Failed to request %s channel.", name); + } + + ret =3D devm_add_action(dev, if_mbox_free_channel, t_chan); + if (ret) { + dev_err(dev, "failed to add devm removal of mbox %s\n", name); + goto exit; + } + + *chan =3D t_chan; + +exit: + return ret; +} + +static void se_if_probe_cleanup(void *plat_dev) +{ + struct platform_device *pdev =3D plat_dev; + struct device *dev =3D &pdev->dev; + struct se_fw_load_info *load_fw; + struct se_if_priv *priv; + + priv =3D dev_get_drvdata(dev); + load_fw =3D get_load_fw_instance(priv); + + /* In se_if_request_channel(), passed the clean-up functional + * pointer reference as action to devm_add_action(). + * No need to free the mbox channels here. + */ + + /* free the buffer in se remove, previously allocated + * in se probe to store encrypted IMEM + */ + if (load_fw && load_fw->imem.buf) { + dmam_free_coherent(dev, + ELE_IMEM_SIZE, + load_fw->imem.buf, + load_fw->imem.phyaddr); + load_fw->imem.buf =3D NULL; + } + + /* No need to check, if reserved memory is allocated + * before calling for its release. Or clearing the + * un-set bit. + */ + of_reserved_mem_device_release(dev); +} + +static int se_if_probe(struct platform_device *pdev) +{ + const struct se_if_node_info_list *info_list; + const struct se_if_node_info *info; + struct device *dev =3D &pdev->dev; + struct se_fw_load_info *load_fw; + struct se_if_priv *priv; + u32 idx; + int ret; + + idx =3D GET_IDX_FROM_DEV_NODE_NAME(dev->of_node); + info_list =3D device_get_match_data(dev); + if (idx >=3D info_list->num_mu) { + dev_err(dev, + "Incorrect node name :%s\n", + dev->of_node->full_name); + dev_err(dev, + "%s-, acceptable index range is 0..%d\n", + dev->of_node->name, + info_list->num_mu - 1); + ret =3D -EINVAL; + return ret; + } + + info =3D get_se_if_node_info(info_list, idx); + if (!info) { + ret =3D -EINVAL; + goto exit; + } + + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret =3D -ENOMEM; + goto exit; + } + + priv->dev =3D dev; + priv->if_defs =3D &info->if_defs; + dev_set_drvdata(dev, priv); + + ret =3D devm_add_action(dev, se_if_probe_cleanup, pdev); + if (ret) + goto exit; + + + /* Mailbox client configuration */ + priv->se_mb_cl.dev =3D dev; + priv->se_mb_cl.tx_block =3D false; + priv->se_mb_cl.knows_txdone =3D true; + priv->se_mb_cl.rx_callback =3D se_if_rx_callback; + + ret =3D se_if_request_channel(dev, &priv->tx_chan, + &priv->se_mb_cl, MBOX_TX_NAME); + if (ret) + goto exit; + + ret =3D se_if_request_channel(dev, &priv->rx_chan, + &priv->se_mb_cl, MBOX_RX_NAME); + if (ret) + goto exit; + + mutex_init(&priv->se_if_cmd_lock); + + init_completion(&priv->waiting_rsp_clbk_hdl.done); + init_completion(&priv->cmd_receiver_clbk_hdl.done); + + if (info->pool_name) { + priv->mem_pool =3D of_gen_pool_get(dev->of_node, + info->pool_name, 0); + if (!priv->mem_pool) { + dev_err(dev, + "Unable to get sram pool =3D %s\n", + info->pool_name); + goto exit; + } + } + + if (info->reserved_dma_ranges) { + ret =3D of_reserved_mem_device_init(dev); + if (ret) { + dev_err(dev, + "failed to init reserved memory region %d\n", + ret); + goto exit; + } + } + + ret =3D se_soc_info(priv); + if (ret) { + dev_err(dev, + "failed[%pe] to fetch SoC Info\n", ERR_PTR(ret)); + goto exit; + } + + load_fw =3D get_load_fw_instance(priv); + /* By default, there is no pending FW to be loaded.*/ + if (load_fw->is_fw_loaded) { + mutex_init(&load_fw->se_fw_load); + ret =3D se_load_firmware(priv); + if (ret) + dev_warn(dev, "Failed to load firmware."); + ret =3D 0; + } + dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.= \n", + info->se_name); + return ret; + +exit: + /* if execution control reaches here, if probe fails. + */ + return dev_err_probe(dev, ret, "%s: Probe failed.", __func__); + + return ret; +} + +static void se_if_remove(struct platform_device *pdev) +{ + se_if_probe_cleanup(pdev); +} + +static int se_suspend(struct device *dev) +{ + struct se_if_priv *priv =3D dev_get_drvdata(dev); + struct se_fw_load_info *load_fw; + int ret =3D 0; + + load_fw =3D get_load_fw_instance(priv); + + if (load_fw->handle_susp_resm) { + ret =3D se_save_imem_state(priv, &load_fw->imem); + if (ret < 0) + goto exit; + load_fw->imem.size =3D ret; + } +exit: + return ret; +} + +static int se_resume(struct device *dev) +{ + struct se_if_priv *priv =3D dev_get_drvdata(dev); + struct se_fw_load_info *load_fw; + + load_fw =3D get_load_fw_instance(priv); + + if (load_fw->handle_susp_resm) + se_restore_imem_state(priv, &load_fw->imem); + + return 0; +} + +static const struct dev_pm_ops se_pm =3D { + RUNTIME_PM_OPS(se_suspend, se_resume, NULL) +}; + +static struct platform_driver se_driver =3D { + .driver =3D { + .name =3D "fsl-se-fw", + .of_match_table =3D se_match, + .pm =3D &se_pm, + }, + .probe =3D se_if_probe, + .remove =3D se_if_remove, +}; +MODULE_DEVICE_TABLE(of, se_match); + +module_platform_driver(se_driver); +MODULE_AUTHOR("Pankaj Gupta "); +MODULE_DESCRIPTION("iMX Secure Enclave Driver."); +MODULE_LICENSE("GPL"); diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h new file mode 100644 index 000000000000..de0d4a1bcb9e --- /dev/null +++ b/drivers/firmware/imx/se_ctrl.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + */ + +#ifndef SE_MU_H +#define SE_MU_H + +#include +#include +#include + +#define MAX_FW_LOAD_RETRIES 50 + +#define RES_STATUS(x) FIELD_GET(0x000000ff, x) +#define MAX_NVM_MSG_LEN (256) +#define MESSAGING_VERSION_6 0x6 +#define MESSAGING_VERSION_7 0x7 +#define NODE_NAME "secure-enclave" + +#define GET_ASCII_TO_U8(diff, tens_chr, ones_chr) \ + ((diff > 2) ? (((tens_chr - '0') * 10) + (ones_chr - '0')) :\ + (tens_chr - '0')) + +#define GET_IDX_FROM_DEV_NODE_NAME(dev_of_node) \ + ((strlen(dev_of_node->full_name) > strlen(NODE_NAME)) ?\ + GET_ASCII_TO_U8((strlen(dev_of_node->full_name) - strlen(NODE_NAME)),\ + dev_of_node->full_name[strlen(NODE_NAME) + 1], \ + dev_of_node->full_name[strlen(NODE_NAME) + 2]) : 0) + +struct se_clbk_handle { + struct completion done; + bool signal_rcvd; + atomic_t pending_hdr; + u32 rx_msg_sz; + /* Assignment of the rx_msg buffer to held till the + * received content as part callback function, is copied. + */ + struct se_api_msg *rx_msg; +}; + +struct se_imem_buf { + u8 *buf; + phys_addr_t phyaddr; + u32 size; + u32 state; +}; + +/* Header of the messages exchange with the EdgeLock Enclave */ +struct se_msg_hdr { + u8 ver; + u8 size; + u8 command; + u8 tag; +} __packed; + +#define SE_MU_HDR_SZ 4 + +struct se_api_msg { + struct se_msg_hdr header; + u32 data[]; +}; + +struct se_if_defines { + const void *info; + u8 cmd_tag; + u8 rsp_tag; + u8 success_tag; + u8 base_api_ver; + u8 fw_api_ver; +}; + +struct se_if_priv { + struct device *dev; + + struct se_clbk_handle cmd_receiver_clbk_hdl; + /* Update to the waiting_rsp_dev, to be protected + * under se_if_cmd_lock. + */ + struct se_clbk_handle waiting_rsp_clbk_hdl; + /* + * prevent new command to be sent on the se interface while previous + * command is still processing. (response is awaited) + */ + struct mutex se_if_cmd_lock; + + struct mbox_client se_mb_cl; + struct mbox_chan *tx_chan, *rx_chan; + + struct gen_pool *mem_pool; + const struct se_if_defines *if_defs; +}; + +#endif diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/i= mx/se_api.h new file mode 100644 index 000000000000..c47f84906837 --- /dev/null +++ b/include/linux/firmware/imx/se_api.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + */ + +#ifndef __SE_API_H__ +#define __SE_API_H__ + +#include + +#define SOC_ID_OF_IMX8ULP 0x084D +#define SOC_ID_OF_IMX93 0x9300 + +#endif /* __SE_API_H__ */ --=20 2.34.1 From nobody Tue Nov 26 17:19:49 2024 Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2045.outbound.protection.outlook.com [40.107.104.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F184F213EE7; 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ABI documentation for the NXP secure-enclave driver. User-space library using this driver: - i.MX Secure Enclave library: -- URL: https://github.com/nxp-imx/imx-secure-enclave.git, - i.MX Secure Middle-Ware: -- URL: https://github.com/nxp-imx/imx-smw.git Signed-off-by: Pankaj Gupta --- Documentation/ABI/testing/se-cdev | 43 ++ drivers/firmware/imx/ele_base_msg.c | 8 +- drivers/firmware/imx/ele_common.c | 39 +- drivers/firmware/imx/ele_common.h | 6 +- drivers/firmware/imx/se_ctrl.c | 779 ++++++++++++++++++++++++++++++++= ++++ drivers/firmware/imx/se_ctrl.h | 42 +- include/uapi/linux/se_ioctl.h | 94 +++++ 7 files changed, 990 insertions(+), 21 deletions(-) diff --git a/Documentation/ABI/testing/se-cdev b/Documentation/ABI/testing/= se-cdev new file mode 100644 index 000000000000..3451c909ccc4 --- /dev/null +++ b/Documentation/ABI/testing/se-cdev @@ -0,0 +1,43 @@ +What: /dev/_mu[0-9]+_ch[0-9]+ +Date: May 2024 +KernelVersion: 6.8 +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com +Description: + NXP offers multiple hardware IP(s) for secure enclaves like EdgeLock- + Enclave(ELE), SECO. The character device file descriptors + /dev/_mu*_ch* are the interface between userspace NXP's secure- + enclave shared library and the kernel driver. + + The ioctl(2)-based ABI is defined and documented in + [include]. + ioctl(s) are used primarily for: + - shared memory management + - allocation of I/O buffers + - getting mu info + - setting a dev-ctx as receiver to receive all the commands from FW + - getting SoC info + - send command and receive command response + + The following file operations are supported: + + open(2) + Currently the only useful flags are O_RDWR. + + read(2) + Every read() from the opened character device context is waiting on + wait_event_interruptible, that gets set by the registered mailbox call= back + function, indicating a message received from the firmware on message- + unit. + + write(2) + Every write() to the opened character device context needs to acquire + mailbox_lock before sending message on to the message unit. + + close(2) + Stops and frees up the I/O contexts that were associated + with the file descriptor. + +Users: https://github.com/nxp-imx/imx-secure-enclave.git, + https://github.com/nxp-imx/imx-smw.git + crypto/skcipher, + drivers/nvmem/imx-ocotp-ele.c diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele= _base_msg.c index 53c83eddd52a..329badcc3d14 100644 --- a/drivers/firmware/imx/ele_base_msg.c +++ b/drivers/firmware/imx/ele_base_msg.c @@ -67,7 +67,7 @@ int ele_get_info(struct se_if_priv *priv, struct ele_dev_= info *s_info) tx_msg->data[0] =3D upper_32_bits(get_info_addr); tx_msg->data[1] =3D lower_32_bits(get_info_addr); tx_msg->data[2] =3D sizeof(*s_info); - ret =3D ele_msg_send_rcv(priv, + ret =3D ele_msg_send_rcv(priv->priv_dev_ctx, tx_msg, ELE_GET_INFO_REQ_MSG_SZ, rx_msg, @@ -145,7 +145,7 @@ int ele_ping(struct se_if_priv *priv) goto exit; } =20 - ret =3D ele_msg_send_rcv(priv, + ret =3D ele_msg_send_rcv(priv->priv_dev_ctx, tx_msg, ELE_PING_REQ_SZ, rx_msg, @@ -200,7 +200,7 @@ int ele_service_swap(struct se_if_priv *priv, tx_msg->data[3] =3D lower_32_bits(addr); tx_msg->data[4] =3D se_add_msg_crc((uint32_t *)&tx_msg[0], ELE_SERVICE_SWAP_REQ_MSG_SZ); - ret =3D ele_msg_send_rcv(priv, + ret =3D ele_msg_send_rcv(priv->priv_dev_ctx, tx_msg, ELE_SERVICE_SWAP_REQ_MSG_SZ, rx_msg, @@ -261,7 +261,7 @@ int ele_fw_authenticate(struct se_if_priv *priv, phys_a= ddr_t addr) tx_msg->data[0] =3D lower_32_bits(addr); tx_msg->data[2] =3D addr; =20 - ret =3D ele_msg_send_rcv(priv, + ret =3D ele_msg_send_rcv(priv->priv_dev_ctx, tx_msg, ELE_FW_AUTH_REQ_SZ, rx_msg, diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_c= ommon.c index f7c760bbc7a3..97f34e4e5d2c 100644 --- a/drivers/firmware/imx/ele_common.c +++ b/drivers/firmware/imx/ele_common.c @@ -18,9 +18,10 @@ u32 se_add_msg_crc(u32 *msg, u32 msg_len) return crc; } =20 -int ele_msg_rcv(struct se_if_priv *priv, +int ele_msg_rcv(struct se_if_device_ctx *dev_ctx, struct se_clbk_handle *se_clbk_hdl) { + struct se_if_priv *priv =3D dev_ctx->priv; int err =3D 0; =20 do { @@ -31,12 +32,13 @@ int ele_msg_rcv(struct se_if_priv *priv, */ err =3D wait_for_completion_interruptible(&se_clbk_hdl->done); if (err =3D=3D -ERESTARTSYS) { - if (priv->waiting_rsp_clbk_hdl.rx_msg) { + if (priv->waiting_rsp_clbk_hdl.dev_ctx) { priv->waiting_rsp_clbk_hdl.signal_rcvd =3D true; continue; } dev_err(priv->dev, - "Err[0x%x]:Interrupted by signal.\n", + "%s: Err[0x%x]:Interrupted by signal.\n", + se_clbk_hdl->dev_ctx->devname, err); err =3D -EINTR; break; @@ -46,10 +48,11 @@ int ele_msg_rcv(struct se_if_priv *priv, return err ? err : se_clbk_hdl->rx_msg_sz; } =20 -int ele_msg_send(struct se_if_priv *priv, +int ele_msg_send(struct se_if_device_ctx *dev_ctx, void *tx_msg, int tx_msg_sz) { + struct se_if_priv *priv =3D dev_ctx->priv; struct se_msg_hdr *header; int err; =20 @@ -62,7 +65,8 @@ int ele_msg_send(struct se_if_priv *priv, if (header->size << 2 !=3D tx_msg_sz) { err =3D -EINVAL; dev_err(priv->dev, - "User buf hdr: 0x%x, sz mismatced with input-sz (%d !=3D %d).", + "%s: User buf hdr: 0x%x, sz mismatced with input-sz (%d !=3D %d).", + dev_ctx->devname, *(u32 *)header, header->size << 2, tx_msg_sz); goto exit; @@ -70,7 +74,9 @@ int ele_msg_send(struct se_if_priv *priv, =20 err =3D mbox_send_message(priv->tx_chan, tx_msg); if (err < 0) { - dev_err(priv->dev, "Error: mbox_send_message failure.\n"); + dev_err(priv->dev, + "%s: Error: mbox_send_message failure.", + dev_ctx->devname); return err; } err =3D tx_msg_sz; @@ -80,29 +86,32 @@ int ele_msg_send(struct se_if_priv *priv, } =20 /* API used for send/receive blocking call. */ -int ele_msg_send_rcv(struct se_if_priv *priv, +int ele_msg_send_rcv(struct se_if_device_ctx *dev_ctx, void *tx_msg, int tx_msg_sz, void *rx_msg, int exp_rx_msg_sz) { int err; + struct se_if_priv *priv =3D dev_ctx->priv; =20 guard(mutex)(&priv->se_if_cmd_lock); =20 + priv->waiting_rsp_clbk_hdl.dev_ctx =3D dev_ctx; priv->waiting_rsp_clbk_hdl.rx_msg_sz =3D exp_rx_msg_sz; priv->waiting_rsp_clbk_hdl.rx_msg =3D rx_msg; =20 - err =3D ele_msg_send(priv, tx_msg, tx_msg_sz); + err =3D ele_msg_send(dev_ctx, tx_msg, tx_msg_sz); if (err < 0) goto exit; =20 - err =3D ele_msg_rcv(priv, &priv->waiting_rsp_clbk_hdl); + err =3D ele_msg_rcv(dev_ctx, &priv->waiting_rsp_clbk_hdl); =20 if (priv->waiting_rsp_clbk_hdl.signal_rcvd) { err =3D -EINTR; priv->waiting_rsp_clbk_hdl.signal_rcvd =3D false; } + priv->waiting_rsp_clbk_hdl.dev_ctx =3D NULL; =20 exit: return err; @@ -149,7 +158,8 @@ void se_if_rx_callback(struct mbox_client *mbox_cl, voi= d *msg) if (header->tag =3D=3D priv->if_defs->cmd_tag) { se_clbk_hdl =3D &priv->cmd_receiver_clbk_hdl; dev_dbg(dev, - "Selecting cmd receiver for mesg header:0x%x.", + "Selecting cmd receiver:%s for mesg header:0x%x.", + se_clbk_hdl->dev_ctx->devname, *(u32 *) header); =20 /* Pre-allocated buffer of MAX_NVM_MSG_LEN @@ -158,7 +168,8 @@ void se_if_rx_callback(struct mbox_client *mbox_cl, voi= d *msg) */ if (rx_msg_sz > MAX_NVM_MSG_LEN) { dev_err(dev, - "CMD-RCVER NVM: hdr(0x%x) with different sz(%d !=3D %d).\n", + "%s: CMD-RCVER NVM: hdr(0x%x) with different sz(%d !=3D %d).\n", + se_clbk_hdl->dev_ctx->devname, *(u32 *) header, rx_msg_sz, se_clbk_hdl->rx_msg_sz); =20 @@ -169,13 +180,15 @@ void se_if_rx_callback(struct mbox_client *mbox_cl, v= oid *msg) } else if (header->tag =3D=3D priv->if_defs->rsp_tag) { se_clbk_hdl =3D &priv->waiting_rsp_clbk_hdl; dev_dbg(dev, - "Selecting resp waiter for mesg header:0x%x.", + "Selecting resp waiter:%s for mesg header:0x%x.", + se_clbk_hdl->dev_ctx->devname, *(u32 *) header); =20 if (rx_msg_sz !=3D se_clbk_hdl->rx_msg_sz && !exception_for_size(priv, header)) { dev_err(dev, - "Rsp to CMD: hdr(0x%x) with different sz(%d !=3D %d).\n", + "%s: Rsp to CMD: hdr(0x%x) with different sz(%d !=3D %d).\n", + se_clbk_hdl->dev_ctx->devname, *(u32 *) header, rx_msg_sz, se_clbk_hdl->rx_msg_sz); =20 diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_c= ommon.h index 3d8b6f83fb9d..9bded800c103 100644 --- a/drivers/firmware/imx/ele_common.h +++ b/drivers/firmware/imx/ele_common.h @@ -14,12 +14,12 @@ #define IMX_ELE_FW_DIR "imx/ele/" =20 uint32_t se_add_msg_crc(uint32_t *msg, uint32_t msg_len); -int ele_msg_rcv(struct se_if_priv *priv, +int ele_msg_rcv(struct se_if_device_ctx *dev_ctx, struct se_clbk_handle *se_clbk_hdl); -int ele_msg_send(struct se_if_priv *priv, +int ele_msg_send(struct se_if_device_ctx *dev_ctx, void *tx_msg, int tx_msg_sz); -int ele_msg_send_rcv(struct se_if_priv *priv, +int ele_msg_send_rcv(struct se_if_device_ctx *dev_ctx, void *tx_msg, int tx_msg_sz, void *rx_msg, diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c index 40d815d0ac9b..f41c6441eac1 100644 --- a/drivers/firmware/imx/se_ctrl.c +++ b/drivers/firmware/imx/se_ctrl.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 #include "ele_base_msg.h" #include "ele_common.h" @@ -313,6 +314,762 @@ static int se_load_firmware(struct se_if_priv *priv) return ret; } =20 +static int init_se_shared_mem(struct se_if_device_ctx *dev_ctx) +{ + struct se_shared_mem_mgmt_info *se_shared_mem_mgmt =3D &dev_ctx->se_share= d_mem_mgmt; + struct se_if_priv *priv =3D dev_ctx->priv; + + INIT_LIST_HEAD(&se_shared_mem_mgmt->pending_out); + INIT_LIST_HEAD(&se_shared_mem_mgmt->pending_in); + + /* + * Allocate some memory for data exchanges with S40x. + * This will be used for data not requiring secure memory. + */ + se_shared_mem_mgmt->non_secure_mem.ptr + =3D dma_alloc_coherent(priv->dev, + MAX_DATA_SIZE_PER_USER, + &se_shared_mem_mgmt->non_secure_mem.dma_addr, + GFP_KERNEL); + if (!se_shared_mem_mgmt->non_secure_mem.ptr) + return -ENOMEM; + + se_shared_mem_mgmt->non_secure_mem.size =3D MAX_DATA_SIZE_PER_USER; + se_shared_mem_mgmt->non_secure_mem.pos =3D 0; + + return 0; +} + +static void cleanup_se_shared_mem(struct se_if_device_ctx *dev_ctx) +{ + struct se_shared_mem_mgmt_info *se_shared_mem_mgmt =3D &dev_ctx->se_share= d_mem_mgmt; + struct se_if_priv *priv =3D dev_ctx->priv; + + /* Unmap secure memory shared buffer. */ + if (se_shared_mem_mgmt->secure_mem.ptr) + devm_iounmap(priv->dev, + (void __iomem *)se_shared_mem_mgmt->secure_mem.ptr); + + se_shared_mem_mgmt->secure_mem.ptr =3D NULL; + se_shared_mem_mgmt->secure_mem.dma_addr =3D 0; + se_shared_mem_mgmt->secure_mem.size =3D 0; + se_shared_mem_mgmt->secure_mem.pos =3D 0; + + /* Free non-secure shared buffer. */ + dma_free_coherent(priv->dev, MAX_DATA_SIZE_PER_USER, + se_shared_mem_mgmt->non_secure_mem.ptr, + se_shared_mem_mgmt->non_secure_mem.dma_addr); + + se_shared_mem_mgmt->non_secure_mem.ptr =3D NULL; + se_shared_mem_mgmt->non_secure_mem.dma_addr =3D 0; + se_shared_mem_mgmt->non_secure_mem.size =3D 0; + se_shared_mem_mgmt->non_secure_mem.pos =3D 0; +} + +/* Need to copy the output data to user-device context. + */ +static int se_dev_ctx_cpy_out_data(struct se_if_device_ctx *dev_ctx) +{ + struct se_shared_mem_mgmt_info *se_shared_mem_mgmt =3D &dev_ctx->se_share= d_mem_mgmt; + struct se_if_priv *priv =3D dev_ctx->priv; + struct se_buf_desc *b_desc, *temp; + bool do_cpy =3D true; + + list_for_each_entry_safe(b_desc, temp, &se_shared_mem_mgmt->pending_out, = link) { + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr && do_cpy) { + + dev_dbg(priv->dev, + "Copying output data to user."); + if (do_cpy && copy_to_user(b_desc->usr_buf_ptr, + b_desc->shared_buf_ptr, + b_desc->size)) { + dev_err(priv->dev, + "Failure copying output data to user."); + do_cpy =3D false; + } + } + + if (b_desc->shared_buf_ptr) + memset(b_desc->shared_buf_ptr, 0, b_desc->size); + + list_del(&b_desc->link); + kfree(b_desc); + } + + return do_cpy ? 0 : -EFAULT; +} + +/* + * Clean the used Shared Memory space, + * whether its Input Data copied from user buffers, or + * Data received from FW. + */ +static void se_dev_ctx_shared_mem_cleanup(struct se_if_device_ctx *dev_ctx) +{ + struct se_shared_mem_mgmt_info *se_shared_mem_mgmt =3D &dev_ctx->se_share= d_mem_mgmt; + struct list_head *pending_lists[] =3D {&se_shared_mem_mgmt->pending_in, + &se_shared_mem_mgmt->pending_out}; + struct se_buf_desc *b_desc, *temp; + int i; + + for (i =3D 0; i < 2; i++) { + list_for_each_entry_safe(b_desc, temp, + pending_lists[i], link) { + + if (b_desc->shared_buf_ptr) + memset(b_desc->shared_buf_ptr, 0, b_desc->size); + + list_del(&b_desc->link); + kfree(b_desc); + } + } + se_shared_mem_mgmt->secure_mem.pos =3D 0; + se_shared_mem_mgmt->non_secure_mem.pos =3D 0; +} + +static int add_b_desc_to_pending_list(void *shared_ptr_with_pos, + struct se_ioctl_setup_iobuf *io, + struct se_if_device_ctx *dev_ctx) +{ + struct se_shared_mem_mgmt_info *se_shared_mem_mgmt =3D &dev_ctx->se_share= d_mem_mgmt; + struct se_buf_desc *b_desc =3D NULL; + + b_desc =3D kzalloc(sizeof(*b_desc), GFP_KERNEL); + if (!b_desc) + return -ENOMEM; + + b_desc->shared_buf_ptr =3D shared_ptr_with_pos; + b_desc->usr_buf_ptr =3D io->user_buf; + b_desc->size =3D io->length; + + if (io->flags & SE_IO_BUF_FLAGS_IS_INPUT) { + /* + * buffer is input: + * add an entry in the "pending input buffers" list so + * that copied data can be cleaned from shared memory + * later. + */ + list_add_tail(&b_desc->link, &se_shared_mem_mgmt->pending_in); + } else { + /* + * buffer is output: + * add an entry in the "pending out buffers" list so data + * can be copied to user space when receiving Secure-Enclave + * response. + */ + list_add_tail(&b_desc->link, &se_shared_mem_mgmt->pending_out); + } + + return 0; +} + +/* interface for managed res to unregister a character device */ +static void if_misc_deregister(void *miscdevice) +{ + misc_deregister(miscdevice); +} + +static int init_device_context(struct se_if_priv *priv, int ch_id, + struct se_if_device_ctx **new_dev_ctx, + const struct file_operations *se_if_fops) +{ + const struct se_if_node_info *info =3D container_of(priv->if_defs, + typeof(*info), + if_defs); + struct se_if_device_ctx *dev_ctx; + int ret =3D 0; + + if (ch_id) + dev_ctx =3D kzalloc(sizeof(*dev_ctx), GFP_KERNEL); + else + dev_ctx =3D devm_kzalloc(priv->dev, sizeof(*dev_ctx), GFP_KERNEL); + + if (!dev_ctx) { + ret =3D -ENOMEM; + return ret; + } + + dev_ctx->priv =3D priv; + + if (ch_id) + dev_ctx->devname =3D kasprintf(GFP_KERNEL, "%s_ch%d", + info->se_name, ch_id); + else + dev_ctx->devname =3D devm_kasprintf(priv->dev, + GFP_KERNEL, "%s_ch%d", + info->se_name, ch_id); + if (!dev_ctx->devname) { + ret =3D -ENOMEM; + if (ch_id) + kfree(dev_ctx); + + return ret; + } + + mutex_init(&dev_ctx->fops_lock); + + *new_dev_ctx =3D dev_ctx; + + if (ch_id) { + list_add_tail(&dev_ctx->link, &priv->dev_ctx_list); + priv->active_devctx_count++; + + ret =3D init_se_shared_mem(dev_ctx); + if (ret < 0) { + kfree(dev_ctx->devname); + kfree(dev_ctx); + *new_dev_ctx =3D NULL; + return ret; + } + + return ret; + } + + /* Only for ch_id =3D 0: + * - register the misc device. + * - add action + */ + dev_ctx->miscdev =3D devm_kzalloc(priv->dev, sizeof(*dev_ctx->miscdev), G= FP_KERNEL); + if (!dev_ctx->miscdev) { + ret =3D -ENOMEM; + *new_dev_ctx =3D NULL; + return ret; + } + + dev_ctx->miscdev->name =3D dev_ctx->devname; + dev_ctx->miscdev->minor =3D MISC_DYNAMIC_MINOR; + dev_ctx->miscdev->fops =3D se_if_fops; + dev_ctx->miscdev->parent =3D priv->dev; + ret =3D misc_register(dev_ctx->miscdev); + if (ret) { + dev_err(priv->dev, "failed to register misc device %d\n", + ret); + return ret; + } + + ret =3D devm_add_action(priv->dev, if_misc_deregister, + dev_ctx->miscdev); + if (ret) { + dev_err(priv->dev, + "failed[%d] to add action to the misc-dev\n", + ret); + misc_deregister(dev_ctx->miscdev); + } + + return ret; +} + +static int se_ioctl_cmd_snd_rcv_rsp_handler(struct se_if_device_ctx *dev_c= tx, + u64 arg) +{ + const struct se_if_node_info *info =3D container_of(dev_ctx->priv->if_def= s, + typeof(*info), + if_defs); + struct se_ioctl_cmd_snd_rcv_rsp_info cmd_snd_rcv_rsp_info; + struct se_if_node_info_list *info_list + =3D container_of(info, + typeof(*info_list), + info[info->se_if_id]); + struct se_if_priv *priv =3D dev_ctx->priv; + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_api_msg *rx_msg __free(kfree) =3D NULL; + int err =3D 0; + + if (copy_from_user(&cmd_snd_rcv_rsp_info, (u8 __user *)arg, + sizeof(cmd_snd_rcv_rsp_info))) { + dev_err(priv->dev, + "%s: Failed to copy cmd_snd_rcv_rsp_info from user\n", + dev_ctx->devname); + err =3D -EFAULT; + goto exit; + } + + if (cmd_snd_rcv_rsp_info.tx_buf_sz < SE_MU_HDR_SZ) { + dev_err(priv->dev, + "%s: User buffer too small(%d < %d)\n", + dev_ctx->devname, + cmd_snd_rcv_rsp_info.tx_buf_sz, + SE_MU_HDR_SZ); + err =3D -ENOSPC; + goto exit; + } + + rx_msg =3D kzalloc(cmd_snd_rcv_rsp_info.rx_buf_sz, GFP_KERNEL); + if (!rx_msg) { + err =3D -ENOMEM; + goto exit; + } + + tx_msg =3D memdup_user(cmd_snd_rcv_rsp_info.tx_buf, + cmd_snd_rcv_rsp_info.tx_buf_sz); + if (IS_ERR(tx_msg)) { + err =3D PTR_ERR(tx_msg); + goto exit; + } + + if (tx_msg->header.tag !=3D priv->if_defs->cmd_tag) { + err =3D -EINVAL; + goto exit; + } + + if (tx_msg->header.ver =3D=3D priv->if_defs->fw_api_ver && + !info_list->load_hsm_fw.is_fw_loaded) { + err =3D se_load_firmware(priv); + if (err) { + dev_err(priv->dev, "Could not send the message as FW is not loaded."); + err =3D -EPERM; + goto exit; + } + } + err =3D ele_msg_send_rcv(dev_ctx, + tx_msg, + cmd_snd_rcv_rsp_info.tx_buf_sz, + rx_msg, + cmd_snd_rcv_rsp_info.rx_buf_sz); + if (err < 0) + goto exit; + + dev_dbg(priv->dev, + "%s: %s %s\n", + dev_ctx->devname, + __func__, + "message received, start transmit to user"); + + /* We may need to copy the output data to user before + * delivering the completion message. + */ + err =3D se_dev_ctx_cpy_out_data(dev_ctx); + if (err < 0) + goto exit; + + /* Copy data from the buffer */ + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4, + rx_msg, + cmd_snd_rcv_rsp_info.rx_buf_sz, false); + + if (copy_to_user(cmd_snd_rcv_rsp_info.rx_buf, rx_msg, + cmd_snd_rcv_rsp_info.rx_buf_sz)) { + dev_err(priv->dev, + "%s: Failed to copy to user\n", + dev_ctx->devname); + err =3D -EFAULT; + } + +exit: + se_dev_ctx_shared_mem_cleanup(dev_ctx); + + if (copy_to_user((void __user *)arg, &cmd_snd_rcv_rsp_info, + sizeof(cmd_snd_rcv_rsp_info))) { + dev_err(priv->dev, + "%s: Failed to copy cmd_snd_rcv_rsp_info from user\n", + dev_ctx->devname); + err =3D -EFAULT; + } + + return err; +} + +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx, + u64 arg) +{ + struct se_if_priv *priv =3D dev_ctx->priv; + struct se_if_node_info *info; + struct se_ioctl_get_if_info if_info; + int err =3D 0; + + info =3D container_of(priv->if_defs, typeof(*info), if_defs); + + if_info.se_if_id =3D info->se_if_id; + if_info.interrupt_idx =3D 0; + if_info.tz =3D 0; + if_info.did =3D info->se_if_did; + if_info.cmd_tag =3D priv->if_defs->cmd_tag; + if_info.rsp_tag =3D priv->if_defs->rsp_tag; + if_info.success_tag =3D priv->if_defs->success_tag; + if_info.base_api_ver =3D priv->if_defs->base_api_ver; + if_info.fw_api_ver =3D priv->if_defs->fw_api_ver; + + dev_dbg(priv->dev, + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n", + dev_ctx->devname, + if_info.se_if_id, if_info.interrupt_idx, + if_info.tz, if_info.did); + + if (copy_to_user((u8 __user *)arg, &if_info, sizeof(if_info))) { + dev_err(priv->dev, + "%s: Failed to copy mu info to user\n", + dev_ctx->devname); + err =3D -EFAULT; + goto exit; + } + +exit: + return err; +} + +/* + * Copy a buffer of data to/from the user and return the address to use in + * messages + */ +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx, + u64 arg) +{ + struct se_shared_mem *shared_mem =3D NULL; + struct se_ioctl_setup_iobuf io =3D {0}; + int err =3D 0; + u32 pos; + + if (copy_from_user(&io, (u8 __user *)arg, sizeof(io))) { + dev_err(dev_ctx->priv->dev, + "%s: Failed copy iobuf config from user\n", + dev_ctx->devname); + err =3D -EFAULT; + goto exit; + } + + dev_dbg(dev_ctx->priv->dev, + "%s: io [buf: %p(%d) flag: %x]\n", + dev_ctx->devname, + io.user_buf, io.length, io.flags); + + if (io.length =3D=3D 0 || !io.user_buf) { + /* + * Accept NULL pointers since some buffers are optional + * in FW commands. In this case we should return 0 as + * pointer to be embedded into the message. + * Skip all data copy part of code below. + */ + io.ele_addr =3D 0; + goto copy; + } + + /* No specific requirement for this buffer. */ + shared_mem =3D &dev_ctx->se_shared_mem_mgmt.non_secure_mem; + + /* Check there is enough space in the shared memory. */ + if (shared_mem->size < shared_mem->pos || + round_up(io.length, 8u) >=3D (shared_mem->size - shared_mem->pos)) { + dev_err(dev_ctx->priv->dev, + "%s: Not enough space in shared memory\n", + dev_ctx->devname); + err =3D -ENOMEM; + goto exit; + } + + /* Allocate space in shared memory. 8 bytes aligned. */ + pos =3D shared_mem->pos; + shared_mem->pos +=3D round_up(io.length, 8u); + io.ele_addr =3D (u64)shared_mem->dma_addr + pos; + + memset(shared_mem->ptr + pos, 0, io.length); + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) || + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) { + /* + * buffer is input: + * copy data from user space to this allocated buffer. + */ + if (copy_from_user(shared_mem->ptr + pos, io.user_buf, + io.length)) { + dev_err(dev_ctx->priv->dev, + "%s: Failed copy data to shared memory\n", + dev_ctx->devname); + err =3D -EFAULT; + goto exit; + } + } + + err =3D add_b_desc_to_pending_list(shared_mem->ptr + pos, + &io, + dev_ctx); + if (err < 0) + dev_err(dev_ctx->priv->dev, + "%s: Failed to allocate/link b_desc.", + dev_ctx->devname); + +copy: + /* Provide the EdgeLock Enclave address to user space only if success.*/ + if (copy_to_user((u8 __user *)arg, &io, sizeof(io))) { + dev_err(dev_ctx->priv->dev, + "%s: Failed to copy iobuff setup to user.", + dev_ctx->devname); + err =3D -EFAULT; + goto exit; + } +exit: + return err; +} + +/* IOCTL to provide SoC information */ +static int se_ioctl_get_se_soc_info_handler(struct se_if_device_ctx *dev_c= tx, + u64 arg) +{ + const struct se_if_node_info_list *info_list; + struct se_ioctl_get_soc_info soc_info; + int err =3D -EINVAL; + + info_list =3D device_get_match_data(dev_ctx->priv->dev); + if (!info_list) + goto exit; + + soc_info.soc_id =3D info_list->soc_id; + soc_info.soc_rev =3D se_soc_rev; + + err =3D (int)copy_to_user((u8 __user *)arg, (u8 *)(&soc_info), sizeof(soc= _info)); + if (err) { + dev_err(dev_ctx->priv->dev, + "%s: Failed to copy soc info to user\n", + dev_ctx->devname); + err =3D -EFAULT; + goto exit; + } + +exit: + return err; +} + +/* + * File operations for user-space + */ + +/* Write a message to the MU. */ +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct se_if_device_ctx *dev_ctx =3D fp->private_data; + struct se_api_msg *tx_msg __free(kfree) =3D NULL; + struct se_if_priv *priv =3D dev_ctx->priv; + int err; + + dev_dbg(priv->dev, + "%s: write from buf (%p)%zu, ppos=3D%lld\n", + dev_ctx->devname, + buf, size, ((ppos) ? *ppos : 0)); + + if (mutex_lock_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx !=3D priv->cmd_receiver_clbk_hdl.dev_ctx) { + err =3D -EINVAL; + goto exit; + } + + if (size < SE_MU_HDR_SZ) { + dev_err(priv->dev, + "%s: User buffer too small(%zu < %d)\n", + dev_ctx->devname, + size, SE_MU_HDR_SZ); + err =3D -ENOSPC; + goto exit; + } + + tx_msg =3D memdup_user(buf, size); + if (IS_ERR(tx_msg)) { + err =3D PTR_ERR(tx_msg); + goto exit; + } + + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4, + tx_msg, size, false); + + err =3D ele_msg_send(dev_ctx, tx_msg, size); + if (err < 0) + goto exit; +exit: + mutex_unlock(&dev_ctx->fops_lock); + return err; +} + +/* + * Read a message from the MU. + * Blocking until a message is available. + */ +static ssize_t se_if_fops_read(struct file *fp, char __user *buf, + size_t size, loff_t *ppos) +{ + struct se_if_device_ctx *dev_ctx =3D fp->private_data; + struct se_if_priv *priv =3D dev_ctx->priv; + int err; + + dev_dbg(priv->dev, + "%s: read to buf %p(%zu), ppos=3D%lld\n", + dev_ctx->devname, + buf, size, ((ppos) ? *ppos : 0)); + + if (mutex_lock_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx !=3D priv->cmd_receiver_clbk_hdl.dev_ctx) { + err =3D -EINVAL; + goto exit; + } + + err =3D ele_msg_rcv(dev_ctx, &priv->cmd_receiver_clbk_hdl); + if (err < 0) { + dev_err(priv->dev, + "%s: Err[0x%x]:Interrupted by signal.\n", + dev_ctx->devname, err); + dev_dbg(priv->dev, + "Current active dev-ctx count =3D %d.\n", + dev_ctx->priv->active_devctx_count); + goto exit; + } + + /* We may need to copy the output data to user before + * delivering the completion message. + */ + err =3D se_dev_ctx_cpy_out_data(dev_ctx); + if (err < 0) + goto exit; + + /* Copy data from the buffer */ + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4, + priv->cmd_receiver_clbk_hdl.rx_msg, + priv->cmd_receiver_clbk_hdl.rx_msg_sz, + false); + + if (copy_to_user(buf, priv->cmd_receiver_clbk_hdl.rx_msg, + priv->cmd_receiver_clbk_hdl.rx_msg_sz)) { + dev_err(priv->dev, + "%s: Failed to copy to user\n", + dev_ctx->devname); + err =3D -EFAULT; + } + err =3D priv->cmd_receiver_clbk_hdl.rx_msg_sz; +exit: + priv->cmd_receiver_clbk_hdl.rx_msg_sz =3D 0; + + se_dev_ctx_shared_mem_cleanup(dev_ctx); + + mutex_unlock(&dev_ctx->fops_lock); + return err; +} + +/* Open a character device. */ +static int se_if_fops_open(struct inode *nd, struct file *fp) +{ + struct miscdevice *miscdev =3D fp->private_data; + struct se_if_priv *priv =3D dev_get_drvdata(miscdev->parent); + struct se_if_device_ctx *misc_dev_ctx =3D priv->priv_dev_ctx; + struct se_if_device_ctx *dev_ctx; + int err =3D 0; + + if (mutex_lock_interruptible(&misc_dev_ctx->fops_lock)) + return -EBUSY; + + priv->dev_ctx_mono_count++; + err =3D init_device_context(priv, + priv->dev_ctx_mono_count ? + priv->dev_ctx_mono_count + : priv->dev_ctx_mono_count++, + &dev_ctx, NULL); + if (err) { + dev_err(priv->dev, + "Failed[0x%x] to create device contexts.\n", + err); + goto exit; + } + + fp->private_data =3D dev_ctx; + +exit: + mutex_unlock(&misc_dev_ctx->fops_lock); + return err; +} + +/* Close a character device. */ +static int se_if_fops_close(struct inode *nd, struct file *fp) +{ + struct se_if_device_ctx *dev_ctx =3D fp->private_data; + struct se_if_priv *priv =3D dev_ctx->priv; + + if (mutex_lock_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + /* check if this device was registered as command receiver. */ + if (priv->cmd_receiver_clbk_hdl.dev_ctx =3D=3D dev_ctx) { + priv->cmd_receiver_clbk_hdl.dev_ctx =3D NULL; + kfree(priv->cmd_receiver_clbk_hdl.rx_msg); + priv->cmd_receiver_clbk_hdl.rx_msg =3D NULL; + } + + se_dev_ctx_shared_mem_cleanup(dev_ctx); + cleanup_se_shared_mem(dev_ctx); + + priv->active_devctx_count--; + list_del(&dev_ctx->link); + + mutex_unlock(&dev_ctx->fops_lock); + kfree(dev_ctx->devname); + kfree(dev_ctx); + + return 0; +} + +/* IOCTL entry point of a character device */ +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + struct se_if_device_ctx *dev_ctx =3D fp->private_data; + struct se_if_priv *priv =3D dev_ctx->priv; + int err; + + /* Prevent race during change of device context */ + if (mutex_lock_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + switch (cmd) { + case SE_IOCTL_ENABLE_CMD_RCV: + if (!priv->cmd_receiver_clbk_hdl.dev_ctx) { + if (!priv->cmd_receiver_clbk_hdl.rx_msg) { + priv->cmd_receiver_clbk_hdl.rx_msg + =3D kzalloc(MAX_NVM_MSG_LEN, + GFP_KERNEL); + if (!priv->cmd_receiver_clbk_hdl.rx_msg) { + err =3D -ENOMEM; + break; + } + } + priv->cmd_receiver_clbk_hdl.rx_msg_sz =3D MAX_NVM_MSG_LEN; + priv->cmd_receiver_clbk_hdl.dev_ctx =3D dev_ctx; + err =3D 0; + } else { + err =3D -EBUSY; + } + break; + case SE_IOCTL_GET_MU_INFO: + err =3D se_ioctl_get_mu_info(dev_ctx, arg); + break; + case SE_IOCTL_SETUP_IOBUF: + err =3D se_ioctl_setup_iobuf_handler(dev_ctx, arg); + break; + case SE_IOCTL_GET_SOC_INFO: + err =3D se_ioctl_get_se_soc_info_handler(dev_ctx, arg); + break; + case SE_IOCTL_CMD_SEND_RCV_RSP: + err =3D se_ioctl_cmd_snd_rcv_rsp_handler(dev_ctx, arg); + break; + default: + err =3D -EINVAL; + dev_dbg(priv->dev, + "%s: IOCTL %.8x not supported\n", + dev_ctx->devname, + cmd); + } + + mutex_unlock(&dev_ctx->fops_lock); + + return (long)err; +} + +/* Char driver setup */ +static const struct file_operations se_if_fops =3D { + .open =3D se_if_fops_open, + .owner =3D THIS_MODULE, + .release =3D se_if_fops_close, + .unlocked_ioctl =3D se_ioctl, + .read =3D se_if_fops_read, + .write =3D se_if_fops_write, +}; + /* interface for managed res to free a mailbox channel */ static void if_mbox_free_channel(void *mbox_chan) { @@ -348,6 +1105,7 @@ static int se_if_request_channel(struct device *dev, =20 static void se_if_probe_cleanup(void *plat_dev) { + struct se_if_device_ctx *dev_ctx, *t_dev_ctx; struct platform_device *pdev =3D plat_dev; struct device *dev =3D &pdev->dev; struct se_fw_load_info *load_fw; @@ -372,6 +1130,18 @@ static void se_if_probe_cleanup(void *plat_dev) load_fw->imem.buf =3D NULL; } =20 + if (priv->dev_ctx_mono_count) { + list_for_each_entry_safe(dev_ctx, t_dev_ctx, &priv->dev_ctx_list, link) { + list_del(&dev_ctx->link); + priv->active_devctx_count--; + } + } + + if (priv->priv_dev_ctx && priv->priv_dev_ctx->miscdev) { + devm_remove_action(dev, if_misc_deregister, &priv->priv_dev_ctx->miscdev= ); + misc_deregister(priv->priv_dev_ctx->miscdev); + } + /* No need to check, if reserved memory is allocated * before calling for its release. Or clearing the * un-set bit. @@ -456,6 +1226,7 @@ static int se_if_probe(struct platform_device *pdev) goto exit; } } + INIT_LIST_HEAD(&priv->dev_ctx_list); =20 if (info->reserved_dma_ranges) { ret =3D of_reserved_mem_device_init(dev); @@ -467,6 +1238,14 @@ static int se_if_probe(struct platform_device *pdev) } } =20 + ret =3D init_device_context(priv, 0, &priv->priv_dev_ctx, &se_if_fops); + if (ret) { + dev_err(dev, + "Failed[0x%x] to create device contexts.\n", + ret); + goto exit; + } + ret =3D se_soc_info(priv); if (ret) { dev_err(dev, diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h index de0d4a1bcb9e..a7f740e83a7c 100644 --- a/drivers/firmware/imx/se_ctrl.h +++ b/drivers/firmware/imx/se_ctrl.h @@ -13,6 +13,7 @@ #define MAX_FW_LOAD_RETRIES 50 =20 #define RES_STATUS(x) FIELD_GET(0x000000ff, x) +#define MAX_DATA_SIZE_PER_USER (65 * 1024) #define MAX_NVM_MSG_LEN (256) #define MESSAGING_VERSION_6 0x6 #define MESSAGING_VERSION_7 0x7 @@ -31,7 +32,7 @@ struct se_clbk_handle { struct completion done; bool signal_rcvd; - atomic_t pending_hdr; + struct se_if_device_ctx *dev_ctx; u32 rx_msg_sz; /* Assignment of the rx_msg buffer to held till the * received content as part callback function, is copied. @@ -46,6 +47,40 @@ struct se_imem_buf { u32 state; }; =20 +struct se_buf_desc { + u8 *shared_buf_ptr; + void __user *usr_buf_ptr; + u32 size; + struct list_head link; +}; + +struct se_shared_mem { + dma_addr_t dma_addr; + u32 size; + u32 pos; + u8 *ptr; +}; + +struct se_shared_mem_mgmt_info { + struct list_head pending_in; + struct list_head pending_out; + + struct se_shared_mem secure_mem; + struct se_shared_mem non_secure_mem; +}; + +/* Private struct for each char device instance. */ +struct se_if_device_ctx { + struct se_if_priv *priv; + struct miscdevice *miscdev; + const char *devname; + + struct mutex fops_lock; + + struct se_shared_mem_mgmt_info se_shared_mem_mgmt; + struct list_head link; +}; + /* Header of the messages exchange with the EdgeLock Enclave */ struct se_msg_hdr { u8 ver; @@ -89,6 +124,11 @@ struct se_if_priv { =20 struct gen_pool *mem_pool; const struct se_if_defines *if_defs; + + struct se_if_device_ctx *priv_dev_ctx; + struct list_head dev_ctx_list; + u32 active_devctx_count; + u32 dev_ctx_mono_count; }; =20 #endif diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h new file mode 100644 index 000000000000..582e3fef086e --- /dev/null +++ b/include/uapi/linux/se_ioctl.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Cla= use*/ +/* + * Copyright 2024 NXP + */ + +#ifndef SE_IOCTL_H +#define SE_IOCTL_H + +/* IOCTL definitions. */ + +struct se_ioctl_setup_iobuf { + void __user *user_buf; + u32 length; + u32 flags; + u64 ele_addr; +}; + +struct se_ioctl_shared_mem_cfg { + u32 base_offset; + u32 size; +}; + +struct se_ioctl_get_if_info { + u8 se_if_id; + u8 interrupt_idx; + u8 tz; + u8 did; + u8 cmd_tag; + u8 rsp_tag; + u8 success_tag; + u8 base_api_ver; + u8 fw_api_ver; +}; + +struct se_ioctl_cmd_snd_rcv_rsp_info { + u32 __user *tx_buf; + int tx_buf_sz; + u32 __user *rx_buf; + int rx_buf_sz; +}; + +struct se_ioctl_get_soc_info { + u16 soc_id; + u16 soc_rev; +}; + +/* IO Buffer Flags */ +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u) +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u) +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u) +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u) +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u) + +/* IOCTLS */ +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */ + +/* + * ioctl to designated the current fd as logical-reciever. + * This is ioctl is send when the nvm-daemon, a slave to the + * firmware is started by the user. + */ +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01) + +/* + * ioctl to get the buffer allocated from the memory, which is shared + * between kernel and FW. + * Post allocation, the kernel tagged the allocated memory with: + * Output + * Input + * Input-Output + * Short address + * Secure-memory + */ +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \ + struct se_ioctl_setup_iobuf) + +/* + * ioctl to get the mu information, that is used to exchange message + * with FW, from user-spaced. + */ +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \ + struct se_ioctl_get_if_info) +/* + * ioctl to get SoC Info from user-space. + */ +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \ + struct se_ioctl_get_soc_info) + +/* + * ioctl to send command and receive response from user-space. + */ +#define SE_IOCTL_CMD_SEND_RCV_RSP _IOWR(SE_IOCTL, 0x07, \ + struct se_ioctl_cmd_snd_rcv_rsp_info) +#endif --=20 2.34.1