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Thu, 17 Oct 2024 01:21:22 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49H1LLOv001473 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 01:21:21 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 16 Oct 2024 18:21:21 -0700 From: Jessica Zhang Date: Wed, 16 Oct 2024 18:21:26 -0700 Subject: [PATCH v3 20/23] drm/msm/dpu: Start frame done timer after encoder kickoff Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241016-concurrent-wb-v3-20-a33cf9b93835@quicinc.com> References: <20241016-concurrent-wb-v3-0-a33cf9b93835@quicinc.com> In-Reply-To: <20241016-concurrent-wb-v3-0-a33cf9b93835@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Simona Vetter , Simona Vetter CC: , , , , , Rob Clark , =?utf-8?q?Ville_Syrj=C3=A4l=C3=A4?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-2a633 X-Developer-Signature: v=1; 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Thus, create a separate API for starting the encoder frame done timer and call it after the encoder kickoff is finished Reviewed-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 ++++++++++++++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 +++- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index b156175c81898d5c0b5dc4692bf44fa74dffa574..22d135c8c8be498533b6730fbd0= 077628b846989 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -970,8 +970,10 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) =20 dpu_vbif_clear_errors(dpu_kms); =20 - drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { dpu_encoder_kickoff(encoder); + dpu_encoder_start_frame_done_timer(encoder); + } =20 reinit_completion(&dpu_crtc->frame_done_comp); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 7d2ebbb4f20d3c4ca588ff227e398387887b22f8..7e00fabe1327d753c00327870df= dbab4eb587754 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1941,18 +1941,16 @@ bool dpu_encoder_is_valid_for_commit(struct drm_enc= oder *drm_enc) return true; } =20 -void dpu_encoder_kickoff(struct drm_encoder *drm_enc) +/** + * dpu_encoder_start_frame_done_timer - Start the encoder frame done timer + * @drm_enc: Pointer to drm encoder structure + */ +void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc; - struct dpu_encoder_phys *phys; unsigned long timeout_ms; - unsigned int i; =20 - DPU_ATRACE_BEGIN("encoder_kickoff"); dpu_enc =3D to_dpu_encoder_virt(drm_enc); - - trace_dpu_enc_kickoff(DRMID(drm_enc)); - timeout_ms =3D DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); =20 @@ -1960,6 +1958,19 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc) mod_timer(&dpu_enc->frame_done_timer, jiffies + msecs_to_jiffies(timeout_ms)); =20 +} + +void dpu_encoder_kickoff(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + struct dpu_encoder_phys *phys; + unsigned int i; + + DPU_ATRACE_BEGIN("encoder_kickoff"); + dpu_enc =3D to_dpu_encoder_virt(drm_enc); + + trace_dpu_enc_kickoff(DRMID(drm_enc)); + /* All phys encs are ready to go, trigger the kickoff */ _dpu_encoder_kickoff_phys(dpu_enc); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.h index 0d27e50384f049e21d4b5b5258d77d3ec7976c13..deaa0463b289fd12eaa0bb4179c= 58d04425007a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -210,4 +210,6 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm= _enc, */ bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc); =20 +void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc); + #endif /* __DPU_ENCODER_H__ */ --=20 2.34.1