From nobody Tue Nov 26 22:18:55 2024 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D26F41F76C8 for ; Tue, 15 Oct 2024 16:48:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010885; cv=none; b=HfDgY91eGMNoR566rbCy9/wYRCDoomqnxBupTZp9SP6DACmJsMQpU5JVP7ol25zMx9snN2ud5DvrY11mUlSx/u00qr/y0a6O7plUOBIRjWw42un/GIJmeHSkfkMw9WnS7tktpC/ZptudOMDC3+4LHyjWZBigl4CeJ7m24pBU9lo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010885; c=relaxed/simple; bh=LERwhS4RVKBGhttEmAJP9WRlWvBzyJk53VHGxQRRYkI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KAqZNH8NfYybtN0q/bYXwFg2PFwZAwh73cMqLrHh1HRibj4A6xmqqXmQCG21QiUMxM1Tt6zXVcbd1bY48zJPP1Atn8+r3A3PEJrwAuA4Yu7O7cMnojPqFJ1UHMEIJcr1CW7pAvpHXn7hoZoGJ3chUiqSHFaLNPM7yZqg5rK+U1g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=lL5PztFz; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="lL5PztFz" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-37d41894a32so18722f8f.1 for ; Tue, 15 Oct 2024 09:48:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729010880; x=1729615680; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7pKXusPTZ5tcxxkq2V3AB08xzlPZhMDjS7/H8WgERgg=; b=lL5PztFz4D8EHVoAv5hJ+NRkYoJLwIl+QIl+G4+5Q6q7zwnOSPqCz16bCLRI5hL34t 8NwDj6Ws6BV97AlrLMOWESxySb+F3LzXIXG6GtKrgQKBi1y6W7kMhVOsRwqusehNFPYt uD+LxlnT/p6KJZz8oIANxWWRfFJ7mOE7biesvxbhNclfSARd99Pis4J8N26HZs4aUgrI rt5f0P7pWLY2J3wmJyNpYcKeeqqL2jQvsRrCDUvWtbZ+DdxKDza5ii0skz7BAkeBpt+p 4de+Oy+dQAGoX3wXQX1ZUU0nlc2knlKIBLe8e8OBRcsnGEae0lyMt5dEgOJEdZO6mBv7 gqHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729010880; x=1729615680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7pKXusPTZ5tcxxkq2V3AB08xzlPZhMDjS7/H8WgERgg=; b=P0HJgyBfIfynf91FH5hN0hmJDeza6XR7w5/BHCm1dK+bc3p9Aypei5MDGKo9OOatzV OUzImbvheWc9NxO0u6/+5hU+He08uM6Zzx6k+hrBWgi+41UTCL+HQT6H+a15jyrn19Vh xnpcMLUAJBSOlJQ6UklhGouVi6zKTkDBk0lOQTGWfRJT0U7nXSDcJklsj6nzJ0GgGG6s UxXmjmg6TMJPMSHGiz+7dsx56XFbRvoJ4Jq8x2WmFRLAR7cGnHQR4xbdLNKD9/5kfj0p cWlvp/M+RkVQqBQkjbBAyx1NLeMVxFd3BEByZVpmofmygfJA0IrDHUut75FKbH8/ghX+ 6L+w== X-Forwarded-Encrypted: i=1; AJvYcCWpuqyMon9GyCEE3XKfs2wf/HrHw1SzInaP09AfILavuYuj2+GW1RV7I7PEccOJyerw+WsCuRU966htI44=@vger.kernel.org X-Gm-Message-State: AOJu0YwXi3t02l989+Lgi8DCT7MPa7znUoMNyfeHvrhNMAOFbRiL2oAt AVRdCHnS2Hau8vJh0qZsrVDpIKo0dVd66vsSN2wk24xtYawgH88Xqoil+31wsuk= X-Google-Smtp-Source: AGHT+IHHc60GgREOlS98Zspu++ht5CfNcHtWXghPlVy/gA432Hwxq+nY4kDwZWwzU4bPGzheaVwXoQ== X-Received: by 2002:a05:6000:194b:b0:37d:460d:2d07 with SMTP id ffacd0b85a97d-37d86285f8cmr1094955f8f.10.1729010879983; Tue, 15 Oct 2024 09:47:59 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56eab2sm22882045e9.26.2024.10.15.09.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 09:47:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, ulf.hansson@linaro.org Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 1/4] clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup() Date: Tue, 15 Oct 2024 19:47:29 +0300 Message-Id: <20241015164732.4085249-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> References: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Move the PM domain power on in rzg2l_cpg_pd_setup(). With this the previously always-on power domains got struct generic_pm_domain::{power_on, power_off} populated (and registered with simple_qos_governor if #power-domain-cells =3D <1> and with pm_domain_always_on_gov if #power-domain-cells =3D <0>). The values for struct generic_pm_domain::{power_on, power_off} are now populated for all registered domains but used by core only for the domains that can use them (the PM domain should be non always-on and registered with simple_qos_governor). Moreover, the power on/off functions check if the mstop support is valid. The mstop is populated only by the RZ/G3S initialization code at the moment. This approach was chosen to keep the code simple and use the same code across different implementations. There should be no issues with this approach as the always on domains are registered with GENPD_FLAG_ALWAYS_ON and the PM domain core takes care of it. This approach allows doing further cleanups on the rzg2l_cpg power domain registering code that will be handled by the next commit. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Reviewed-by: Ulf Hansson --- Changes in v4: - call rzg2l_cpg_power_on() unconditionally - drop the governor parameter of rzg2l_cpg_pd_setup() and decide the governor based on always_on flag - collected tags Changes in v3: - none; this patch is new drivers/clk/renesas/rzg2l-cpg.c | 41 ++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 88bf39e8c79c..63ad467196f3 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1680,23 +1680,31 @@ static int rzg2l_cpg_power_off(struct generic_pm_do= main *domain) return 0; } =20 -static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_= on) +static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd) { + bool always_on =3D !!(pd->genpd.flags & GENPD_FLAG_ALWAYS_ON); struct dev_power_governor *governor; + int ret; + + if (always_on) + governor =3D &pm_domain_always_on_gov; + else + governor =3D &simple_qos_governor; =20 pd->genpd.flags |=3D GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; pd->genpd.attach_dev =3D rzg2l_cpg_attach_dev; pd->genpd.detach_dev =3D rzg2l_cpg_detach_dev; - if (always_on) { - pd->genpd.flags |=3D GENPD_FLAG_ALWAYS_ON; - governor =3D &pm_domain_always_on_gov; - } else { - pd->genpd.power_on =3D rzg2l_cpg_power_on; - pd->genpd.power_off =3D rzg2l_cpg_power_off; - governor =3D &simple_qos_governor; - } + pd->genpd.power_on =3D rzg2l_cpg_power_on; + pd->genpd.power_off =3D rzg2l_cpg_power_off; + + ret =3D pm_genpd_init(&pd->genpd, governor, !always_on); + if (ret) + return ret; =20 - return pm_genpd_init(&pd->genpd, governor, !always_on); + if (always_on) + ret =3D rzg2l_cpg_power_on(&pd->genpd); + + return ret; } =20 static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) @@ -1711,8 +1719,9 @@ static int __init rzg2l_cpg_add_clk_domain(struct rzg= 2l_cpg_priv *priv) return -ENOMEM; =20 pd->genpd.name =3D np->name; + pd->genpd.flags =3D GENPD_FLAG_ALWAYS_ON; pd->priv =3D priv; - ret =3D rzg2l_cpg_pd_setup(pd, true); + ret =3D rzg2l_cpg_pd_setup(pd); if (ret) return ret; =20 @@ -1785,20 +1794,16 @@ static int __init rzg2l_cpg_add_pm_domains(struct r= zg2l_cpg_priv *priv) return -ENOMEM; =20 pd->genpd.name =3D info->pm_domains[i].name; + if (always_on) + pd->genpd.flags =3D GENPD_FLAG_ALWAYS_ON; pd->conf =3D info->pm_domains[i].conf; pd->id =3D info->pm_domains[i].id; pd->priv =3D priv; =20 - ret =3D rzg2l_cpg_pd_setup(pd, always_on); + ret =3D rzg2l_cpg_pd_setup(pd); if (ret) return ret; =20 - if (always_on) { - ret =3D rzg2l_cpg_power_on(&pd->genpd); - if (ret) - return ret; - } - domains->domains[i] =3D &pd->genpd; /* Parent should be on the very first entry of info->pm_domains[]. */ if (!i) { --=20 2.39.2 From nobody Tue Nov 26 22:18:55 2024 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05ED71F9EA7 for ; Tue, 15 Oct 2024 16:48:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010885; cv=none; b=YEy2xARD7tRR/1u4jYqJZMhhFWtxIvk3rm/+szSqNN8OKmGunxKKwYd4b9v/CIu9ZsryxhTy0FyL4X08PwOHNobsVbIRFEbN6R3+6F7T0fHV6yZPpy4gCAbj6pK237uUp4N+31R8CI57by/pfiQZhNonJykC9hiOtPVpwYznzyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010885; c=relaxed/simple; bh=Jb5I9yevY8Ohi3WQ6h5tfsgDg3BdRc3SmPZpDeGGynA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jN8Zi1boeBgo5/fpqq/j9EwPnibLn2Gif9VVO+ifN9pM8BplPOOZJAv3Ccsbg+rKuahW2hjCUr1gDMPpsvjnn5GwizxQnNcHZ5HM3huOYLPjDTw1iTkh5jtZMguOxOvwnxNjQ+zZCPy3pq2oqQt0F6ab2Hh9XvMTm6mEW25SKec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Z5ao1M4v; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Z5ao1M4v" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-37d447de11dso4043557f8f.1 for ; Tue, 15 Oct 2024 09:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729010882; x=1729615682; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Aa2k11SdDGuhZHKsqJ/TS4gDqIGQb7t26+plXvVEVl4=; b=Z5ao1M4vbsAOwbbqydzUrxzuGqNF6xGKeyj/c0dacnOnZ+E4AQerq75yE+L1BNkK9f tuWChYfsUwN/W3yj/HV42HdB4AnC3XZYG/mjpZZbixmB20VbHx3/4HqYU4eaFRR6XQPG yP1wKDQmfon0MIdPXKvgfhKEigLS+Ynp9xnBaEwixd8NHusP7GIHFBk13lQE78UZhmiS GFNcjMW+IYnc6YgaMs71y0AX561ATTB3qVvsmFuhVfaZvHqfn1or1qghsIonyJPjwfMf vNb/4FDw9iqj1VZZcA0xdQA2CjWNyKRfnrNFtvk2rV3olXpQRKwRUV5c7viMsaSc7mmK exnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729010882; x=1729615682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Aa2k11SdDGuhZHKsqJ/TS4gDqIGQb7t26+plXvVEVl4=; b=KXTO++GCq9Bfcfs9qnIgORC0LX0GV7QTB5r4MQSGdhNXhHtD3AUkWbsz3d1JgyKe4U y8jOpBfhJPB5NNRPv1+8curMBf6Tb5xxOl+Pc3Am5ae3ry0kmsWR81D4mIBk/3ZVED9+ TjlzsnS9sbM3dG070YpTjS1yBAi2+UEuZjZ29GiKYeeGv9Zo3R6EwoK9k/f6qUna4niE CCls2+tsMyisyeuh9f1oKyWuvtwNU4Tq8dHKPvnWSOqHgq8Mp+vUKu0ITgJn4Y/tP7AG gQgy/vZJTognoCzVtHArFHU23CYNzX5ul9l1BgqdU/7jBOgQ6nXLlTUvIQcYqJxOd4/X 4khw== X-Forwarded-Encrypted: i=1; AJvYcCW1l9DDw1uxt3dWwEPgekqQVOjwTcwiS+eZ4e7rziYYIS7zjtb+AATGz3kwGqoM6130KJN17tKCBGwPJwE=@vger.kernel.org X-Gm-Message-State: AOJu0YwBYTNuD/MfbuPWXH8TCo9uxamfj6vUBYGdpiomC8v65h4h4qoq uUek6hnZ5G8tL1gD9bEOlVSIjUVuEi5PyTtX3F23tDRXu/P0s/wfks9748tOKz8= X-Google-Smtp-Source: AGHT+IFtO/+0oKxhctg37h6yJi7w7d+SI/mPQq4wE3AQYP22Ho6+mJDTTlrYPnox00UJhtypId0rQg== X-Received: by 2002:a5d:6703:0:b0:37d:4dd5:220f with SMTP id ffacd0b85a97d-37d551fba84mr10424622f8f.26.1729010882139; Tue, 15 Oct 2024 09:48:02 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56eab2sm22882045e9.26.2024.10.15.09.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 09:48:01 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, ulf.hansson@linaro.org Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 2/4] clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones Date: Tue, 15 Oct 2024 19:47:30 +0300 Message-Id: <20241015164732.4085249-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> References: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea For watchdog PM domain it is necessary to provide GENPD_FLAG_IRQ_SAFE flag to be able to power on the watchdog PM domain from atomic context. For this, adjust the current infrastructure to be able to provide GENPD_FLAG_* for individual PM domains. With this, remove the always_on flag from rzg2l_cpg_add_pm_domains() as it is not necessary anymore. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Reviewed-by: Ulf Hansson --- Changes in v4: - rebased on latest next - collected tags Changes in v3: - update patch description - diff in rzg2l_cpg_add_pm_domains() is now simplified as a result of adding patch 01/04 from this series Changes in v2: - none Changes since RFC: - none; this patch is new drivers/clk/renesas/r9a08g045-cpg.c | 53 +++++++++++------------------ drivers/clk/renesas/rzg2l-cpg.c | 4 +-- drivers/clk/renesas/rzg2l-cpg.h | 10 ++---- 3 files changed, 24 insertions(+), 43 deletions(-) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 1ce40fb51f13..a24cafcbc619 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include =20 @@ -266,61 +267,47 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a= 08g045_pm_domains[] =3D { /* Keep always-on domain on the first position for proper domains registr= ation. */ DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, DEF_REG_CONF(0, 0), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("gic", R9A08G045_PD_GIC, DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("ia55", R9A08G045_PD_IA55, DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("dmac", R9A08G045_PD_DMAC, DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("wdt0", R9A08G045_PD_WDT0, - DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), 0), DEF_PD("sdhi0", R9A08G045_PD_SDHI0, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0), DEF_PD("sdhi1", R9A08G045_PD_SDHI1, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0), DEF_PD("sdhi2", R9A08G045_PD_SDHI2, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0), DEF_PD("usb0", R9A08G045_PD_USB0, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0), DEF_PD("usb1", R9A08G045_PD_USB1, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), 0), DEF_PD("usb-phy", R9A08G045_PD_USB_PHY, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), 0), DEF_PD("eth0", R9A08G045_PD_ETHER0, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0), DEF_PD("eth1", R9A08G045_PD_ETHER1, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0), DEF_PD("i2c0", R9A08G045_PD_I2C0, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0), DEF_PD("i2c1", R9A08G045_PD_I2C1, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0), DEF_PD("i2c2", R9A08G045_PD_I2C2, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0), DEF_PD("i2c3", R9A08G045_PD_I2C3, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0), DEF_PD("scif0", R9A08G045_PD_SCIF0, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0), DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), }; =20 const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 63ad467196f3..85dad87f2318 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1786,7 +1786,6 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg= 2l_cpg_priv *priv) return ret; =20 for (unsigned int i =3D 0; i < info->num_pm_domains; i++) { - bool always_on =3D !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON); struct rzg2l_cpg_pd *pd; =20 pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); @@ -1794,8 +1793,7 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg= 2l_cpg_priv *priv) return -ENOMEM; =20 pd->genpd.name =3D info->pm_domains[i].name; - if (always_on) - pd->genpd.flags =3D GENPD_FLAG_ALWAYS_ON; + pd->genpd.flags =3D info->pm_domains[i].genpd_flags; pd->conf =3D info->pm_domains[i].conf; pd->id =3D info->pm_domains[i].id; pd->priv =3D priv; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index ecfe7e7ea8a1..881a89b5a710 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -270,14 +270,14 @@ struct rzg2l_cpg_pm_domain_conf { * struct rzg2l_cpg_pm_domain_init_data - PM domain init data * @name: PM domain name * @conf: PM domain configuration - * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*) + * @genpd_flags: genpd flags (see GENPD_FLAG_*) * @id: PM domain ID (similar to the ones defined in * include/dt-bindings/clock/-cpg.h) */ struct rzg2l_cpg_pm_domain_init_data { const char * const name; struct rzg2l_cpg_pm_domain_conf conf; - u32 flags; + u32 genpd_flags; u16 id; }; =20 @@ -288,13 +288,9 @@ struct rzg2l_cpg_pm_domain_init_data { .conf =3D { \ .mstop =3D (_mstop_conf), \ }, \ - .flags =3D (_flags), \ + .genpd_flags =3D (_flags), \ } =20 -/* Power domain flags. */ -#define RZG2L_PD_F_ALWAYS_ON BIT(0) -#define RZG2L_PD_F_NONE (0) - /** * struct rzg2l_cpg_info - SoC-specific CPG Description * --=20 2.39.2 From nobody Tue Nov 26 22:18:55 2024 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D779F1F9EB2 for ; Tue, 15 Oct 2024 16:48:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010887; cv=none; b=uh93UMC5ZtnKD2bLAoNhqCkCQVrXGAlO8aYjV49LlXt+95Kgj3ignRTuxbH4Z9nnsq+ggA/vJX+gEQb6iX2UkNz0zjtpjaTAmrzJL9nva0hKO8oi5lM1LoBglqMXPJVDj8VpwsonR7rWLVGvQmdf+hProoeZud4Uish0b3SDxog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010887; c=relaxed/simple; bh=aZbIwEcSSt0dH39z0JtBebgmt6ej6WRax9WCOwkWn7A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OW3yhUnYha1AlUOJzZ58MZ0YK/8FLOvRGbR2Dm3VKFksCd7D2/+fT7S+cygRDIBPwhXU64JfkmHzb6HeHWzLD7B3y/gWnjTmY9lq3MjiEbJ+uks3ZBQKaQz9k6R6RBFewV5GfdCB+0vICMAmAd1qOCy7iX9ZTwxa3CFah1P2tYg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Iyxk7sIj; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Iyxk7sIj" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4311ae6426aso37754825e9.2 for ; Tue, 15 Oct 2024 09:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729010884; x=1729615684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=28BpXdSWTssZ0ypW72g+pbX5C7u5uJHyKQlEUMgzrGE=; b=Iyxk7sIjXaSAsyyoZ1RaMbriKuJ1rJ/3msj7gN2kWYB4tL2l/fC82dQKbNCq/mAozg vH8CuKjsqa02AuUETLA6SqDSKmnhyVELvAcXMsMvpoLSwHrBStCDvSywzrHHgXXMYhv0 tZqgykih7RP+DVp7tMnbCfNnYOeUzemY3lItR6uAgO7NTUZ5q2nU8hBRKL/peVUaWoEX gu45pnsu1jlOSR5RM5ZYi8iVp8iZD1n+gMSKB1EpkIQB2oQ4irdi4hYTZNbr7Q0JY2Ds Mk38zUPiE19seAqepfsFax1S55k/NgdzPp0IEjAQn3Dkn+pO1l/TiDW/FtiQFFsrg8NT ESpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729010884; x=1729615684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=28BpXdSWTssZ0ypW72g+pbX5C7u5uJHyKQlEUMgzrGE=; b=v2H7cmFslP9cu4LUadl51+3z8fZWYxsUI8yCq8lxI7BulzLi8O2H1Gnsd+NRraBth9 XSv5FRKVXL14Lp7xNyutOEa3+glINPtCUTJrA8yIA7a0aaemfVICY02ESexJsCeljI7d hflHKuSQFlhtwm4YBiBHrWPAmGXByAvrScG6ZDsf8FdBQyChoTilcxxh1f8QoyzFXPMS Q/uvdUGweF212Q4+MqvCXIdXLMmbCvQpsKBgacSwkP/0FybXF3Rv8o1HChwqtOwH9RYo je7MNSifKTjhyy7bJGlVfYG6Xp6R4PIADRuEsai5BnIvYNNcSgKI3ViH84qSl7oc+11O gBNQ== X-Forwarded-Encrypted: i=1; AJvYcCVdZF0erP+dqCKCVs+dnhLHH8Srpe8ggYoi1K9hHtXurw7Pcm09eiVlR8TNmXVMJyCOy+YuvdofiiN9B0Q=@vger.kernel.org X-Gm-Message-State: AOJu0Ywo3TJYRO93q/hDnt/jRzS7Z/OqHY0h6xX2gLqCIAplhRg9EHXQ 9LIZzvDLvONnumk2om+1HIxq6EBWE5OsIF6UW4892uXg07zNsxQyQ1czB7Y9Uks= X-Google-Smtp-Source: AGHT+IFV4hQGNWpr5pbDWtAVvd2BGrADLGqJrjGSGacjVgpHRTnrURCIxxyqQ9Q10icW6jWU2wR6Gw== X-Received: by 2002:a05:600c:34cd:b0:42c:a6da:a149 with SMTP id 5b1f17b1804b1-4314a35ea0amr10487485e9.25.1729010884089; Tue, 15 Oct 2024 09:48:04 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56eab2sm22882045e9.26.2024.10.15.09.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 09:48:03 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, ulf.hansson@linaro.org Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 3/4] clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe Date: Tue, 15 Oct 2024 19:47:31 +0300 Message-Id: <20241015164732.4085249-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> References: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea If the watchdog is part of a dedicated power domain (as it may be on RZ/G3S) the watchdog PM domain need to be powered on in the watchdog restart handler. Currently, only the clocks are enabled in the watchdog restart handler. To be able to also power on the PM domain we need to call pm_runtime_resume_and_get() on the watchdog restart handler, mark the watchdog device as IRQ safe and register the watchdog PM domain with GENPD_FLAG_IRQ_SAFE. Register watchdog PM domain as IRQ safe. Along with it the always-on PM domain (parent of the watchdog domain) was marked as IRQ safe. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Reviewed-by: Ulf Hansson --- Changes in v4: - collected tags Changes in v3: - none Changes in v2: - changed patch title; it was "clk: renesas: rzg2l-cpg: Mark watchdog and always-on PM domains as IRQ safe" Changes since RFC: - none; this patch is new drivers/clk/renesas/r9a08g045-cpg.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index a24cafcbc619..f5f454832bb5 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -267,7 +267,7 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08= g045_pm_domains[] =3D { /* Keep always-on domain on the first position for proper domains registr= ation. */ DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, DEF_REG_CONF(0, 0), - GENPD_FLAG_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE), DEF_PD("gic", R9A08G045_PD_GIC, DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)), GENPD_FLAG_ALWAYS_ON), @@ -278,7 +278,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08= g045_pm_domains[] =3D { DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)), GENPD_FLAG_ALWAYS_ON), DEF_PD("wdt0", R9A08G045_PD_WDT0, - DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), 0), + DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), + GENPD_FLAG_IRQ_SAFE), DEF_PD("sdhi0", R9A08G045_PD_SDHI0, DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0), DEF_PD("sdhi1", R9A08G045_PD_SDHI1, --=20 2.39.2 From nobody Tue Nov 26 22:18:55 2024 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D2EE1F9ED8 for ; Tue, 15 Oct 2024 16:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010890; cv=none; b=aeWUqBUyvLyV74ch8ZToUjT12vMP5/L6T3IxoBzpAIKq2kL66bbN1mnw8FqQrldSvh3QK71IVm4dR49ew5Olknw46WCQyGKv5POvk6mvjwvALKXW5Y0Ud6bOzaPuXKS9o9fIMl6LkrJ2y52tzqV76hFUCkTANzP6luoMK1+D9vg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729010890; c=relaxed/simple; bh=Do6R67fDrh9jcYKlaytygcK60uwldKHxRsm47aMNHGw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bUK4Vtup/L3Cu463uhUpAXmmBxKaLLtLIsLlen07iUvC3Dh49GDhS0mZxl8c5P8wIXpL05nY2PAkajQF+nkI6e3bzCEhl3wHqu2E9XliGHQWo15yuRwFl5zqJ3RjR9SiatdFofen3W4cL80rr6o8SxogZJqMsYWh1xDQs6IzB5E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=ND11Q3V5; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="ND11Q3V5" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-37d5038c653so3514077f8f.2 for ; Tue, 15 Oct 2024 09:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729010886; x=1729615686; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8+WjlxGYvCEnZMLQQq/g2hxfKe8FSL9YNlHSnfanC+Q=; b=ND11Q3V5CbQbjKBaTyhLSaUK3vA8iLwFSE9vjjPMMMXv65XpQjNJm8otm6sDdcLG6L /xuwfrH0PfdZVc3aaEmjn+qtaY6qJbAmJQ0MEt1YOOvfzKHagF7tlsc6JMMZJRH0gwyt cc0hOSKpeRSV5R0KixwmncUOnHbTjbQMtjBDGIZlllDauIX5VxUExT0CpLuVFMzN9Lp0 5bj4GAbZ6zRlx4FSbHea7TnQYW78Bg25D3UBw/6/fiEGrmAWw40bP8KBrnYb2e8Nxigo 4VT8NNXHfRlIVMO7n1fZG+zSPo4NBePYywQ8Dvth6CHoIHHbpROit8i5o4fm1nF43Nfc X0sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729010886; x=1729615686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8+WjlxGYvCEnZMLQQq/g2hxfKe8FSL9YNlHSnfanC+Q=; b=sWNmRP9ROvBnKkbWAr6KUXRaUIptspwb5fq4RttYXQQ/4uz4ZyXNqUKtmoc7YtszQD iVn7ihPWuEqLiQQxl0gIM7aivJ1GPAQnJgim9G/jO/7I9uX/DIsBRtUGQSAe2Ip+ixWW wCOZrhxvjRYiaWXYHTto80Q0OMZqmuarmIVsluCMzcP2m7oth+ZsfK+VGHEpeDRrLjjX OeESf5P6y7XfMFgj6LAtlDZWwqewOVD/5aJP/giBJ8HwYaEkQCfiDHurj99ECYDsuj+z 5UpccfdzSca5opUFXy9Fd6a0X7b/jrrd81wkAOReB1w9jdWBEvQ6oW4RlOYHPkNGWq3D ZnVQ== X-Forwarded-Encrypted: i=1; AJvYcCVvqJGhYuXJFK1K+Da2yZhQ2Q07H6bpJ+m614GOs9j4uWvbSdtONLYRpWQV8Yp31iGIF1RwvKFnXVR87Hs=@vger.kernel.org X-Gm-Message-State: AOJu0Yw0d5gJ+LLxse7BPyPzbWrMCmn+6s95g7t7k/pjwne0rI9tVv1o SUXbFqRM3yjq7jDcTdHAlgHs40q4DVF2ZSNeWFY24uzsFLlm99WpQh8qV3ys74s= X-Google-Smtp-Source: AGHT+IFbPxKiOb7gV0asDYaMtDQ6cVmg+NsPy6xW6VOvqCFQFXVTlGbw+GFY1xG0Jhjvm9YrsIjHwQ== X-Received: by 2002:a05:6000:4f:b0:37c:cfeb:e612 with SMTP id ffacd0b85a97d-37d55198893mr9563540f8f.1.1729010885896; Tue, 15 Oct 2024 09:48:05 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56eab2sm22882045e9.26.2024.10.15.09.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 09:48:05 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, ulf.hansson@linaro.org Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 4/4] watchdog: rzg2l_wdt: Power on the watchdog domain in the restart handler Date: Tue, 15 Oct 2024 19:47:32 +0300 Message-Id: <20241015164732.4085249-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> References: <20241015164732.4085249-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea On RZ/G3S the watchdog can be part of a software-controlled PM domain. In this case, the watchdog device need to be powered on in struct watchdog_ops::restart API. This can be done though pm_runtime_resume_and_get() API if the watchdog PM domain and watchdog device are marked as IRQ safe. We mark the watchdog PM domain as IRQ safe with GENPD_FLAG_IRQ_SAFE when the watchdog PM domain is registered and the watchdog device though pm_runtime_irq_safe(). Before commit e4cf89596c1f ("watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'") pm_runtime_get_sync() was used in watchdog restart handler (which is similar to pm_runtime_resume_and_get() except the later one handles the runtime resume errors). Commit e4cf89596c1f ("watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'") dropped the pm_runtime_get_sync() and replaced it with clk_prepare_enable() to avoid invalid wait context due to genpd_lock() in genpd_runtime_resume() being called from atomic context. But clk_prepare_enable() doesn't fit for this either (as reported by Ulf Hansson) as clk_prepare() can also sleep (it just not throw invalid wait context warning as it is not written for this). Because the watchdog device is marked now as IRQ safe (though this patch) the irq_safe_dev_in_sleep_domain() call from genpd_runtime_resume() returns 1 for devices not registering an IRQ safe PM domain for watchdog (as the watchdog device is IRQ safe, PM domain is not and watchdog PM domain is always-on), this being the case for RZ/G3S with old device trees and the rest of the SoCs that use this driver, we can now drop also the clk_prepare_enable() calls in restart handler and rely on pm_runtime_resume_and_get(). Thus, drop clk_prepare_enable() and use pm_runtime_resume_and_get() in watchdog restart handler. Acked-by: Guenter Roeck Reviewed-by: Ulf Hansson Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v4: - collected Geert's tag Changes in v3: - collected Ulf's tag Changes in v2: - adjusted patch description and comment from code - collected tags Changes since RFC: - use pm_runtime_resume_and_get() and pm_runtime_irq_safe() - drop clock prepare in probe drivers/watchdog/rzg2l_wdt.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 2a35f890a288..11bbe48160ec 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -166,8 +167,22 @@ static int rzg2l_wdt_restart(struct watchdog_device *w= dev, struct rzg2l_wdt_priv *priv =3D watchdog_get_drvdata(wdev); int ret; =20 - clk_prepare_enable(priv->pclk); - clk_prepare_enable(priv->osc_clk); + /* + * In case of RZ/G3S the watchdog device may be part of an IRQ safe power + * domain that is currently powered off. In this case we need to power + * it on before accessing registers. Along with this the clocks will be + * enabled. We don't undo the pm_runtime_resume_and_get() as the device + * need to be on for the reboot to happen. + * + * For the rest of SoCs not registering a watchdog IRQ safe power + * domain it is safe to call pm_runtime_resume_and_get() as the + * irq_safe_dev_in_sleep_domain() call in genpd_runtime_resume() + * returns non zero value and the genpd_lock() is avoided, thus, there + * will be no invalid wait context reported by lockdep. + */ + ret =3D pm_runtime_resume_and_get(wdev->parent); + if (ret) + return ret; =20 if (priv->devtype =3D=3D WDT_RZG2L) { ret =3D reset_control_deassert(priv->rstc); @@ -275,6 +290,7 @@ static int rzg2l_wdt_probe(struct platform_device *pdev) =20 priv->devtype =3D (uintptr_t)of_device_get_match_data(dev); =20 + pm_runtime_irq_safe(&pdev->dev); pm_runtime_enable(&pdev->dev); =20 priv->wdev.info =3D &rzg2l_wdt_ident; --=20 2.39.2