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charset="utf-8" From: Clark Wang Extract enetc_int_vector_init() and enetc_int_vector_destroy() from enetc_alloc_msix() so that the code is more concise and readable. Signed-off-by: Clark Wang Signed-off-by: Wei Fang --- v2 changes: This patch is separated from v1 patch 9 ("net: enetc: optimize the allocation of tx_bdr"). Separate enetc_int_vector_init() from the original patch. In addition, add new help function enetc_int_vector_destroy(). --- drivers/net/ethernet/freescale/enetc/enetc.c | 174 +++++++++---------- 1 file changed, 87 insertions(+), 87 deletions(-) diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/eth= ernet/freescale/enetc/enetc.c index 032d8eadd003..d36af3f8ba31 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc.c +++ b/drivers/net/ethernet/freescale/enetc/enetc.c @@ -2965,6 +2965,87 @@ int enetc_ioctl(struct net_device *ndev, struct ifre= q *rq, int cmd) } EXPORT_SYMBOL_GPL(enetc_ioctl); =20 +static int enetc_int_vector_init(struct enetc_ndev_priv *priv, int i, + int v_tx_rings) +{ + struct enetc_int_vector *v __free(kfree); + struct enetc_bdr *bdr; + int j, err; + + v =3D kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL); + if (!v) + return -ENOMEM; + + bdr =3D &v->rx_ring; + bdr->index =3D i; + bdr->ndev =3D priv->ndev; + bdr->dev =3D priv->dev; + bdr->bd_count =3D priv->rx_bd_count; + bdr->buffer_offset =3D ENETC_RXB_PAD; + priv->rx_ring[i] =3D bdr; + + err =3D xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0); + if (err) + return err; + + err =3D xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq, + MEM_TYPE_PAGE_SHARED, NULL); + if (err) { + xdp_rxq_info_unreg(&bdr->xdp.rxq); + return err; + } + + /* init defaults for adaptive IC */ + if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) { + v->rx_ictt =3D 0x1; + v->rx_dim_en =3D true; + } + + INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work); + netif_napi_add(priv->ndev, &v->napi, enetc_poll); + v->count_tx_rings =3D v_tx_rings; + + for (j =3D 0; j < v_tx_rings; j++) { + int idx; + + /* default tx ring mapping policy */ + idx =3D priv->bdr_int_num * j + i; + __set_bit(idx, &v->tx_rings_map); + bdr =3D &v->tx_ring[j]; + bdr->index =3D idx; + bdr->ndev =3D priv->ndev; + bdr->dev =3D priv->dev; + bdr->bd_count =3D priv->tx_bd_count; + priv->tx_ring[idx] =3D bdr; + } + + priv->int_vector[i] =3D no_free_ptr(v); + + return 0; +} + +static void enetc_int_vector_destroy(struct enetc_ndev_priv *priv, int i) +{ + struct enetc_int_vector *v =3D priv->int_vector[i]; + struct enetc_bdr *rx_ring =3D &v->rx_ring; + int j, tx_ring_index; + + xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); + xdp_rxq_info_unreg(&rx_ring->xdp.rxq); + netif_napi_del(&v->napi); + cancel_work_sync(&v->rx_dim.work); + + priv->rx_ring[i] =3D NULL; + + for (j =3D 0; j < v->count_tx_rings; j++) { + tx_ring_index =3D priv->bdr_int_num * j + i; + priv->tx_ring[tx_ring_index] =3D NULL; + } + + kfree(v); + priv->int_vector[i] =3D NULL; +} + int enetc_alloc_msix(struct enetc_ndev_priv *priv) { struct pci_dev *pdev =3D priv->si->pdev; @@ -2986,64 +3067,9 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv) /* # of tx rings per int vector */ v_tx_rings =3D priv->num_tx_rings / priv->bdr_int_num; =20 - for (i =3D 0; i < priv->bdr_int_num; i++) { - struct enetc_int_vector *v; - struct enetc_bdr *bdr; - int j; - - v =3D kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL); - if (!v) { - err =3D -ENOMEM; + for (i =3D 0; i < priv->bdr_int_num; i++) + if (enetc_int_vector_init(priv, i, v_tx_rings)) goto fail; - } - - priv->int_vector[i] =3D v; - - bdr =3D &v->rx_ring; - bdr->index =3D i; - bdr->ndev =3D priv->ndev; - bdr->dev =3D priv->dev; - bdr->bd_count =3D priv->rx_bd_count; - bdr->buffer_offset =3D ENETC_RXB_PAD; - priv->rx_ring[i] =3D bdr; - - err =3D xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0); - if (err) { - kfree(v); - goto fail; - } - - err =3D xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq, - MEM_TYPE_PAGE_SHARED, NULL); - if (err) { - xdp_rxq_info_unreg(&bdr->xdp.rxq); - kfree(v); - goto fail; - } - - /* init defaults for adaptive IC */ - if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) { - v->rx_ictt =3D 0x1; - v->rx_dim_en =3D true; - } - INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work); - netif_napi_add(priv->ndev, &v->napi, enetc_poll); - v->count_tx_rings =3D v_tx_rings; - - for (j =3D 0; j < v_tx_rings; j++) { - int idx; - - /* default tx ring mapping policy */ - idx =3D priv->bdr_int_num * j + i; - __set_bit(idx, &v->tx_rings_map); - bdr =3D &v->tx_ring[j]; - bdr->index =3D idx; - bdr->ndev =3D priv->ndev; - bdr->dev =3D priv->dev; - bdr->bd_count =3D priv->tx_bd_count; - priv->tx_ring[idx] =3D bdr; - } - } =20 num_stack_tx_queues =3D enetc_num_stack_tx_queues(priv); =20 @@ -3062,16 +3088,8 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv) return 0; =20 fail: - while (i--) { - struct enetc_int_vector *v =3D priv->int_vector[i]; - struct enetc_bdr *rx_ring =3D &v->rx_ring; - - xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); - xdp_rxq_info_unreg(&rx_ring->xdp.rxq); - netif_napi_del(&v->napi); - cancel_work_sync(&v->rx_dim.work); - kfree(v); - } + while (i--) + enetc_int_vector_destroy(priv, i); =20 pci_free_irq_vectors(pdev); =20 @@ -3083,26 +3101,8 @@ void enetc_free_msix(struct enetc_ndev_priv *priv) { int i; =20 - for (i =3D 0; i < priv->bdr_int_num; i++) { - struct enetc_int_vector *v =3D priv->int_vector[i]; - struct enetc_bdr *rx_ring =3D &v->rx_ring; - - xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq); - xdp_rxq_info_unreg(&rx_ring->xdp.rxq); - netif_napi_del(&v->napi); - cancel_work_sync(&v->rx_dim.work); - } - - for (i =3D 0; i < priv->num_rx_rings; i++) - priv->rx_ring[i] =3D NULL; - - for (i =3D 0; i < priv->num_tx_rings; i++) - priv->tx_ring[i] =3D NULL; - - for (i =3D 0; i < priv->bdr_int_num; i++) { - kfree(priv->int_vector[i]); - priv->int_vector[i] =3D NULL; - } + for (i =3D 0; i < priv->bdr_int_num; i++) + enetc_int_vector_destroy(priv, i); =20 /* disable all MSIX for this device */ pci_free_irq_vectors(priv->si->pdev); --=20 2.34.1