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charset="utf-8" Add an entry for the MT8186 based Chinchou Chromebook, also known as the ASUS Chromebook CZ12 Flip (CZ1204F). Signed-off-by: Zhengqiao Xia --- .../devicetree/bindings/arm/mediatek.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 1d4bb50fcd8d..49188382f6c0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -239,6 +239,32 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - description: Google Chinchou (ASUS Chromebook CZ12 Flip (CZ1204F)) + items: + - const: google,chinchou-sku0 + - const: google,chinchou-sku2 + - const: google,chinchou-sku4 + - const: google,chinchou-sku5 + - const: google,chinchou + - const: mediatek,mt8186 + - description: Google Chinchou (ASUS Chromebook CZ12 Flip (CZ1204F)) + items: + - const: google,chinchou-sku1 + - const: google,chinchou-sku3 + - const: google,chinchou-sku6 + - const: google,chinchou-sku7 + - const: google,chinchou-sku17 + - const: google,chinchou-sku20 + - const: google,chinchou-sku22 + - const: google,chinchou-sku23 + - const: mediatek,mt8186 + - description: Google Chinchou (ASUS Chromebook CZ12 Flip (CZ1204F)) + items: + - const: google,chinchou-sku16 + - const: google,chinchou-sku18 + - const: google,chinchou-sku19 + - const: google,chinchou-sku21 + - const: mediatek,mt8186 - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14= M868)) items: - const: google,steelix-sku393219 --=20 2.17.1 From nobody Wed Nov 27 00:38:57 2024 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71DDE1EF959 for ; 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Tue, 15 Oct 2024 05:26:28 -0700 (PDT) Received: from ubuntu.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392e8cdc7sm1592844a91.10.2024.10.15.05.26.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 05:26:28 -0700 (PDT) From: Zhengqiao Xia To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, hsinyi@chromium.org, rafal@milecki.pl, macpaul.lin@mediatek.com, sean.wang@mediatek.com, Zhengqiao Xia Subject: [PATCH v1 2/3] arm64: dts: mediatek: Add MT8186 Chinchou Chromebooks Date: Tue, 15 Oct 2024 20:26:07 +0800 Message-Id: <20241015122608.24569-3-xiazhengqiao@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241015122608.24569-1-xiazhengqiao@huaqin.corp-partner.google.com> References: <20241015122608.24569-1-xiazhengqiao@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" MT8186 chinchou, known as ASUS Chromebook CZ12 Flip, is a MT8186 based laptop. It is based on the "corsola" design. It includes chinchou and chinchou360, including LTE, stylus, touchscreen combinations. Signed-off-by: Zhengqiao Xia --- arch/arm64/boot/dts/mediatek/Makefile | 3 + .../mediatek/mt8186-corsola-chinchou-sku0.dts | 18 ++ .../mediatek/mt8186-corsola-chinchou-sku1.dts | 34 ++ .../mt8186-corsola-chinchou-sku16.dts | 28 ++ .../dts/mediatek/mt8186-corsola-chinchou.dtsi | 296 ++++++++++++++++++ 5 files changed, 379 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sk= u0.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sk= u1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sk= u16.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dt= si diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 8fd7b2bb7a15..0db7770e8907 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -55,6 +55,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-kodama-sku3= 2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-chinchou-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-chinchou-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-chinchou-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-magneton-sku393216.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-magneton-sku393217.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-magneton-sku393218.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts = b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts new file mode 100644 index 000000000000..543dc3dd5324 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-chinchou.dtsi" + +/ { + model =3D "Google chinchou sku0 board"; + compatible =3D "google,chinchou-sku0", "google,chinchou-sku2", + "google,chinchou-sku4", "google,chinchou-sku5", + "google,chinchou", "mediatek,mt8186"; +}; + +&gpio_keys { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts = b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts new file mode 100644 index 000000000000..c53fd42b7488 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-chinchou.dtsi" + +/ { + model =3D "Google chinchou sku1/sku17 board"; + compatible =3D "google,chinchou-sku1", "google,chinchou-sku17", + "google,chinchou-sku3", "google,chinchou-sku6", + "google,chinchou-sku7", "google,chinchou-sku20", + "google,chinchou-sku22", "google,chinchou-sku23", + "mediatek,mt8186"; +}; + +&gpio_keys { + status =3D "disabled"; +}; + +&i2c1 { + i2c-scl-internal-delay-ns =3D <10000>; + + touchscreen: touchscreen@41 { + compatible =3D "ilitek,ili2901"; + reg =3D <0x41>; + interrupts-extended =3D <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&touchscreen_pins>; + reset-gpios =3D <&pio 60 GPIO_ACTIVE_LOW>; + vccio-supply =3D <&pp1800_tchscr_report_disable>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts= b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts new file mode 100644 index 000000000000..b6f8eb37c384 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-chinchou.dtsi" + +/ { + model =3D "Google chinchou sku16/sku2147483647 board"; + compatible =3D "google,chinchou-sku16", "google,chinchou-sku18", + "google,chinchou-sku19", "google,chinchou-sku21", + "mediatek,mt8186"; +}; + +&i2c1 { + i2c-scl-internal-delay-ns =3D <10000>; + + touchscreen: touchscreen@41 { + compatible =3D "ilitek,ili2901"; + reg =3D <0x41>; + interrupts-extended =3D <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&touchscreen_pins>; + reset-gpios =3D <&pio 60 GPIO_ACTIVE_LOW>; + vccio-supply =3D <&pp1800_tchscr_report_disable>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi b/ar= ch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi new file mode 100644 index 000000000000..1ecb51a00e53 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" + +/ { + /delete-node/ speaker-codec; + + pp1000_edpbrdg: regulator-pp1000-edpbrdg { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1000_edpbrdg"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_pp1000_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 29 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_z2>; + }; + + pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_edpbrdg_dx"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_pp1800_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 30 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6366_vio18_reg>; + }; + + pp3300_edp_dx: regulator-pp3300-edp-dx { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_edp_dx"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_pp3300_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 31 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_z2>; + }; + + pp1800_tchscr_report_disable: regulator-pp1800-tchscr-report-disable { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_tchscr_report_disable"; + pinctrl-names =3D "default"; + enable-active-low; + regulator-boot-on; + pinctrl-0 =3D <&touch_pin_report>; + gpio =3D <&pio 37 GPIO_ACTIVE_LOW>; + }; +}; + +&dsi_out { + remote-endpoint =3D <&anx7625_in>; +}; + +&i2c0 { + clock-frequency =3D <400000>; + + anx_bridge: anx7625@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&anx7625_pins>; + enable-gpios =3D <&pio 96 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&pio 98 GPIO_ACTIVE_HIGH>; + vdd10-supply =3D <&pp1000_edpbrdg>; + vdd18-supply =3D <&pp1800_edpbrdg_dx>; + vdd33-supply =3D <&pp3300_edp_dx>; + analogix,lane0-swing =3D /bits/ 8 <0x70 0x30>; + analogix,lane1-swing =3D /bits/ 8 <0x70 0x30>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + anx7625_in: endpoint { + remote-endpoint =3D <&dsi_out>; + data-lanes =3D <0 1 2 3>; + }; + }; + + port@1 { + reg =3D <1>; + + anx7625_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible =3D "edp-panel"; + power-supply =3D <&pp3300_disp_x>; + backlight =3D <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&anx7625_out>; + }; + }; + }; + }; + }; +}; + +&i2c2 { + /delete-node/ trackpad@15; + + touchpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + interrupts-extended =3D <&pio 11 IRQ_TYPE_LEVEL_LOW>; + post-power-on-delay-ms =3D <10>; + hid-descr-addr =3D <0x0001>; + vdd-supply =3D <&pp3300_s3>; + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency =3D <400000>; + /delete-node/ codec@1a; + + rt5650: rt5650@1a { + compatible =3D "realtek,rt5650"; + reg =3D <0x1a>; + avdd-supply =3D <&mt6366_vio18_reg>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rt1019p_pins_default>; + cbj-sleeve-gpio =3D <&pio 150 GPIO_ACTIVE_HIGH>; + interrupt-parent =3D <&pio>; + interrupts =3D <17 IRQ_TYPE_EDGE_BOTH>; + #sound-dai-cells =3D <0>; + realtek,dmic1-data-pin =3D <2>; + realtek,jd-mode =3D <2>; + }; +}; + +&i2c_tunnel { + /delete-node/ sbs-battery@b; + + battery: sbs-battery@f { + compatible =3D "sbs,sbs-battery"; + reg =3D <0xf>; + sbs,i2c-retry-count =3D <2>; + sbs,poll-retry-count =3D <1>; + }; +}; + +&keyboard_controller { + keypad,num-columns =3D <15>; + + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + MATRIX_KEY(0x00, 0x01, 0) /* T11 */ + MATRIX_KEY(0x01, 0x05, 0) /* T12 */ + >; + + linux,keymap =3D < + CROS_STD_MAIN_KEYMAP + MATRIX_KEY(0x00, 0x02, KEY_BACK) /* T1 */ + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) /* T2 */ + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) /* T3 */ + MATRIX_KEY(0x01, 0x02, KEY_SCALE) /* T4 */ + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) /* T5 */ + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) /* T6 */ + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) /* T7 */ + MATRIX_KEY(0x02, 0x09, KEY_MUTE) /* T8 */ + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) /* T9 */ + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) /* T10 */ + MATRIX_KEY(0x00, 0x01, KEY_MICMUTE) /* T11 */ + MATRIX_KEY(0x01, 0x05, KEY_CONTROLPANEL) /* T12 */ + MATRIX_KEY(0x03, 0x05, KEY_PREVIOUSSONG) /* T13 */ + MATRIX_KEY(0x00, 0x09, KEY_PLAYPAUSE) /* T14 */ + MATRIX_KEY(0x00, 0x0b, KEY_NEXTSONG) /* T15 */ + MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) /* Search*/ + MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL) /* Left Control*/ + MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT) /* Left ALT*/ + MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL) /* Right Control*/ + MATRIX_KEY(0x06, 0x0a, KEY_BACKSLASH) /* BACKSLASH*/ + >; +}; + +&mmc1_pins_default { + pins-clk { + drive-strength =3D ; + }; + + pins-cmd-dat { + drive-strength =3D ; + }; +}; + +&mmc1_pins_uhs { + pins-clk { + drive-strength =3D ; + }; + + pins-cmd-dat { + drive-strength =3D ; + }; +}; + +&pen_insert { + wakeup-event-action =3D ; +}; + +&pio { + anx7625_pins: anx7625-pins { + pins-int { + pinmux =3D ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux =3D ; + output-low; + }; + + pins-power-en { + pinmux =3D ; + output-low; + }; + }; + + en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins { + pins-vreg-en { + pinmux =3D ; + output-low; + }; + }; + + en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins { + pins-vreg-en { + pinmux =3D ; + output-low; + }; + }; + + en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins { + pins-vreg-en { + pinmux =3D ; + output-low; + }; + }; + + touch_pin_report: pin-report { + pinmux =3D ; + output-low; + }; +}; + +&sound { + compatible =3D "mediatek,mt8186-mt6366-rt5650-sound"; + mediatek,adsp =3D <&adsp>; + /delete-property/ audio-routing; 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Tue, 15 Oct 2024 05:26:31 -0700 (PDT) Received: from ubuntu.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392e8cdc7sm1592844a91.10.2024.10.15.05.26.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 05:26:31 -0700 (PDT) From: Zhengqiao Xia To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, hsinyi@chromium.org, rafal@milecki.pl, macpaul.lin@mediatek.com, sean.wang@mediatek.com, Zhengqiao Xia Subject: [PATCH v1 3/3] arm64: dts: mediatek: Add exton node for DP bridge Date: Tue, 15 Oct 2024 20:26:08 +0800 Message-Id: <20241015122608.24569-4-xiazhengqiao@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241015122608.24569-1-xiazhengqiao@huaqin.corp-partner.google.com> References: <20241015122608.24569-1-xiazhengqiao@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add exton node for DP bridge to make the display work properly. Signed-off-by: Zhengqiao Xia --- arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/= boot/dts/mediatek/mt8186-corsola.dtsi index 682c6ad2574d..943837f20377 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -424,6 +424,7 @@ ovdd-supply =3D <&mt6366_vsim2_reg>; pwr18-supply =3D <&pp1800_dpbrdg_dx>; reset-gpios =3D <&pio 177 GPIO_ACTIVE_HIGH>; + extcon =3D <&usbc_extcon>; =20 ports { #address-cells =3D <1>; @@ -1656,6 +1657,11 @@ try-power-role =3D "source"; }; }; + + usbc_extcon: extcon0 { + compatible =3D "google,extcon-usbc-cros-ec"; + google,usb-port-id =3D <0>; + }; }; }; =20 --=20 2.17.1