From nobody Wed Nov 27 02:44:42 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2B521D4154; Tue, 15 Oct 2024 12:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728993939; cv=none; b=eKzlW1rWAQt+cZp0CBTai1nftVhPWLcS/+oks+huiTCS6DuKUFqPPCvSzFtbuT3Ui1mt47bu62IFwAhBR0qz3RyulsDvM1HvRpSHdI1aOGpK16paw7uX6q6/4ppN4zarP2u+r7VdzyRJn65iwGyGtfuo4ie5b/wbxovFRBXx+xQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728993939; c=relaxed/simple; bh=yJwBOsx2FFF5UUXvkJc0NErh+4E988PPOj2Fqwi7sDs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EwEfrlMlkOpkNxD2kz4AxRqyngmWNljhC56rjc5oo4k5aPqcXq8JYxrb4cVYNZ0zVqHuK3nLVKAF0dIH90Cmtk0r3ZfHyujqyo0CHtlKQyrdPtjFobhB+9nXSl9c7y/XsUMltYye2Zd1dVUhVbMSmSD65bW8AF4JN/QnVsqBd9U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=CluNCIld; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="CluNCIld" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48ADCC4CECE; Tue, 15 Oct 2024 12:05:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1728993939; bh=yJwBOsx2FFF5UUXvkJc0NErh+4E988PPOj2Fqwi7sDs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CluNCIldZhji3lGI/SK2Kb18QD1TEU+GPvQktLsoeBqqPc76U/iVjDgcK4JNfaVP5 toCkHhmG2fivPddpKoJUCOmwI48lQQEg2ENs84YI3QvW/nnWSJEdInuURZ11z03XVT 3KHjDKWXFgnzM+eTDos70WLjBSJhFinVjf2WBP8Q= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Catalin Marinas , Will Deacon , Suzuki K Poulose , James Morse , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Anshuman Khandual , Mark Rutland , Sasha Levin Subject: [PATCH 5.15 560/691] arm64: Add Cortex-715 CPU part definition Date: Tue, 15 Oct 2024 13:28:28 +0200 Message-ID: <20241015112502.572209234@linuxfoundation.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241015112440.309539031@linuxfoundation.org> References: <20241015112440.309539031@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 5.15-stable review patch. If anyone has any objections, please let me know. Acked-by: Catalin Marinas ------------------ From: Anshuman Khandual [ Upstream commit 07e39e60bbf0ccd5f895568e1afca032193705c0 ] Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: James Morse Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Catalin Marinas Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/20221116140915.356601-2-anshuman.khandual@a= rm.com Signed-off-by: Will Deacon [ Mark: Trivial backport ] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 59f135b280a8a..75cbd3880b5c7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -82,6 +82,7 @@ #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A520 0xD80 #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B @@ -144,6 +145,7 @@ #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A510) #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A520) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A710) +#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A78C) --=20 2.43.0