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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, lftan.linux@gmai.com Subject: [PATCH net-next 3/4] net: stmmac: dwmac4: Receive Watchdog Timeout is not in abnormal interrupt summary Date: Tue, 15 Oct 2024 14:57:07 +0800 Message-ID: <20241015065708.3465151-4-leyfoon.tan@starfivetech.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241015065708.3465151-1-leyfoon.tan@starfivetech.com> References: <20241015065708.3465151-1-leyfoon.tan@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BJXPR01CA0067.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:12::34) To ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQZPR01MB0979:EE_|ZQZPR01MB1105:EE_ X-MS-Office365-Filtering-Correlation-Id: f3daca27-bfe6-4589-dd2f-08dcece6a94b X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|52116014|41320700013|38350700014; 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charset="utf-8" The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal Interrupt Summary (AIS). Move the RWT handling out of the AIS condition statement. From databook, the AIS is the logical OR of the following interrupt bits: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Fixes: 48863ce5940f ("stmmac: add DMA support for GMAC 4.xx") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_lib.c index 0d185e54eb7e..57c03d491774 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void= __iomem *ioaddr, x->rx_buf_unav_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_RPS)) x->rx_process_stopped_irq++; - if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) - x->rx_watchdog_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_ETI)) x->tx_early_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) { @@ -198,6 +196,10 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, voi= d __iomem *ioaddr, ret =3D tx_hard_error; } } + + if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) + x->rx_watchdog_irq++; + /* TX/RX NORMAL interrupts */ if (likely(intr_status & DMA_CHAN_STATUS_RI)) { u64_stats_update_begin(&stats->syncp); --=20 2.34.1