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Correct the _MASK and _SHIFT macros to use the appropriate mask and shift. Fixes: 35f74c0c5dce ("stmmac: add GMAC4 DMA/CORE Header File") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/eth= ernet/stmicro/stmmac/dwmac4.h index 93a78fd0737b..acbe5a027c85 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -389,8 +389,8 @@ static inline u32 mtl_chanx_base_addr(const struct dwma= c4_addrs *addrs, =20 #define MTL_OP_MODE_EHFC BIT(7) =20 -#define MTL_OP_MODE_RTC_MASK 0x18 -#define MTL_OP_MODE_RTC_SHIFT 3 +#define MTL_OP_MODE_RTC_MASK GENMASK(1, 0) +#define MTL_OP_MODE_RTC_SHIFT 0 =20 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) #define MTL_OP_MODE_RTC_64 0 --=20 2.34.1 From nobody Wed Nov 27 00:41:37 2024 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2103.outbound.protection.partner.outlook.cn [139.219.17.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDEF91CEADB; Tue, 15 Oct 2024 12:34:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.17.103 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728995661; cv=fail; b=lkI/EK6xIz1InjYGJJiZe+lXTaZeQdaaSGgaEXYxcKKj+U+egLNNuAMjy3Cp83L/q9kbyVBScNyk80y6b6PdOWPTbaBIxCtJcLPeIswERBiJG7Vivh8fi3GCkKeI3YhuCSKg0GmqCbZ4WsLvaKvHxdqaZdg9QeIzIjBpLKSUAq8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728995661; c=relaxed/simple; bh=iT2wgr2wM31RkT8f26iqfj2jdsdUVNCwTxf0kvAlRLw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=GtgQR88t77YLehDmVAp+eMtNhinmvyK2s4uwQKW+iER1ADriSp9jjDrNq6+3+ogiffai5jItOrsbPUsFkpQQfKgFLcrPcbKEjxbTBgI8MDnuuve/ZZ527i0hlwMQ4BgRlBSkDbf19cQfqc55bZtO5bUw79Vk6jKRPpuN8/Ya378= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.17.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UK43JSzZzdhYTdNvvIrIEqFcJdMyYRDiK62oNYXH2uTLr5gjhYdntzmXLNVBvm6DNKBajaKzUCBiDHLfkTrEwYRbyTSVYqqREpTAUfH0SyOo6WMYUx2n+VUVOBdcjwET0zyrkQKaD9+f/9ac9H84WBGShf0kNBLdjaI1x7RyyC3CYIimAXGxhJQc3/p7XMrYU01VOXDkm0dSbdYz6T4BEamrEZpnC4CbVU6RinR/gvrCMF1NTAmbWrrVtIsnDRhfMrmBgkvSMoXloy5ZJjDFjoEbrLfR/Z3J8ItEPMhk6Pf3FbmRjd8tlc9Dr0Xbi49HfiF2tAlFA7DsLMPPDXI0bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=H21ENuAQ3xhhwqJ2Csk3hLYVtlxsl1QHD1/8Vp4Qjww=; b=T1SdBtCQQB1+3RyU+woKxl7WPmu5JFjM2wvOXF+ZRFgGFo3+snoo7SYhTgaNu6rTnKUr0DRzBuOSJ7hypCGZYbMtCMdSMG3MYHzSHeKtzaENorIZInXRODbyXMKab2XLBzMyjzHxAzi2/SJgz8/bqsQEWD8LwPsk4vUfNc9uo/jA1s45Hw+OFm1MNCQ/m9ZSEBixgSY1iutNf+/ZtzjpKkVwF6Y+ZFQ44D/kJjFozxVtnJHIC+sg8z4tdQ+CxMfpXhU3H0zXBgq3vp4sIzPW1X6bb7k0BcWib9/7EKPW5wSeC3/0DlRU2i9BcvY3xklQLnSebr/MUOYkOKGQpnbPsw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) by ZQZPR01MB1105.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:9::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.20; Tue, 15 Oct 2024 06:57:39 +0000 Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095]) by ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095%4]) with mapi id 15.20.8048.013; Tue, 15 Oct 2024 06:57:39 +0000 From: Ley Foon Tan To: Alexandre Torgue , Jose Abreu Cc: "David S . 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charset="utf-8" In order to mask off the bits, we need to use the '~' operator to invert all the bits of _MASK and clear them. Fixes: 48863ce5940f ("stmmac: add DMA support for GMAC 4.xx") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_dma.c index e0165358c4ac..4e1b1bd98f68 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -266,7 +266,7 @@ static void dwmac4_dma_rx_chan_op_mode(struct stmmac_pr= iv *priv, } else { pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); mtl_rx_op &=3D ~MTL_OP_MODE_RSF; - mtl_rx_op &=3D MTL_OP_MODE_RTC_MASK; + mtl_rx_op &=3D ~MTL_OP_MODE_RTC_MASK; if (mode <=3D 32) mtl_rx_op |=3D MTL_OP_MODE_RTC_32; else if (mode <=3D 64) @@ -335,7 +335,7 @@ static void dwmac4_dma_tx_chan_op_mode(struct stmmac_pr= iv *priv, } else { pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); mtl_tx_op &=3D ~MTL_OP_MODE_TSF; - mtl_tx_op &=3D MTL_OP_MODE_TTC_MASK; + mtl_tx_op &=3D ~MTL_OP_MODE_TTC_MASK; /* Set the transmit threshold */ if (mode <=3D 32) mtl_tx_op |=3D MTL_OP_MODE_TTC_32; --=20 2.34.1 From nobody Wed Nov 27 00:41:37 2024 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2116.outbound.protection.partner.outlook.cn [139.219.146.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AB369474; Tue, 15 Oct 2024 07:29:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.116 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728977399; cv=fail; b=U5eDc9aag5gZo8GXRKDKvFGrl6ppedNd0YFal2BbP41q9p80v5SNrqngZ1tpio/ufrDUGQL2i2QCz5Ag7mPoKhrH54vn4Od9ul9drsMUqLFlxxPzLOXeQlh04rozV/Nd1GWyRQTZiXDIL+S2XCgl8Fbsysham5h1evni8z+v/rg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728977399; c=relaxed/simple; bh=XCLPmR0Le7fiiSbIqWvfFshIc15qkSSlQhSOMR74F4Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=PHYbk13BkXW8Zf+gEOkxSo35jMPjxHlekrZY4DKwObBjTlkhT0je+DZ1jzSg4eYAqy5fcwKLr1TKXDhcR+ae754CA3MRmEhENXtbQXRmTqWLyuXqjdKU5yCjY6e4KQXAIL6gbVGJ6sBZDmGlQt5YDarDmk5sPsxtAN7f5dErzkI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.146.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nMzZ4zfJoUmjI1WA39IFKga8wwOUGw7pE5gyJxVGDfFWqBE5+1mavK7mAinqpH8LB6XN1VwJ5XvVhpJaq/3mELUxF2vh9pczNppy2YfZvIVjynZSNxOZUdCfIl1nxj6qNwT3l9sxzu2P/zNDeQeYRaCTKEcSY8mXBPgY7uvS8amt6BeQFvRQCbC9euMq+LwkPobMs4vso55r8Yjil/Cbx6R/MeQUFgrhfpEJgazpNSVzYmWkxX59xeYPb0FDPRvWmukQkCK8dA0YJ3Pbivcl7rMqbIJ4w2ExByav3e2VUvGXDlDmqd8oK0L5AFuHdJC3Bfrfnuc6Pc2pl8dgDbbomA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iu4UJegdTlMh3TpMhAjavI1nxDebeKR67mjS+Twfsb8=; b=BQUmdV+tk++ipUyj4ylLzWMKn3j5W6g9x1AuUUNuEoZsQ+/DDELPZKKqF61gKpripi1qXlYhNZpeasJncwkyAIozY3W04VwUM/TCPfRm4njjsStTUHK9qSTIxHWUfQqLM8fOKn/CJyMYjAigR9psJbgZazRcD2qxnhBuEJ6Ltm6u+GZ5i02yiu/t5nITWQHONBQAZwcYYMUIHOMu+bzZwVBRQuBY4fAybfbPUjMmQbM8pDLNI/CLVwbZVbVIVYJ2x2qtERTl2f+6KvLZEAV+9QnHddNu5z/Ko4jR+s313bMN7xhqwN08cqsaQxyGyUDQ+dKv8krgX34Wf1aXEwrfMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) by ZQZPR01MB1105.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:9::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.20; Tue, 15 Oct 2024 06:57:40 +0000 Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095]) by ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095%4]) with mapi id 15.20.8048.013; Tue, 15 Oct 2024 06:57:40 +0000 From: Ley Foon Tan To: Alexandre Torgue , Jose Abreu Cc: "David S . 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charset="utf-8" The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal Interrupt Summary (AIS). Move the RWT handling out of the AIS condition statement. From databook, the AIS is the logical OR of the following interrupt bits: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Fixes: 48863ce5940f ("stmmac: add DMA support for GMAC 4.xx") Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_lib.c index 0d185e54eb7e..57c03d491774 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void= __iomem *ioaddr, x->rx_buf_unav_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_RPS)) x->rx_process_stopped_irq++; - if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) - x->rx_watchdog_irq++; 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charset="utf-8" Dump the DMA high address registers (upper 32-bit address). Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 ++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_dma.c index 4e1b1bd98f68..60cee7a06ba2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -203,8 +203,12 @@ static void _dwmac4_dump_dma_regs(struct stmmac_priv *= priv, readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel)); reg_space[DMA_CHAN_RX_CONTROL(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_TX_BASE_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_TX_BASE_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_RX_BASE_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_RX_BASE_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel)); reg_space[DMA_CHAN_TX_END_ADDR(default_addrs, channel) / 4] =3D @@ -225,8 +229,12 @@ static void _dwmac4_dump_dma_regs(struct stmmac_priv *= priv, readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel)); reg_space[DMA_CHAN_CUR_RX_DESC(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_CUR_TX_BUF_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel)); + reg_space[DMA_CHAN_CUR_RX_BUF_ADDR_HI(default_addrs, channel) / 4] =3D + readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel)); reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(default_addrs, channel) / 4] =3D readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel)); reg_space[DMA_CHAN_STATUS(default_addrs, channel) / 4] =3D diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net= /ethernet/stmicro/stmmac/dwmac4_dma.h index 17d9120db5fe..4f980dcd3958 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h @@ -127,7 +127,9 @@ static inline u32 dma_chanx_base_addr(const struct dwma= c4_addrs *addrs, #define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x)= + 0x3c) #define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x= 44) #define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x= 4c) +#define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, = x) + 0x50) #define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) = + 0x54) +#define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, = x) + 0x58) #define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) = + 0x5c) #define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60) =20 --=20 2.34.1