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Tue, 15 Oct 2024 14:17:36 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49FEHZOp024803 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 15 Oct 2024 14:17:35 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Oct 2024 07:17:29 -0700 From: Luo Jie Date: Tue, 15 Oct 2024 22:16:54 +0800 Subject: [PATCH v4 4/4] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241015-qcom_ipq_cmnpll-v4-4-27817fbe3505@quicinc.com> References: <20241015-qcom_ipq_cmnpll-v4-0-27817fbe3505@quicinc.com> In-Reply-To: <20241015-qcom_ipq_cmnpll-v4-0-27817fbe3505@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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It in-turn supplies fixed rate output clocks to the hardware blocks that provide ethernet functions such as PPE (Packet Process Engine) and connected switch or PHY, and to GCC. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 +++++++++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/= boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..77e1e42083f3 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -3,7 +3,7 @@ * IPQ9574 RDP board common device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 /dts-v1/; @@ -164,6 +164,10 @@ &usb3 { status =3D "okay"; }; =20 +&cmn_pll_ref_clk { + clock-frequency =3D <48000000>; +}; + &xo_board_clk { clock-frequency =3D <24000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 14c7b3a78442..93f66bb83c5a 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,10 +3,11 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 #include +#include #include #include #include @@ -19,6 +20,11 @@ / { #size-cells =3D <2>; =20 clocks { + cmn_pll_ref_clk: cmn-pll-ref-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -243,6 +249,18 @@ mdio: mdio@90000 { status =3D "disabled"; }; =20 + cmn_pll: clock-controller@9b000 { + compatible =3D "qcom,ipq9574-cmn-pll"; + reg =3D <0x0009b000 0x800>; + clocks =3D <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names =3D "ref", "ahb", "sys"; + #clock-cells =3D <1>; + assigned-clocks =3D <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 =3D /bits/ 64 <12000000000>; + }; + qfprom: efuse@a4000 { compatible =3D "qcom,ipq9574-qfprom", "qcom,qfprom"; reg =3D <0x000a4000 0x5a1>; --=20 2.34.1