From nobody Wed Nov 27 04:31:15 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3353B1C7617; Mon, 14 Oct 2024 15:25:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728919503; cv=none; b=nJynzR0E99ULzwNADRGafMxPOdR8/wATGYQgFS5fHEo+2TXFbTWCAZKhHhGnDMfGWc45djuOXzuMsAQrvQCPZ1L4fPB6BGuZ8ZO5q1oCAZ+7tzCqpbQ6AH9ECo20kY91zdtR8geXJ8vJTP58B126WmbFYtyYlbxeHfyFmBDyYJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728919503; c=relaxed/simple; bh=1GoaPfLQ84iWGdlMtTwtwD5xjUpqEJmFCGIhxXHA0q0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kMm3pZkILHYfewCpchaYLkPwF9bWHxS/RFQMfTY2088l9K2Cu138QXmJSe17hHEuCJUoVW9i08xNtuTTyz+XBHugq9vfL6Nto6v5MQWM7t1SPsK9Ymk+sL3c+5S0uxxxuOAUS9WLjDR+Q79lwxaZeSEP/UYJcQ63w25TxcCf3eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=QeI6S4SU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="QeI6S4SU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3FFD7C4CEC3; Mon, 14 Oct 2024 15:25:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1728919502; bh=1GoaPfLQ84iWGdlMtTwtwD5xjUpqEJmFCGIhxXHA0q0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QeI6S4SUhYpSgimP4UGiLNrCdTShZ2vhFcqoiR3Q47fh5YlBhE0U49sfN98EoUztx vq21kJImqh9R3WTPuT99R7l9sxA5jhR02oaeEgG80ew8nvhDTEXtmYeD4KZ4zMQckK d1UQitE9ZdU0Y519GEqfyN6x95GFAQ1rG7VLSQX0= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Catalin Marinas , Will Deacon , Suzuki K Poulose , James Morse , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Anshuman Khandual , Mark Rutland , Sasha Levin Subject: [PATCH 6.1 624/798] arm64: Add Cortex-715 CPU part definition Date: Mon, 14 Oct 2024 16:19:38 +0200 Message-ID: <20241014141242.554119006@linuxfoundation.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241014141217.941104064@linuxfoundation.org> References: <20241014141217.941104064@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 6.1-stable review patch. If anyone has any objections, please let me know. Acked-by: Catalin Marinas ------------------ From: Anshuman Khandual [ Upstream commit 07e39e60bbf0ccd5f895568e1afca032193705c0 ] Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: James Morse Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Catalin Marinas Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/20221116140915.356601-2-anshuman.khandual@a= rm.com Signed-off-by: Will Deacon [ Mark: Trivial backport ] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index a0a028a6b9670..9916346948ba2 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -82,6 +82,7 @@ #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A520 0xD80 #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B @@ -156,6 +157,7 @@ #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A510) #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A520) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A710) +#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A78C) --=20 2.43.0