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charset="utf-8" From: Stefan Eichenberger According to the i.MX8M Mini reference manual chapter "16.1.4.2 Generation of Start" it is only necessary to poll for bus busy and arbitration lost in multi master mode. This helps to avoid rescheduling while the i2c bus is busy and avoids SMBus devices to timeout. For backward compatibility, the single-master property needs to be explicitly set to disable the bus busy polling. Signed-off-by: Stefan Eichenberger Reviewed-by: Frank Li Acked-by: Oleksij Rempel --- @Frank and Oleksij: I kept your tags even though I made multi-master the new default. Let me know if you have any objections. drivers/i2c/busses/i2c-imx.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index 98539313cbc97..d697abd2459d4 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -216,6 +216,8 @@ struct imx_i2c_struct { struct i2c_client *slave; enum i2c_slave_event last_slave_event; =20 + bool multi_master; + /* For checking slave events. */ spinlock_t slave_lock; struct hrtimer slave_timer; @@ -481,6 +483,9 @@ static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_= imx, int for_busy, bool a unsigned long orig_jiffies =3D jiffies; unsigned int temp; =20 + if (!i2c_imx->multi_master) + return 0; + while (1) { temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); =20 @@ -540,8 +545,8 @@ static int i2c_imx_trx_complete(struct imx_i2c_struct *= i2c_imx, bool atomic) return -ETIMEDOUT; } =20 - /* check for arbitration lost */ - if (i2c_imx->i2csr & I2SR_IAL) { + /* In multi-master mode check for arbitration lost */ + if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) { dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 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Mon, 14 Oct 2024 06:16:43 -0700 (PDT) Received: from eichest-laptop.lan ([2a02:168:af72:0:d130:f8ef:c6c1:55ee]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-430d748d42fsm153420425e9.43.2024.10.14.06.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 06:16:42 -0700 (PDT) From: Stefan Eichenberger To: o.rempel@pengutronix.de, kernel@pengutronix.de, andi.shyti@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, francesco.dolcini@toradex.com, l.stach@pengutronix.de, arnd@arndb.de, Frank.Li@nxp.com Cc: linux-i2c@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan Eichenberger Subject: [PATCH v5 2/3] i2c: imx: separate atomic, dma and non-dma use case Date: Mon, 14 Oct 2024 15:15:13 +0200 Message-ID: <20241014131635.205489-3-eichest@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014131635.205489-1-eichest@gmail.com> References: <20241014131635.205489-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Eichenberger Separate the atomic, dma and non-dma use case as a preparation step for moving the non-dma use case to the isr to avoid rescheduling while a transfer is in progress. Signed-off-by: Stefan Eichenberger Reviewed-by: Frank Li Acked-by: Oleksij Rempel --- drivers/i2c/busses/i2c-imx.c | 107 +++++++++++++++++++++++------------ 1 file changed, 70 insertions(+), 37 deletions(-) diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index d697abd2459d4..e0821332c439a 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -1011,6 +1011,43 @@ static int i2c_imx_dma_write(struct imx_i2c_struct *= i2c_imx, return i2c_imx_acked(i2c_imx); } =20 +static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx, + struct i2c_msg *msgs, bool atomic, + bool use_dma) +{ + int result; + unsigned int temp =3D 0; + + /* write slave address */ + imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); + result =3D i2c_imx_trx_complete(i2c_imx, atomic); + if (result) + return result; + result =3D i2c_imx_acked(i2c_imx); + if (result) + return result; + + dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); + + /* setup bus to read data */ + temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); + temp &=3D ~I2CR_MTX; + + /* + * Reset the I2CR_TXAK flag initially for SMBus block read since the + * length is unknown + */ + if (msgs->len - 1) + temp &=3D ~I2CR_TXAK; + if (use_dma) + temp |=3D I2CR_DMAEN; + + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ + + return 0; +} + static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) { @@ -1021,6 +1058,11 @@ static int i2c_imx_dma_read(struct imx_i2c_struct *i= 2c_imx, struct imx_i2c_dma *dma =3D i2c_imx->dma; struct device *dev =3D &i2c_imx->adapter.dev; =20 + result =3D i2c_imx_prepare_read(i2c_imx, msgs, false, true); + if (result) + return result; + + dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); =20 dma->chan_using =3D dma->chan_rx; dma->dma_transfer_dir =3D DMA_DEV_TO_MEM; @@ -1131,50 +1173,24 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c= _imx, struct i2c_msg *msgs, return 0; } =20 +static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, struct i2c= _msg *msgs) +{ + return i2c_imx_write(i2c_imx, msgs, true); +} + static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *ms= gs, bool is_lastmsg, bool atomic) { int i, result; unsigned int temp; int block_data =3D msgs->flags & I2C_M_RECV_LEN; - int use_dma =3D i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE && - msgs->len >=3D DMA_THRESHOLD && !block_data; =20 - dev_dbg(&i2c_imx->adapter.dev, - "<%s> write slave address: addr=3D0x%x\n", - __func__, i2c_8bit_addr_from_msg(msgs)); - - /* write slave address */ - imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); - result =3D i2c_imx_trx_complete(i2c_imx, atomic); + result =3D i2c_imx_prepare_read(i2c_imx, msgs, atomic, false); if (result) return result; - result =3D i2c_imx_acked(i2c_imx); - if (result) - return result; - - dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); - - /* setup bus to read data */ - temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); - temp &=3D ~I2CR_MTX; - - /* - * Reset the I2CR_TXAK flag initially for SMBus block read since the - * length is unknown - */ - if ((msgs->len - 1) || block_data) - temp &=3D ~I2CR_TXAK; - if (use_dma) - temp |=3D I2CR_DMAEN; - imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); - imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ =20 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); =20 - if (use_dma) - return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); - /* read data */ for (i =3D 0; i < msgs->len; i++) { u8 len =3D 0; @@ -1241,6 +1257,12 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_i= mx, struct i2c_msg *msgs, return 0; } =20 +static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, struct i2c_= msg *msgs, + bool is_lastmsg) +{ + return i2c_imx_read(i2c_imx, msgs, is_lastmsg, true); +} + static int i2c_imx_xfer_common(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, bool atomic) { @@ -1248,6 +1270,7 @@ static int i2c_imx_xfer_common(struct i2c_adapter *ad= apter, int result; bool is_lastmsg =3D false; struct imx_i2c_struct *i2c_imx =3D i2c_get_adapdata(adapter); + int use_dma =3D 0; =20 /* Start I2C transfer */ result =3D i2c_imx_start(i2c_imx, atomic); @@ -1300,15 +1323,25 @@ static int i2c_imx_xfer_common(struct i2c_adapter *= adapter, (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), (temp & I2SR_RXAK ? 1 : 0)); #endif + + use_dma =3D i2c_imx->dma && msgs[i].len >=3D DMA_THRESHOLD && + msgs[i].flags & I2C_M_DMA_SAFE; if (msgs[i].flags & I2C_M_RD) { - result =3D i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic); + int block_data =3D msgs->flags & I2C_M_RECV_LEN; + + if (atomic) + result =3D i2c_imx_atomic_read(i2c_imx, &msgs[i], is_lastmsg); + else if (use_dma && !block_data) + result =3D i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg); + else + result =3D i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, false); } else { - if (!atomic && - i2c_imx->dma && msgs[i].len >=3D DMA_THRESHOLD && - msgs[i].flags & I2C_M_DMA_SAFE) + if (atomic) + result =3D i2c_imx_atomic_write(i2c_imx, &msgs[i]); + else if (use_dma) result =3D i2c_imx_dma_write(i2c_imx, &msgs[i]); else - result =3D i2c_imx_write(i2c_imx, &msgs[i], atomic); + result =3D i2c_imx_write(i2c_imx, &msgs[i], false); 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charset="utf-8" From: Stefan Eichenberger We are experiencing a problem with the i.MX I2C controller when communicating with SMBus devices. We are seeing devices time-out because the time between sending/receiving two bytes is too long, and the SMBus device returns to the idle state. This happens because the i.MX I2C controller sends and receives byte by byte. When a byte is sent or received, we get an interrupt and can send or receive the next byte. The current implementation sends a byte and then waits for an event generated by the interrupt subroutine. After the event is received, the next byte is sent and we wait again. This waiting allows the scheduler to reschedule other tasks, with the disadvantage that we may not send the next byte for a long time because the send task is not immediately scheduled. For example, if the rescheduling takes more than 25ms, this can cause SMBus devices to timeout and communication to fail. This patch changes the behavior so that we do not reschedule the send/receive task, but instead send or receive the next byte in the interrupt subroutine. This prevents rescheduling and drastically reduces the time between sending/receiving bytes. The cost in the interrupt subroutine is relatively small, we check what state we are in and then send/receive the next byte. Before we had to call wake_up, which is even less expensive. However, we also had to do some scheduling, which increased the overall cost compared to the new solution. The wake_up function to wake up the send/receive task is now only called when an error occurs or when the transfer is complete. Signed-off-by: Stefan Eichenberger Acked-by: Oleksij Rempel --- drivers/i2c/busses/i2c-imx.c | 272 ++++++++++++++++++++++++++++++++--- 1 file changed, 249 insertions(+), 23 deletions(-) diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index e0821332c439a..44749e594ddb6 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -197,6 +197,17 @@ struct imx_i2c_dma { enum dma_data_direction dma_data_dir; }; =20 +enum imx_i2c_state { + IMX_I2C_STATE_DONE, + IMX_I2C_STATE_FAILED, + IMX_I2C_STATE_WRITE, + IMX_I2C_STATE_DMA, + IMX_I2C_STATE_READ, + IMX_I2C_STATE_READ_CONTINUE, + IMX_I2C_STATE_READ_BLOCK_DATA, + IMX_I2C_STATE_READ_BLOCK_DATA_LEN, +}; + struct imx_i2c_struct { struct i2c_adapter adapter; struct clk *clk; @@ -216,6 +227,12 @@ struct imx_i2c_struct { struct i2c_client *slave; enum i2c_slave_event last_slave_event; =20 + struct i2c_msg *msg; + unsigned int msg_buf_idx; + int isr_result; + bool is_lastmsg; + enum imx_i2c_state state; + bool multi_master; =20 /* For checking slave events. */ @@ -908,11 +925,156 @@ static int i2c_imx_unreg_slave(struct i2c_client *cl= ient) return ret; } =20 +static inline int i2c_imx_isr_acked(struct imx_i2c_struct *i2c_imx) +{ + i2c_imx->isr_result =3D 0; + + if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { + i2c_imx->state =3D IMX_I2C_STATE_FAILED; + i2c_imx->isr_result =3D -ENXIO; + wake_up(&i2c_imx->queue); + } + + return i2c_imx->isr_result; +} + +static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx) +{ + int result; + + result =3D i2c_imx_isr_acked(i2c_imx); + if (result) + return result; + + if (i2c_imx->msg->len =3D=3D i2c_imx->msg_buf_idx) + return 0; + + imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX= _I2C_I2DR); + + return 1; +} + +static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx) +{ + int result; + unsigned int temp; + + result =3D i2c_imx_isr_acked(i2c_imx); + if (result) + return result; + + /* setup bus to read data */ + temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); + temp &=3D ~I2CR_MTX; + if (i2c_imx->msg->len - 1) + temp &=3D ~I2CR_TXAK; + + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ + + return 0; +} + +static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_im= x) +{ + unsigned int temp; + + if ((i2c_imx->msg->len - 1) =3D=3D i2c_imx->msg_buf_idx) { + if (i2c_imx->is_lastmsg) { + /* + * It must generate STOP before read I2DR to prevent + * controller from generating another clock cycle + */ + temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); + if (!(temp & I2CR_MSTA)) + i2c_imx->stopped =3D 1; + temp &=3D ~(I2CR_MSTA | I2CR_MTX); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); + } else { + /* + * For i2c master receiver repeat restart operation like: + * read -> repeat MSTA -> read/write + * The controller must set MTX before read the last byte in + * the first read operation, otherwise the first read cost + * one extra clock cycle. + */ + temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); + temp |=3D I2CR_MTX; + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); + } + } else if (i2c_imx->msg_buf_idx =3D=3D (i2c_imx->msg->len - 2)) { + temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); + temp |=3D I2CR_TXAK; + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); + } + + i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] =3D imx_i2c_read_reg(i2c_imx, I= MX_I2C_I2DR); +} + +static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *= i2c_imx) +{ + u8 len =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); + + if (len =3D=3D 0 || len > I2C_SMBUS_BLOCK_MAX) { + i2c_imx->isr_result =3D -EPROTO; + i2c_imx->state =3D IMX_I2C_STATE_FAILED; + wake_up(&i2c_imx->queue); + } + i2c_imx->msg->len +=3D len; +} + static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsi= gned int status) { - /* save status register */ - i2c_imx->i2csr =3D status; - wake_up(&i2c_imx->queue); + /* + * This state machine handles I2C reception and transmission in non-DMA + * mode. We must process all the data in the ISR to reduce the delay + * between two consecutive messages. If the data is not processed in + * the ISR, SMBus devices may timeout, leading to a bus error. + */ + switch (i2c_imx->state) { + case IMX_I2C_STATE_DMA: + i2c_imx->i2csr =3D status; + wake_up(&i2c_imx->queue); + break; + + case IMX_I2C_STATE_READ: + if (i2c_imx_isr_read(i2c_imx)) + break; + i2c_imx->state =3D IMX_I2C_STATE_READ_CONTINUE; + break; + + case IMX_I2C_STATE_READ_CONTINUE: + i2c_imx_isr_read_continue(i2c_imx); + if (i2c_imx->msg_buf_idx =3D=3D i2c_imx->msg->len) { + i2c_imx->state =3D IMX_I2C_STATE_DONE; + wake_up(&i2c_imx->queue); + } + break; + + case IMX_I2C_STATE_READ_BLOCK_DATA: + if (i2c_imx_isr_read(i2c_imx)) + break; + i2c_imx->state =3D IMX_I2C_STATE_READ_BLOCK_DATA_LEN; + break; + + case IMX_I2C_STATE_READ_BLOCK_DATA_LEN: + i2c_imx_isr_read_block_data_len(i2c_imx); + i2c_imx->state =3D IMX_I2C_STATE_READ_CONTINUE; + break; + + case IMX_I2C_STATE_WRITE: + if (i2c_imx_isr_write(i2c_imx)) + break; + i2c_imx->state =3D IMX_I2C_STATE_DONE; + wake_up(&i2c_imx->queue); + break; + + default: + i2c_imx->i2csr =3D status; + i2c_imx->state =3D IMX_I2C_STATE_FAILED; + i2c_imx->isr_result =3D -EINVAL; + wake_up(&i2c_imx->queue); + } =20 return IRQ_HANDLED; } @@ -959,6 +1121,8 @@ static int i2c_imx_dma_write(struct imx_i2c_struct *i2= c_imx, struct imx_i2c_dma *dma =3D i2c_imx->dma; struct device *dev =3D &i2c_imx->adapter.dev; =20 + i2c_imx->state =3D IMX_I2C_STATE_DMA; + dma->chan_using =3D dma->chan_tx; dma->dma_transfer_dir =3D DMA_MEM_TO_DEV; dma->dma_data_dir =3D DMA_TO_DEVICE; @@ -1012,15 +1176,14 @@ static int i2c_imx_dma_write(struct imx_i2c_struct = *i2c_imx, } =20 static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx, - struct i2c_msg *msgs, bool atomic, - bool use_dma) + struct i2c_msg *msgs, bool use_dma) { int result; unsigned int temp =3D 0; =20 /* write slave address */ imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); - result =3D i2c_imx_trx_complete(i2c_imx, atomic); + result =3D i2c_imx_trx_complete(i2c_imx, !use_dma); if (result) return result; result =3D i2c_imx_acked(i2c_imx); @@ -1058,7 +1221,9 @@ static int i2c_imx_dma_read(struct imx_i2c_struct *i2= c_imx, struct imx_i2c_dma *dma =3D i2c_imx->dma; struct device *dev =3D &i2c_imx->adapter.dev; =20 - result =3D i2c_imx_prepare_read(i2c_imx, msgs, false, true); + i2c_imx->state =3D IMX_I2C_STATE_DMA; + + result =3D i2c_imx_prepare_read(i2c_imx, msgs, true); if (result) return result; =20 @@ -1139,8 +1304,8 @@ static int i2c_imx_dma_read(struct imx_i2c_struct *i2= c_imx, return 0; } =20 -static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *m= sgs, - bool atomic) +static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, + struct i2c_msg *msgs) { int i, result; =20 @@ -1149,7 +1314,7 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c_i= mx, struct i2c_msg *msgs, =20 /* write slave address */ imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); - result =3D i2c_imx_trx_complete(i2c_imx, atomic); + result =3D i2c_imx_trx_complete(i2c_imx, true); if (result) return result; result =3D i2c_imx_acked(i2c_imx); @@ -1163,7 +1328,7 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c_i= mx, struct i2c_msg *msgs, "<%s> write byte: B%d=3D0x%X\n", __func__, i, msgs->buf[i]); imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); - result =3D i2c_imx_trx_complete(i2c_imx, atomic); + result =3D i2c_imx_trx_complete(i2c_imx, true); if (result) return result; result =3D i2c_imx_acked(i2c_imx); @@ -1173,19 +1338,44 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c= _imx, struct i2c_msg *msgs, return 0; } =20 -static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, struct i2c= _msg *msgs) +static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *m= sgs) { - return i2c_imx_write(i2c_imx, msgs, true); + dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=3D0x%x\n", + __func__, i2c_8bit_addr_from_msg(msgs)); + + i2c_imx->state =3D IMX_I2C_STATE_WRITE; + i2c_imx->msg =3D msgs; + i2c_imx->msg_buf_idx =3D 0; + + /* + * By writing the device address we start the state machine in the ISR. + * The ISR will report when it is done or when it fails. + */ + imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); + wait_event_timeout(i2c_imx->queue, + i2c_imx->state =3D=3D IMX_I2C_STATE_DONE || + i2c_imx->state =3D=3D IMX_I2C_STATE_FAILED, + (msgs->len + 1) * HZ / 10); + if (i2c_imx->state =3D=3D IMX_I2C_STATE_FAILED) { + dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n", + __func__, i2c_imx->isr_result); + return i2c_imx->isr_result; + } + if (i2c_imx->state !=3D IMX_I2C_STATE_DONE) { + dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__); + return -ETIMEDOUT; + } + return 0; } =20 -static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *ms= gs, - bool is_lastmsg, bool atomic) +static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, + struct i2c_msg *msgs, bool is_lastmsg) { int i, result; unsigned int temp; int block_data =3D msgs->flags & I2C_M_RECV_LEN; =20 - result =3D i2c_imx_prepare_read(i2c_imx, msgs, atomic, false); + result =3D i2c_imx_prepare_read(i2c_imx, msgs, false); if (result) return result; =20 @@ -1195,7 +1385,7 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_im= x, struct i2c_msg *msgs, for (i =3D 0; i < msgs->len; i++) { u8 len =3D 0; =20 - result =3D i2c_imx_trx_complete(i2c_imx, atomic); + result =3D i2c_imx_trx_complete(i2c_imx, true); if (result) return result; /* @@ -1226,7 +1416,7 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_im= x, struct i2c_msg *msgs, temp &=3D ~(I2CR_MSTA | I2CR_MTX); imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); if (!i2c_imx->stopped) - i2c_imx_bus_busy(i2c_imx, 0, atomic); + i2c_imx_bus_busy(i2c_imx, 0, true); } else { /* * For i2c master receiver repeat restart operation like: @@ -1257,10 +1447,46 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_= imx, struct i2c_msg *msgs, return 0; } =20 -static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, struct i2c_= msg *msgs, - bool is_lastmsg) +static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *ms= gs, + bool is_lastmsg) { - return i2c_imx_read(i2c_imx, msgs, is_lastmsg, true); + int block_data =3D msgs->flags & I2C_M_RECV_LEN; + + dev_dbg(&i2c_imx->adapter.dev, + "<%s> write slave address: addr=3D0x%x\n", + __func__, i2c_8bit_addr_from_msg(msgs)); + + i2c_imx->is_lastmsg =3D is_lastmsg; + + if (block_data) + i2c_imx->state =3D IMX_I2C_STATE_READ_BLOCK_DATA; + else + i2c_imx->state =3D IMX_I2C_STATE_READ; + i2c_imx->msg =3D msgs; + i2c_imx->msg_buf_idx =3D 0; + + /* + * By writing the device address we start the state machine in the ISR. + * The ISR will report when it is done or when it fails. + */ + imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); + wait_event_timeout(i2c_imx->queue, + i2c_imx->state =3D=3D IMX_I2C_STATE_DONE || + i2c_imx->state =3D=3D IMX_I2C_STATE_FAILED, + (msgs->len + 1) * HZ / 10); + if (i2c_imx->state =3D=3D IMX_I2C_STATE_FAILED) { + dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n", + __func__, i2c_imx->isr_result); + return i2c_imx->isr_result; + } + if (i2c_imx->state !=3D IMX_I2C_STATE_DONE) { + dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__); + return -ETIMEDOUT; + } + if (!i2c_imx->stopped) + return i2c_imx_bus_busy(i2c_imx, 0, false); + + return 0; } =20 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, @@ -1334,14 +1560,14 @@ static int i2c_imx_xfer_common(struct i2c_adapter *= adapter, else if (use_dma && !block_data) result =3D i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg); else - result =3D i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, false); + result =3D i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); } else { if (atomic) result =3D i2c_imx_atomic_write(i2c_imx, &msgs[i]); else if (use_dma) result =3D i2c_imx_dma_write(i2c_imx, &msgs[i]); else - result =3D i2c_imx_write(i2c_imx, &msgs[i], false); + result =3D i2c_imx_write(i2c_imx, &msgs[i]); } if (result) goto fail0; --=20 2.43.0