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Mon, 14 Oct 2024 13:07:36 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id CNT6LZgXDWcqTwAAD6G6ig (envelope-from ); Mon, 14 Oct 2024 13:07:36 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v3 05/11] PCI: brcmstb: Enable external MSI-X if available Date: Mon, 14 Oct 2024 16:07:04 +0300 Message-ID: <20241014130710.413-6-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014130710.413-1-svarbanov@suse.de> References: <20241014130710.413-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: D24131FE57 X-Spam-Score: -1.51 X-Rspamd-Action: no action X-Spamd-Result: default: False [-1.51 / 50.00]; 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charset="utf-8" On RPi5 there is an external MIP MSI-X interrupt controller which can handle up to 64 interrupts. Signed-off-by: Stanimir Varbanov --- v2 -> v3: - No changes drivers/pci/controller/pcie-brcmstb.c | 63 +++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index b0ef2f31914d..b76c16287f37 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1323,6 +1323,52 @@ static int brcm_pcie_start_link(struct brcm_pcie *pc= ie) return 0; } =20 +static int brcm_pcie_enable_external_msix(struct brcm_pcie *pcie, + struct device_node *msi_np) +{ + struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS]; + u64 msi_pci_addr, msi_phys_addr; + struct resource r; + int mip_bar, ret; + u32 val, reg; + + ret =3D of_property_read_reg(msi_np, 1, &msi_pci_addr, NULL); + if (ret) + return ret; + + ret =3D of_address_to_resource(msi_np, 0, &r); + if (ret) + return ret; + + msi_phys_addr =3D r.start; + + /* Find free inbound window for MIP access */ + mip_bar =3D brcm_pcie_get_inbound_wins(pcie, inbound_wins); + if (mip_bar < 0) + return mip_bar; + + mip_bar +=3D 1; + reg =3D brcm_bar_reg_offset(mip_bar); + + val =3D lower_32_bits(msi_pci_addr); + val |=3D brcm_pcie_encode_ibar_size(SZ_4K); + writel(val, pcie->base + reg); + + val =3D upper_32_bits(msi_pci_addr); + writel(val, pcie->base + reg + 4); + + reg =3D brcm_ubus_reg_offset(mip_bar); + + val =3D lower_32_bits(msi_phys_addr); + val |=3D PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK; + writel(val, pcie->base + reg); + + val =3D upper_32_bits(msi_phys_addr); + writel(val, pcie->base + reg + 4); + + return 0; +} + static const char * const supplies[] =3D { "vpcie3v3", "vpcie3v3aux", @@ -1888,11 +1934,20 @@ static int brcm_pcie_probe(struct platform_device *= pdev) goto fail; } =20 - msi_np =3D of_parse_phandle(pcie->np, "msi-parent", 0); - if (pci_msi_enabled() && msi_np =3D=3D pcie->np) { - ret =3D brcm_pcie_enable_msi(pcie); + if (pci_msi_enabled()) { + msi_np =3D of_parse_phandle(pcie->np, "msi-parent", 0); + const char *str; + + if (msi_np =3D=3D pcie->np) { + str =3D "internal MSI"; + ret =3D brcm_pcie_enable_msi(pcie); + } else { + str =3D "external MSI-X"; + ret =3D brcm_pcie_enable_external_msix(pcie, msi_np); + } + if (ret) { - dev_err(pcie->dev, "probe of internal MSI failed"); + dev_err(pcie->dev, "enable of %s failed\n", str); goto fail; } } --=20 2.43.0