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Signed-off-by: Fei Shao --- Changes in v4: - Squash following patch to update MERGE alias IDs from 0-4 to 1-5: https://lore.kernel.org/all/20241014094622.1720289-1-fshao@chromium.org/ arch/arm64/boot/dts/mediatek/mt8188.dtsi | 298 +++++++++++++++++++++++ 1 file changed, 298 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 09556225751e..3345a2adc0fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -24,9 +24,32 @@ / { #size-cells =3D <2>; =20 aliases { + ethdr0 =3D ðdr0; gce0 =3D &gce0; gce1 =3D &gce1; + merge1 =3D &merge1; + merge2 =3D &merge2; + merge3 =3D &merge3; + merge4 =3D &merge4; + merge5 =3D &merge5; mutex0 =3D &mutex0; + mutex1 =3D &mutex1; + padding0 =3D &padding0; + padding1 =3D &padding1; + padding2 =3D &padding2; + padding3 =3D &padding3; + padding4 =3D &padding4; + padding5 =3D &padding5; + padding6 =3D &padding6; + padding7 =3D &padding7; + vdo1-rdma0 =3D &vdo1_rdma0; + vdo1-rdma1 =3D &vdo1_rdma1; + vdo1-rdma2 =3D &vdo1_rdma2; + vdo1-rdma3 =3D &vdo1_rdma3; + vdo1-rdma4 =3D &vdo1_rdma4; + vdo1-rdma5 =3D &vdo1_rdma5; + vdo1-rdma6 =3D &vdo1_rdma6; + vdo1-rdma7 =3D &vdo1_rdma7; }; =20 cpus { @@ -2532,6 +2555,16 @@ vdosys1: syscon@1c100000 { mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0 0x1000>; }; =20 + mutex1: mutex@1c101000 { + compatible =3D "mediatek,mt8188-disp-mutex"; + reg =3D <0 0x1c101000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_DISP_MUTEX>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; + mediatek,gce-events =3D ; + }; + larb2: smi@1c102000 { compatible =3D "mediatek,mt8188-smi-larb"; reg =3D <0 0x1c102000 0 0x1000>; @@ -2553,5 +2586,270 @@ larb3: smi@1c103000 { mediatek,larb-id =3D ; mediatek,smi =3D <&vpp_smi_common>; }; + + vdo1_rdma0: rdma@1c104000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c104000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: rdma@1c105000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c105000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA1>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: rdma@1c106000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c106000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA2>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: rdma@1c107000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c107000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA3>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: rdma@1c108000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c108000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA4>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: rdma@1c109000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c109000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA5>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: rdma@1c10a000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c10a000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA6>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: rdma@1c10b000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c10b000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA7>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge1: merge@1c10c000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10c000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute; + }; + + merge2: merge@1c10d000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute; + }; + + merge3: merge@1c10e000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10e000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute; + }; + + merge4: merge@1c10f000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10f000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute; + }; + + merge5: merge@1c110000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c110000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en; + }; + + ethdr0: ethdr@1c114000 { + compatible =3D "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethd= r"; + reg =3D <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names =3D "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + + clocks =3D <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names =3D "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; + + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, + <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; + + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + }; + + padding0: padding@1c11d000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + + padding1: padding@1c11e000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11e000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING1>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; + }; + + padding2: padding@1c11f000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11f000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING2>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; + }; + + padding3: padding@1c120000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c120000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING3>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; + }; + + padding4: padding@1c121000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c121000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING4>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; + }; + + padding5: padding@1c122000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c122000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING5>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; + }; + + padding6: padding@1c123000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c123000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING6>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; + }; + + padding7: padding@1c124000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c124000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING7>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; + }; }; }; --=20 2.47.0.rc1.288.g06298d1525-goog