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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241014-x1e80100-qcp-sdhc-v2-1-868e70a825e0@linaro.org> References: <20241014-x1e80100-qcp-sdhc-v2-0-868e70a825e0@linaro.org> In-Reply-To: <20241014-x1e80100-qcp-sdhc-v2-0-868e70a825e0@linaro.org> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Johan Hovold , Dmitry Baryshkov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=3660; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=4VkCpW8QDcAjyN11pnkcHCM7wZTUs/xHfXdy554thg0=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnDNQatl0+ZaxhTK6HrIKFMggJRViZ3svgxsFMs wG+/0xQq6KJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZwzUGgAKCRAbX0TJAJUV Vnb9D/9vZhhnQGk3sjlZ48o7ve71Lc1FSN3Gyzt2CF8GgV/NQXnb4PUJ6A2EltVC08EUIzZe4/H HE1FIA5YXf5WWm7oWs8yeSF+pk95qZemVeq4hBBm2eaxEmpXotHaCiqWFUXB5/XvDYr9JXQbm8S fW0mXcjlyZhIj74XW94KIRKvUJAXFjuhpiVNzDQCf2ffYf4UZb5YlMD2V9M7gG7b+xf1YDfL14c 2h612YmPx+Xq4ClKSI9Nl4W5CO8R1KfCVcxbBmI6por3uBiFakAVASfeYbWkM+0aartN74GCtm3 N8lknpdsqLfLJQiX5lrcRCnoBj8ct5NtTd7Sqiw/qw6+AK0df5p+44AXT2ruyvyh6cdOo/MIe9Q qsxlOnMEfPV8RKhpTzWeepTYPB5AmJYjiYjhJ19oi6u4Y14na6fHf2+Wlm8REc9YrekvN+YSWTc d43Vni9tlxluSiH4cT+cR1AzFA9eiWSuM1uQc22lzmejZbGjZ6d8HvUavFZ1IKhbdXgxccNd+z/ D6pT1hstMjS5TZzdWGzU2kUUmH56NtxZcFDCiMLrghqh9EBFqy84Vw+D/pBsuCzhoprfqV/+zVG cnTHk8DTm04Mc8QNmWRAVNcW0lGUJs5a0d0NAMEEIvIsZbbYnrpLLgkvzQlcvJuRDeKxRmdwf8m NtbX3Rdth9pCGvQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Describe the two SHDC v5 controllers found on x1e80100 platform. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 102 +++++++++++++++++++++++++++++= ++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 0e6802c1d2d8375987c614ec69c440e2f38d25c6..2d0befd6ba0ea11fdf2305d23c0= cd8743de303dc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3887,6 +3887,108 @@ lpass_lpicx_noc: interconnect@7430000 { #interconnect-cells =3D <2>; }; =20 + sdhc_2: mmc@8804000 { + compatible =3D "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x08804000 0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "core", "xo"; + iommus =3D <&apps_smmu 0x520 0>; + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + interconnects =3D <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + bus-width =3D <4>; + dma-coherent; + + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + sdhc_4: mmc@8844000 { + compatible =3D "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x08844000 0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC4_AHB_CLK>, + <&gcc GCC_SDCC4_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "core", "xo"; + iommus =3D <&apps_smmu 0x160 0>; + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc4_opp_table>; + + interconnects =3D <&aggre2_noc MASTER_SDCC_4 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_4 0>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + bus-width =3D <4>; + dma-coherent; + + status =3D "disabled"; + + sdhc4_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_2_hsphy: phy@88e0000 { compatible =3D "qcom,x1e80100-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; --=20 2.34.1