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[79.45.239.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b7ee0afsm10969352f8f.102.2024.10.14.03.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 03:09:37 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 14 Oct 2024 12:08:08 +0200 Subject: [PATCH v6 2/8] dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-2-eeef0c1e0e56@baylibre.com> References: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-0-eeef0c1e0e56@baylibre.com> In-Reply-To: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-0-eeef0c1e0e56@baylibre.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com, Mark Brown , Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Add a new compatible and related bindigns for the fpga-based "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the generic AXI "DAC" IP, intended to control ad3552r and similar chips, mainly to reach high speed transfer rates using a QSPI DDR (dobule-data-rate) interface. The ad3552r device is defined as a child of the AXI DAC, that in this case is acting as an SPI controller. Note, #io-backend is present because it is possible (in theory anyway) to use a separate controller for the control path than that used for the datapath. Signed-off-by: Angelo Dureghello --- .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 56 ++++++++++++++++++= ++-- 1 file changed, 53 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml index a55e9bfc66d7..2b7e16717219 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml @@ -19,11 +19,13 @@ description: | memory via DMA into the DAC. =20 https://wiki.analog.com/resources/fpga/docs/axi_dac_ip + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html =20 properties: compatible: enum: - adi,axi-dac-9.1.b + - adi,axi-ad3552r =20 reg: maxItems: 1 @@ -36,7 +38,14 @@ properties: - const: tx =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: s_axi_aclk + - const: dac_clk =20 '#io-backend-cells': const: 0 @@ -47,7 +56,16 @@ required: - reg - clocks =20 -additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: adi,axi-ad3552r + then: + $ref: /schemas/spi/spi-controller.yaml# + +unevaluatedProperties: false =20 examples: - | @@ -57,6 +75,38 @@ examples: dmas =3D <&tx_dma 0>; dma-names =3D "tx"; #io-backend-cells =3D <0>; - clocks =3D <&axi_clk>; + clocks =3D <&clkc 15>; + clock-names =3D "s_axi_aclk"; + }; + + - | + #include + axi_dac: spi@44a70000 { + compatible =3D "adi,axi-ad3552r"; + reg =3D <0x44a70000 0x1000>; + dmas =3D <&dac_tx_dma 0>; + dma-names =3D "tx"; + #io-backend-cells =3D <0>; + clocks =3D <&clkc 15>, <&ref_clk>; + clock-names =3D "s_axi_aclk", "dac_clk"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + dac@0 { + compatible =3D "adi,ad3552r"; + reg =3D <0>; + reset-gpios =3D <&gpio0 92 GPIO_ACTIVE_HIGH>; + io-backends =3D <&axi_dac>; + spi-max-frequency =3D <66000000>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + adi,output-range-microvolt =3D <(-10000000) (10000000)>; + }; + }; }; ... --=20 2.45.0.rc1