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[79.45.239.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b7ee0afsm10969352f8f.102.2024.10.14.03.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 03:09:35 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 14 Oct 2024 12:08:07 +0200 Subject: [PATCH v6 1/8] dt-bindings: iio: dac: ad3552r: add iio backend support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-1-eeef0c1e0e56@baylibre.com> References: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-0-eeef0c1e0e56@baylibre.com> In-Reply-To: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-0-eeef0c1e0e56@baylibre.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com, Mark Brown , Angelo Dureghello , Conor Dooley X-Mailer: b4 0.14.1 From: Angelo Dureghello There is a version of AXI DAC IP block (for FPGAs) that provides a physical QSPI bus for AD3552R and similar chips, so supporting spi-controller functionalities. For this case, the binding is modified to include some additional properties. Acked-by: Conor Dooley Signed-off-by: Angelo Dureghello --- Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index 41fe00034742..2d2561a52683 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -60,6 +60,12 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] =20 + io-backends: + description: The iio backend reference. + Device can be optionally connected to the "axi-ad3552r IP" fpga-based + QSPI + DDR (Double Data Rate) controller to reach high speed transfe= rs. + maxItems: 1 + '#address-cells': const: 1 =20 @@ -128,6 +134,7 @@ patternProperties: - custom-output-range-config =20 allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: --=20 2.45.0.rc1