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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e49a7e5e7sm5611109b3a.179.2024.10.14.10.54.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 10:54:30 -0700 (PDT) From: Drew Fustini Date: Mon, 14 Oct 2024 10:54:19 -0700 Subject: [PATCH 2/8] riscv: dts: thead: Add TH1520 GPIO ranges Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241014-th1520-pinctrl-dts-v1-2-268592ca786e@tenstorrent.com> References: <20241014-th1520-pinctrl-dts-v1-0-268592ca786e@tenstorrent.com> In-Reply-To: <20241014-th1520-pinctrl-dts-v1-0-268592ca786e@tenstorrent.com> To: Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Thomas Bonnefille , Kanak Shilledar Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add gpio-ranges properties to the TH1520 device tree, so user space can change basic pinconf settings for GPIOs and are not allowed to use pads already used by other functions. Adjust number of GPIOs available for the different controllers. Acked-by: Linus Walleij Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 93c17f52fbe9..9c6cbb4fc3d7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -335,6 +335,7 @@ portc: gpio-controller@0 { gpio-controller; #gpio-cells =3D <2>; ngpios =3D <32>; + gpio-ranges =3D <&padctrl0_apsys 0 0 32>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; @@ -353,7 +354,8 @@ portd: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; - ngpios =3D <32>; + ngpios =3D <23>; + gpio-ranges =3D <&padctrl0_apsys 0 32 23>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; @@ -380,6 +382,7 @@ porta: gpio-controller@0 { gpio-controller; #gpio-cells =3D <2>; ngpios =3D <32>; + gpio-ranges =3D <&padctrl1_apsys 0 0 32>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; @@ -398,7 +401,8 @@ portb: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; - ngpios =3D <32>; + ngpios =3D <31>; + gpio-ranges =3D <&padctrl1_apsys 0 32 31>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; @@ -551,7 +555,8 @@ porte: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; - ngpios =3D <32>; + ngpios =3D <16>; + gpio-ranges =3D <&padctrl_aosys 0 9 16>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; @@ -576,7 +581,8 @@ portf: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; - ngpios =3D <32>; + ngpios =3D <23>; + gpio-ranges =3D <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; --=20 2.34.1