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Mon, 14 Oct 2024 09:08:03 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49E9819u014732 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Oct 2024 09:08:01 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 14 Oct 2024 02:07:57 -0700 From: Dikshita Agarwal Date: Mon, 14 Oct 2024 14:37:26 +0530 Subject: [PATCH v4 05/28] media: iris: implement video firmware load/unload Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241014-qcom-video-iris-v4-v4-5-c5eaa4e9ab9e@quicinc.com> References: <20241014-qcom-video-iris-v4-v4-0-c5eaa4e9ab9e@quicinc.com> In-Reply-To: <20241014-qcom-video-iris-v4-v4-0-c5eaa4e9ab9e@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Philipp Zabel CC: Hans Verkuil , Sebastian Fricke , , , , , Dikshita Agarwal X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Firmware is loaded as part of core initialization and unloaded as part of core de-initialization. Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/Kconfig | 2 + drivers/media/platform/qcom/iris/Makefile | 1 + drivers/media/platform/qcom/iris/iris_core.c | 8 ++ drivers/media/platform/qcom/iris/iris_firmware.c | 108 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_firmware.h | 14 +++ .../platform/qcom/iris/iris_platform_common.h | 12 +++ .../platform/qcom/iris/iris_platform_sm8550.c | 10 ++ 7 files changed, 155 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platf= orm/qcom/iris/Kconfig index 8debddec87a5..f92cc7fe9378 100644 --- a/drivers/media/platform/qcom/iris/Kconfig +++ b/drivers/media/platform/qcom/iris/Kconfig @@ -3,6 +3,8 @@ config VIDEO_QCOM_IRIS depends on VIDEO_DEV depends on ARCH_QCOM || COMPILE_TEST select V4L2_MEM2MEM_DEV + select QCOM_MDT_LOADER if ARCH_QCOM + select QCOM_SCM help This is a V4L2 driver for Qualcomm iris video accelerator hardware. It accelerates decoding operations on various diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 93711f108a77..6906caa2c481 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -1,4 +1,5 @@ iris-objs +=3D iris_core.o \ + iris_firmware.o \ iris_hfi_gen1_command.o \ iris_hfi_gen2_command.o \ iris_hfi_queue.o \ diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 360a54909ef6..8c7d53c57086 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -4,11 +4,13 @@ */ =20 #include "iris_core.h" +#include "iris_firmware.h" #include "iris_state.h" =20 void iris_core_deinit(struct iris_core *core) { mutex_lock(&core->lock); + iris_fw_unload(core); iris_hfi_queues_deinit(core); core->state =3D IRIS_CORE_DEINIT; mutex_unlock(&core->lock); @@ -33,10 +35,16 @@ int iris_core_init(struct iris_core *core) if (ret) goto error; =20 + ret =3D iris_fw_load(core); + if (ret) + goto error_queue_deinit; + mutex_unlock(&core->lock); =20 return 0; =20 +error_queue_deinit: + iris_hfi_queues_deinit(core); error: core->state =3D IRIS_CORE_DEINIT; exit: diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c new file mode 100644 index 000000000000..58a0f532b862 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include +#include +#include +#include + +#include "iris_core.h" +#include "iris_firmware.h" + +#define MAX_FIRMWARE_NAME_SIZE 128 + +static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n= ame) +{ + u32 pas_id =3D core->iris_platform_data->pas_id; + const struct firmware *firmware =3D NULL; + struct device *dev =3D core->dev; + struct reserved_mem *rmem; + struct device_node *node; + phys_addr_t mem_phys; + size_t res_size; + ssize_t fw_size; + void *mem_virt; + int ret; + + if (strlen(fw_name) >=3D MAX_FIRMWARE_NAME_SIZE - 4) + return -EINVAL; + + node =3D of_parse_phandle(dev->of_node, "memory-region", 0); + if (!node) + return -EINVAL; + + rmem =3D of_reserved_mem_lookup(node); + if (!rmem) { + ret =3D -EINVAL; + goto err_put_node; + } + + mem_phys =3D rmem->base; + res_size =3D rmem->size; + + ret =3D request_firmware(&firmware, fw_name, dev); + if (ret) + goto err_put_node; + + fw_size =3D qcom_mdt_get_size(firmware); + if (fw_size < 0 || res_size < (size_t)fw_size) { + ret =3D -EINVAL; + goto err_release_fw; + } + + mem_virt =3D memremap(mem_phys, res_size, MEMREMAP_WC); + if (!mem_virt) + goto err_release_fw; + + ret =3D qcom_mdt_load(dev, firmware, fw_name, + pas_id, mem_virt, mem_phys, res_size, NULL); + if (ret) + goto err_mem_unmap; + + ret =3D qcom_scm_pas_auth_and_reset(pas_id); + if (ret) + goto err_mem_unmap; + + return ret; + +err_mem_unmap: + memunmap(mem_virt); +err_release_fw: + release_firmware(firmware); +err_put_node: + of_node_put(node); + + return ret; +} + +int iris_fw_load(struct iris_core *core) +{ + struct tz_cp_config *cp_config =3D core->iris_platform_data->tz_cp_config= _data; + int ret; + + ret =3D iris_load_fw_to_memory(core, core->iris_platform_data->fwname); + if (ret) { + dev_err(core->dev, "firmware download failed\n"); + return -ENOMEM; + } + + ret =3D qcom_scm_mem_protect_video_var(cp_config->cp_start, + cp_config->cp_size, + cp_config->cp_nonpixel_start, + cp_config->cp_nonpixel_size); + if (ret) { + dev_err(core->dev, "protect memory failed\n"); + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + return ret; + } + + return ret; +} + +int iris_fw_unload(struct iris_core *core) +{ + return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); +} diff --git a/drivers/media/platform/qcom/iris/iris_firmware.h b/drivers/med= ia/platform/qcom/iris/iris_firmware.h new file mode 100644 index 000000000000..8d4f6b7f75c5 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_firmware.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _IRIS_FIRMWARE_H_ +#define _IRIS_FIRMWARE_H_ + +struct iris_core; + +int iris_fw_load(struct iris_core *core); +int iris_fw_unload(struct iris_core *core); + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index dac64ec4bf03..04bef37b7b77 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -6,6 +6,8 @@ #ifndef _IRIS_PLATFORM_COMMON_H_ #define _IRIS_PLATFORM_COMMON_H_ =20 +#define IRIS_PAS_ID 9 + extern struct iris_platform_data sm8550_data; =20 enum platform_clk_type { @@ -19,6 +21,13 @@ struct platform_clk_data { const char *clk_name; }; =20 +struct tz_cp_config { + u32 cp_start; + u32 cp_size; + u32 cp_nonpixel_start; + u32 cp_nonpixel_size; +}; + struct iris_platform_data { struct iris_inst *(*get_instance)(void); const struct icc_info *icc_tbl; @@ -32,6 +41,9 @@ struct iris_platform_data { const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; u64 dma_mask; + const char *fwname; + u32 pas_id; + struct tz_cp_config *tz_cp_config_data; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.c index 9b305b8e2110..96d9d6e816a0 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c @@ -24,6 +24,13 @@ static const struct platform_clk_data sm8550_clk_table[]= =3D { {IRIS_HW_CLK, "vcodec0_core" }, }; =20 +static struct tz_cp_config tz_cp_config_sm8550 =3D { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, +}; + struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .icc_tbl =3D sm8550_icc_table, @@ -37,4 +44,7 @@ struct iris_platform_data sm8550_data =3D { .clk_tbl =3D sm8550_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), .dma_mask =3D GENMASK(31, 29) - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .pas_id =3D IRIS_PAS_ID, + .tz_cp_config_data =3D &tz_cp_config_sm8550, }; --=20 2.34.1